1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8544ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_BOOKE 1 /* BOOKE */ 16 #define CONFIG_E500 1 /* BOOKE e500 family */ 17 #define CONFIG_MPC8544 1 18 #define CONFIG_MPC8544DS 1 19 20 #ifndef CONFIG_SYS_TEXT_BASE 21 #define CONFIG_SYS_TEXT_BASE 0xfff80000 22 #endif 23 24 #define CONFIG_PCI1 1 /* PCI controller 1 */ 25 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 26 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 27 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 28 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 29 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 30 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 32 33 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 34 35 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 36 #define CONFIG_ENV_OVERWRITE 37 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 38 39 #ifndef __ASSEMBLY__ 40 extern unsigned long get_board_sys_clk(unsigned long dummy); 41 #endif 42 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 43 44 /* 45 * These can be toggled for performance analysis, otherwise use default. 46 */ 47 #define CONFIG_L2_CACHE /* toggle L2 cache */ 48 #define CONFIG_BTB /* toggle branch predition */ 49 50 /* 51 * Only possible on E500 Version 2 or newer cores. 52 */ 53 #define CONFIG_ENABLE_36BIT_PHYS 1 54 55 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 56 #define CONFIG_SYS_MEMTEST_END 0x00400000 57 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 58 59 #define CONFIG_SYS_CCSRBAR 0xe0000000 60 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 61 62 /* DDR Setup */ 63 #define CONFIG_SYS_FSL_DDR2 64 #undef CONFIG_FSL_DDR_INTERACTIVE 65 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 66 #define CONFIG_DDR_SPD 67 68 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 69 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 70 71 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 72 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 73 #define CONFIG_VERY_BIG_RAM 74 75 #define CONFIG_NUM_DDR_CONTROLLERS 1 76 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 77 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 78 79 /* I2C addresses of SPD EEPROMs */ 80 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 81 82 /* Make sure required options are set */ 83 #ifndef CONFIG_SPD_EEPROM 84 #error ("CONFIG_SPD_EEPROM is required") 85 #endif 86 87 #undef CONFIG_CLOCKS_IN_MHZ 88 89 /* 90 * Memory map 91 * 92 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 93 * 94 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 95 * 96 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 97 * 98 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 99 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 100 * 101 * Localbus cacheable 102 * 103 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 104 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 105 * 106 * Localbus non-cacheable 107 * 108 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 109 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 110 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 111 * 112 */ 113 114 /* 115 * Local Bus Definitions 116 */ 117 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ 118 119 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 120 121 #define CONFIG_SYS_BR0_PRELIM 0xff801001 122 #define CONFIG_SYS_BR1_PRELIM 0xfe801001 123 124 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 125 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 126 127 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 128 129 #define CONFIG_SYS_FLASH_QUIET_TEST 130 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 131 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 132 #undef CONFIG_SYS_FLASH_CHECKSUM 133 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 134 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 135 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 136 137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 138 139 #define CONFIG_FLASH_CFI_DRIVER 140 #define CONFIG_SYS_FLASH_CFI 141 #define CONFIG_SYS_FLASH_EMPTY_INFO 142 143 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 144 145 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ 146 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 147 148 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ 149 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 150 151 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 152 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 153 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 154 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 155 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 156 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 157 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 158 * register */ 159 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 160 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 161 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 162 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 163 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 164 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 165 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 166 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 167 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 168 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 169 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 170 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ 171 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 172 #define PIXIS_VSPEED2_TSEC1SER 0x2 173 #define PIXIS_VSPEED2_TSEC3SER 0x1 174 #define PIXIS_VCFGEN1_TSEC1SER 0x20 175 #define PIXIS_VCFGEN1_TSEC3SER 0x40 176 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) 177 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) 178 179 #define CONFIG_SYS_INIT_RAM_LOCK 1 180 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ 181 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 182 183 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 184 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 185 186 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 187 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 188 189 /* Serial Port - controlled on board with jumper J8 190 * open - index 2 191 * shorted - index 1 192 */ 193 #define CONFIG_CONS_INDEX 1 194 #define CONFIG_SYS_NS16550_SERIAL 195 #define CONFIG_SYS_NS16550_REG_SIZE 1 196 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 197 198 #define CONFIG_SYS_BAUDRATE_TABLE \ 199 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 200 201 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 202 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 203 204 /* I2C */ 205 #define CONFIG_SYS_I2C 206 #define CONFIG_SYS_I2C_FSL 207 #define CONFIG_SYS_FSL_I2C_SPEED 400000 208 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 209 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 210 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 211 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 212 213 /* 214 * General PCI 215 * Memory space is mapped 1-1, but I/O space must start from 0. 216 */ 217 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ 218 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 219 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ 220 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 221 222 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 223 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 224 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 225 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 226 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 227 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 228 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 229 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 230 231 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 232 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 233 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 234 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 235 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 236 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 237 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 238 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 239 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 240 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 241 242 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 243 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 244 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 245 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 246 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 247 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 248 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 249 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 250 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 251 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 252 253 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 254 #define CONFIG_SYS_PCIE3_NAME "ULI" 255 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 256 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 257 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 258 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ 259 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ 260 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 261 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ 262 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ 263 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 264 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 265 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 266 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ 267 268 #if defined(CONFIG_PCI) 269 270 /*PCIE video card used*/ 271 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 272 273 /*PCI video card used*/ 274 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 275 276 /* video */ 277 278 #if defined(CONFIG_VIDEO) 279 #define CONFIG_BIOSEMU 280 #define CONFIG_ATI_RADEON_FB 281 #define CONFIG_VIDEO_LOGO 282 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 283 #endif 284 285 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 286 287 #undef CONFIG_EEPRO100 288 #undef CONFIG_TULIP 289 290 #ifndef CONFIG_PCI_PNP 291 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 292 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 293 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 294 #endif 295 296 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 297 #define CONFIG_DOS_PARTITION 298 #define CONFIG_SCSI_AHCI 299 300 #ifdef CONFIG_SCSI_AHCI 301 #define CONFIG_LIBATA 302 #define CONFIG_SATA_ULI5288 303 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 304 #define CONFIG_SYS_SCSI_MAX_LUN 1 305 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 306 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 307 #endif /* SCSCI */ 308 309 #endif /* CONFIG_PCI */ 310 311 #if defined(CONFIG_TSEC_ENET) 312 313 #define CONFIG_MII 1 /* MII PHY management */ 314 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 315 #define CONFIG_TSEC1 1 316 #define CONFIG_TSEC1_NAME "eTSEC1" 317 #define CONFIG_TSEC3 1 318 #define CONFIG_TSEC3_NAME "eTSEC3" 319 320 #define CONFIG_PIXIS_SGMII_CMD 321 #define CONFIG_FSL_SGMII_RISER 1 322 #define SGMII_RISER_PHY_OFFSET 0x1c 323 324 #define TSEC1_PHY_ADDR 0 325 #define TSEC3_PHY_ADDR 1 326 327 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 328 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 329 330 #define TSEC1_PHYIDX 0 331 #define TSEC3_PHYIDX 0 332 333 #define CONFIG_ETHPRIME "eTSEC1" 334 335 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 336 #endif /* CONFIG_TSEC_ENET */ 337 338 /* 339 * Environment 340 */ 341 #define CONFIG_ENV_IS_IN_FLASH 1 342 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 343 #define CONFIG_ENV_ADDR 0xfff80000 344 #else 345 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) 346 #endif 347 #define CONFIG_ENV_SIZE 0x2000 348 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ 349 350 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 351 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 352 353 /* 354 * BOOTP options 355 */ 356 #define CONFIG_BOOTP_BOOTFILESIZE 357 #define CONFIG_BOOTP_BOOTPATH 358 #define CONFIG_BOOTP_GATEWAY 359 #define CONFIG_BOOTP_HOSTNAME 360 361 /* 362 * Command line configuration. 363 */ 364 #define CONFIG_CMD_IRQ 365 #define CONFIG_CMD_REGINFO 366 367 #if defined(CONFIG_PCI) 368 #define CONFIG_CMD_PCI 369 #define CONFIG_SCSI 370 #endif 371 372 /* 373 * USB 374 */ 375 #define CONFIG_USB_EHCI 376 377 #ifdef CONFIG_USB_EHCI 378 #define CONFIG_USB_EHCI_PCI 379 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 380 #define CONFIG_PCI_EHCI_DEVICE 0 381 #endif 382 383 #undef CONFIG_WATCHDOG /* watchdog disabled */ 384 385 /* 386 * Miscellaneous configurable options 387 */ 388 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 389 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 390 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 391 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 392 #if defined(CONFIG_CMD_KGDB) 393 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 394 #else 395 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 396 #endif 397 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 398 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 399 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 400 401 /* 402 * For booting Linux, the board info and command line data 403 * have to be in the first 64 MB of memory, since this is 404 * the maximum mapped by the Linux kernel during initialization. 405 */ 406 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 407 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 408 409 #if defined(CONFIG_CMD_KGDB) 410 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 411 #endif 412 413 /* 414 * Environment Configuration 415 */ 416 417 /* The mac addresses for all ethernet interface */ 418 #if defined(CONFIG_TSEC_ENET) 419 #define CONFIG_HAS_ETH0 420 #define CONFIG_HAS_ETH1 421 #endif 422 423 #define CONFIG_IPADDR 192.168.1.251 424 425 #define CONFIG_HOSTNAME 8544ds_unknown 426 #define CONFIG_ROOTPATH "/nfs/mpc85xx" 427 #define CONFIG_BOOTFILE "8544ds/uImage.uboot" 428 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ 429 430 #define CONFIG_SERVERIP 192.168.1.1 431 #define CONFIG_GATEWAYIP 192.168.1.1 432 #define CONFIG_NETMASK 255.255.0.0 433 434 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 435 436 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 437 438 #define CONFIG_BAUDRATE 115200 439 440 #define CONFIG_EXTRA_ENV_SETTINGS \ 441 "netdev=eth0\0" \ 442 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 443 "tftpflash=tftpboot $loadaddr $uboot; " \ 444 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 445 " +$filesize; " \ 446 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 447 " +$filesize; " \ 448 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 449 " $filesize; " \ 450 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 451 " +$filesize; " \ 452 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 453 " $filesize\0" \ 454 "consoledev=ttyS0\0" \ 455 "ramdiskaddr=2000000\0" \ 456 "ramdiskfile=8544ds/ramdisk.uboot\0" \ 457 "fdtaddr=1e00000\0" \ 458 "fdtfile=8544ds/mpc8544ds.dtb\0" \ 459 "bdev=sda3\0" 460 461 #define CONFIG_NFSBOOTCOMMAND \ 462 "setenv bootargs root=/dev/nfs rw " \ 463 "nfsroot=$serverip:$rootpath " \ 464 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 465 "console=$consoledev,$baudrate $othbootargs;" \ 466 "tftp $loadaddr $bootfile;" \ 467 "tftp $fdtaddr $fdtfile;" \ 468 "bootm $loadaddr - $fdtaddr" 469 470 #define CONFIG_RAMBOOTCOMMAND \ 471 "setenv bootargs root=/dev/ram rw " \ 472 "console=$consoledev,$baudrate $othbootargs;" \ 473 "tftp $ramdiskaddr $ramdiskfile;" \ 474 "tftp $loadaddr $bootfile;" \ 475 "tftp $fdtaddr $fdtfile;" \ 476 "bootm $loadaddr $ramdiskaddr $fdtaddr" 477 478 #define CONFIG_BOOTCOMMAND \ 479 "setenv bootargs root=/dev/$bdev rw " \ 480 "console=$consoledev,$baudrate $othbootargs;" \ 481 "tftp $loadaddr $bootfile;" \ 482 "tftp $fdtaddr $fdtfile;" \ 483 "bootm $loadaddr - $fdtaddr" 484 485 #endif /* __CONFIG_H */ 486