1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8540ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_MPC8540 1 /* MPC8540 specific */ 42 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ 43 44 #define CONFIG_PCI 45 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 46 #define CONFIG_ENV_OVERWRITE 47 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 48 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 49 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 50 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 51 52 53 /* 54 * sysclk for MPC85xx 55 * 56 * Two valid values are: 57 * 33000000 58 * 66000000 59 * 60 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 61 * is likely the desired value here, so that is now the default. 62 * The board, however, can run at 66MHz. In any event, this value 63 * must match the settings of some switches. Details can be found 64 * in the README.mpc85xxads. 65 */ 66 67 #ifndef CONFIG_SYS_CLK_FREQ 68 #define CONFIG_SYS_CLK_FREQ 33000000 69 #endif 70 71 72 /* 73 * These can be toggled for performance analysis, otherwise use default. 74 */ 75 #define CONFIG_L2_CACHE /* toggle L2 cache */ 76 #define CONFIG_BTB /* toggle branch predition */ 77 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 78 79 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 80 81 #undef CFG_DRAM_TEST /* memory test, takes time */ 82 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 83 #define CFG_MEMTEST_END 0x00400000 84 85 86 /* 87 * Base addresses -- Note these are effective addresses where the 88 * actual resources get mapped (not physical addresses) 89 */ 90 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 91 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 92 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 93 94 95 /* 96 * DDR Setup 97 */ 98 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 99 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 100 101 #if defined(CONFIG_SPD_EEPROM) 102 /* 103 * Determine DDR configuration from I2C interface. 104 */ 105 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 106 107 #else 108 /* 109 * Manually set up DDR parameters 110 */ 111 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ 112 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 113 #define CFG_DDR_CS0_CONFIG 0x80000002 114 #define CFG_DDR_TIMING_1 0x37344321 115 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 116 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 117 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 118 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 119 #endif 120 121 122 /* 123 * SDRAM on the Local Bus 124 */ 125 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 126 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 127 128 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 129 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ 130 131 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 132 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 133 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 134 #undef CFG_FLASH_CHECKSUM 135 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 136 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 137 138 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 139 140 141 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 142 #define CFG_RAMBOOT 143 #else 144 #undef CFG_RAMBOOT 145 #endif 146 147 148 #undef CONFIG_CLOCKS_IN_MHZ 149 150 151 /* 152 * Local Bus Definitions 153 */ 154 155 /* 156 * Base Register 2 and Option Register 2 configure SDRAM. 157 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 158 * 159 * For BR2, need: 160 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 161 * port-size = 32-bits = BR2[19:20] = 11 162 * no parity checking = BR2[21:22] = 00 163 * SDRAM for MSEL = BR2[24:26] = 011 164 * Valid = BR[31] = 1 165 * 166 * 0 4 8 12 16 20 24 28 167 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 168 * 169 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 170 * FIXME: the top 17 bits of BR2. 171 */ 172 173 #define CFG_BR2_PRELIM 0xf0001861 174 175 /* 176 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 177 * 178 * For OR2, need: 179 * 64MB mask for AM, OR2[0:7] = 1111 1100 180 * XAM, OR2[17:18] = 11 181 * 9 columns OR2[19-21] = 010 182 * 13 rows OR2[23-25] = 100 183 * EAD set for extra time OR[31] = 1 184 * 185 * 0 4 8 12 16 20 24 28 186 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 187 */ 188 189 #define CFG_OR2_PRELIM 0xfc006901 190 191 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 192 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 193 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 194 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 195 196 /* 197 * LSDMR masks 198 */ 199 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 200 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 201 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 202 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 203 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 204 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 205 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 206 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 207 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 208 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 209 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 210 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 211 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 212 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 213 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 214 215 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 216 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 217 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 218 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 219 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 220 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 221 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 222 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 223 224 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ 225 | CFG_LBC_LSDMR_RFCR5 \ 226 | CFG_LBC_LSDMR_PRETOACT3 \ 227 | CFG_LBC_LSDMR_ACTTORW3 \ 228 | CFG_LBC_LSDMR_BL8 \ 229 | CFG_LBC_LSDMR_WRC2 \ 230 | CFG_LBC_LSDMR_CL3 \ 231 | CFG_LBC_LSDMR_RFEN \ 232 ) 233 234 /* 235 * SDRAM Controller configuration sequence. 236 */ 237 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 238 | CFG_LBC_LSDMR_OP_PCHALL) 239 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 240 | CFG_LBC_LSDMR_OP_ARFRSH) 241 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 242 | CFG_LBC_LSDMR_OP_ARFRSH) 243 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 244 | CFG_LBC_LSDMR_OP_MRW) 245 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 246 | CFG_LBC_LSDMR_OP_NORMAL) 247 248 249 /* 250 * 32KB, 8-bit wide for ADS config reg 251 */ 252 #define CFG_BR4_PRELIM 0xf8000801 253 #define CFG_OR4_PRELIM 0xffffe1f1 254 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) 255 256 #define CONFIG_L1_INIT_RAM 257 #define CFG_INIT_RAM_LOCK 1 258 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 259 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 260 261 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 262 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 263 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 264 265 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 266 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 267 268 /* Serial Port */ 269 #define CONFIG_CONS_INDEX 1 270 #undef CONFIG_SERIAL_SOFTWARE_FIFO 271 #define CFG_NS16550 272 #define CFG_NS16550_SERIAL 273 #define CFG_NS16550_REG_SIZE 1 274 #define CFG_NS16550_CLK get_bus_freq(0) 275 276 #define CFG_BAUDRATE_TABLE \ 277 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 278 279 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 280 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 281 282 /* Use the HUSH parser */ 283 #define CFG_HUSH_PARSER 284 #ifdef CFG_HUSH_PARSER 285 #define CFG_PROMPT_HUSH_PS2 "> " 286 #endif 287 288 /* I2C */ 289 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 290 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 291 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 292 #define CFG_I2C_SLAVE 0x7F 293 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 294 295 /* RapidIO MMU */ 296 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 297 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 298 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 299 300 /* 301 * General PCI 302 * Addresses are mapped 1-1. 303 */ 304 #define CFG_PCI1_MEM_BASE 0x80000000 305 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 306 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 307 #define CFG_PCI1_IO_BASE 0xe2000000 308 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 309 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 310 311 #if defined(CONFIG_PCI) 312 313 #define CONFIG_NET_MULTI 314 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 315 316 #undef CONFIG_EEPRO100 317 #undef CONFIG_TULIP 318 319 #if !defined(CONFIG_PCI_PNP) 320 #define PCI_ENET0_IOADDR 0xe0000000 321 #define PCI_ENET0_MEMADDR 0xe0000000 322 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 323 #endif 324 325 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 326 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 327 328 #endif /* CONFIG_PCI */ 329 330 331 #if defined(CONFIG_TSEC_ENET) 332 333 #ifndef CONFIG_NET_MULTI 334 #define CONFIG_NET_MULTI 1 335 #endif 336 337 #define CONFIG_MII 1 /* MII PHY management */ 338 #define CONFIG_MPC85XX_TSEC1 1 339 #define CONFIG_MPC85XX_TSEC2 1 340 #define TSEC1_PHY_ADDR 0 341 #define TSEC2_PHY_ADDR 1 342 #define TSEC1_PHYIDX 0 343 #define TSEC2_PHYIDX 0 344 345 #define CONFIG_MPC85XX_FEC 1 346 #define FEC_PHY_ADDR 3 347 #define FEC_PHYIDX 0 348 349 #define CONFIG_ETHPRIME "MOTO ENET0" 350 351 #endif /* CONFIG_TSEC_ENET */ 352 353 354 /* 355 * Environment 356 */ 357 #ifndef CFG_RAMBOOT 358 #define CFG_ENV_IS_IN_FLASH 1 359 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 360 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 361 #define CFG_ENV_SIZE 0x2000 362 #else 363 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 364 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 365 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 366 #define CFG_ENV_SIZE 0x2000 367 #endif 368 369 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 370 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 371 372 #if defined(CFG_RAMBOOT) 373 #if defined(CONFIG_PCI) 374 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 375 | CFG_CMD_PING \ 376 | CFG_CMD_PCI \ 377 | CFG_CMD_I2C) \ 378 & \ 379 ~(CFG_CMD_ENV \ 380 | CFG_CMD_LOADS)) 381 #else 382 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 383 | CFG_CMD_PING \ 384 | CFG_CMD_I2C) \ 385 & \ 386 ~(CFG_CMD_ENV \ 387 | CFG_CMD_LOADS)) 388 #endif 389 #else 390 #if defined(CONFIG_PCI) 391 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 392 | CFG_CMD_PCI \ 393 | CFG_CMD_PING \ 394 | CFG_CMD_I2C) 395 #else 396 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 397 | CFG_CMD_PING \ 398 | CFG_CMD_I2C) 399 #endif 400 #endif 401 402 #include <cmd_confdefs.h> 403 404 #undef CONFIG_WATCHDOG /* watchdog disabled */ 405 406 /* 407 * Miscellaneous configurable options 408 */ 409 #define CFG_LONGHELP /* undef to save memory */ 410 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 411 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 412 413 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 414 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 415 #else 416 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 417 #endif 418 419 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 420 #define CFG_MAXARGS 16 /* max number of command args */ 421 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 422 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 423 424 /* 425 * For booting Linux, the board info and command line data 426 * have to be in the first 8 MB of memory, since this is 427 * the maximum mapped by the Linux kernel during initialization. 428 */ 429 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 430 431 /* Cache Configuration */ 432 #define CFG_DCACHE_SIZE 32768 433 #define CFG_CACHELINE_SIZE 32 434 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 435 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 436 #endif 437 438 /* 439 * Internal Definitions 440 * 441 * Boot Flags 442 */ 443 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 444 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 445 446 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 447 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 448 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 449 #endif 450 451 452 /* 453 * Environment Configuration 454 */ 455 456 /* The mac addresses for all ethernet interface */ 457 #if defined(CONFIG_TSEC_ENET) 458 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 459 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 460 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 461 #endif 462 463 #define CONFIG_IPADDR 192.168.1.253 464 465 #define CONFIG_HOSTNAME unknown 466 #define CONFIG_ROOTPATH /nfsroot 467 #define CONFIG_BOOTFILE your.uImage 468 469 #define CONFIG_SERVERIP 192.168.1.1 470 #define CONFIG_GATEWAYIP 192.168.1.1 471 #define CONFIG_NETMASK 255.255.255.0 472 473 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 474 475 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 476 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 477 478 #define CONFIG_BAUDRATE 115200 479 480 #define CONFIG_EXTRA_ENV_SETTINGS \ 481 "netdev=eth0\0" \ 482 "consoledev=ttyS0\0" \ 483 "ramdiskaddr=400000\0" \ 484 "ramdiskfile=your.ramdisk.u-boot\0" 485 486 #define CONFIG_NFSBOOTCOMMAND \ 487 "setenv bootargs root=/dev/nfs rw " \ 488 "nfsroot=$serverip:$rootpath " \ 489 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 490 "console=$consoledev,$baudrate $othbootargs;" \ 491 "tftp $loadaddr $bootfile;" \ 492 "bootm $loadaddr" 493 494 #define CONFIG_RAMBOOTCOMMAND \ 495 "setenv bootargs root=/dev/ram rw " \ 496 "console=$consoledev,$baudrate $othbootargs;" \ 497 "tftp $ramdiskaddr $ramdiskfile;" \ 498 "tftp $loadaddr $bootfile;" \ 499 "bootm $loadaddr $ramdiskaddr" 500 501 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 502 503 #endif /* __CONFIG_H */ 504