1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8540ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_SERVERIP, etc in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 1 /* BOOKE */ 23 #define CONFIG_E500 1 /* BOOKE e500 family */ 24 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ 25 26 /* 27 * default CCARBAR is at 0xff700000 28 * assume U-Boot is less than 0.5MB 29 */ 30 #define CONFIG_SYS_TEXT_BASE 0xfff80000 31 32 #ifndef CONFIG_HAS_FEC 33 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 34 #endif 35 36 #define CONFIG_PCI_INDIRECT_BRIDGE 37 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 38 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 39 #define CONFIG_ENV_OVERWRITE 40 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 41 42 /* 43 * sysclk for MPC85xx 44 * 45 * Two valid values are: 46 * 33000000 47 * 66000000 48 * 49 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 50 * is likely the desired value here, so that is now the default. 51 * The board, however, can run at 66MHz. In any event, this value 52 * must match the settings of some switches. Details can be found 53 * in the README.mpc85xxads. 54 * 55 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 56 * 33MHz to accommodate, based on a PCI pin. 57 * Note that PCI-X won't work at 33MHz. 58 */ 59 60 #ifndef CONFIG_SYS_CLK_FREQ 61 #define CONFIG_SYS_CLK_FREQ 33000000 62 #endif 63 64 /* 65 * These can be toggled for performance analysis, otherwise use default. 66 */ 67 #define CONFIG_L2_CACHE /* toggle L2 cache */ 68 #define CONFIG_BTB /* toggle branch predition */ 69 70 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 71 #define CONFIG_SYS_MEMTEST_END 0x00400000 72 73 #define CONFIG_SYS_CCSRBAR 0xe0000000 74 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 75 76 /* DDR Setup */ 77 #define CONFIG_SYS_FSL_DDR1 78 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 79 #define CONFIG_DDR_SPD 80 #undef CONFIG_FSL_DDR_INTERACTIVE 81 82 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 83 84 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 85 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 86 87 #define CONFIG_NUM_DDR_CONTROLLERS 1 88 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 89 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 90 91 /* I2C addresses of SPD EEPROMs */ 92 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 93 94 /* These are used when DDR doesn't use SPD. */ 95 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 96 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 97 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 98 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 99 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 100 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 101 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 102 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 103 104 /* 105 * SDRAM on the Local Bus 106 */ 107 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 108 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 109 110 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 111 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 112 113 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 114 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 115 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 116 #undef CONFIG_SYS_FLASH_CHECKSUM 117 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 118 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 119 120 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 121 122 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 123 #define CONFIG_SYS_RAMBOOT 124 #else 125 #undef CONFIG_SYS_RAMBOOT 126 #endif 127 128 #define CONFIG_FLASH_CFI_DRIVER 129 #define CONFIG_SYS_FLASH_CFI 130 #define CONFIG_SYS_FLASH_EMPTY_INFO 131 132 #undef CONFIG_CLOCKS_IN_MHZ 133 134 /* 135 * Local Bus Definitions 136 */ 137 138 /* 139 * Base Register 2 and Option Register 2 configure SDRAM. 140 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 141 * 142 * For BR2, need: 143 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 144 * port-size = 32-bits = BR2[19:20] = 11 145 * no parity checking = BR2[21:22] = 00 146 * SDRAM for MSEL = BR2[24:26] = 011 147 * Valid = BR[31] = 1 148 * 149 * 0 4 8 12 16 20 24 28 150 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 151 * 152 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 153 * FIXME: the top 17 bits of BR2. 154 */ 155 156 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 157 158 /* 159 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 160 * 161 * For OR2, need: 162 * 64MB mask for AM, OR2[0:7] = 1111 1100 163 * XAM, OR2[17:18] = 11 164 * 9 columns OR2[19-21] = 010 165 * 13 rows OR2[23-25] = 100 166 * EAD set for extra time OR[31] = 1 167 * 168 * 0 4 8 12 16 20 24 28 169 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 170 */ 171 172 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 173 174 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 175 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 176 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 177 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 178 179 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 180 | LSDMR_RFCR5 \ 181 | LSDMR_PRETOACT3 \ 182 | LSDMR_ACTTORW3 \ 183 | LSDMR_BL8 \ 184 | LSDMR_WRC2 \ 185 | LSDMR_CL3 \ 186 | LSDMR_RFEN \ 187 ) 188 189 /* 190 * SDRAM Controller configuration sequence. 191 */ 192 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 193 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 194 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 195 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 196 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 197 198 /* 199 * 32KB, 8-bit wide for ADS config reg 200 */ 201 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 202 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 203 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 204 205 #define CONFIG_SYS_INIT_RAM_LOCK 1 206 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 207 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 208 209 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 210 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 211 212 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 213 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 214 215 /* Serial Port */ 216 #define CONFIG_CONS_INDEX 1 217 #define CONFIG_SYS_NS16550_SERIAL 218 #define CONFIG_SYS_NS16550_REG_SIZE 1 219 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 220 221 #define CONFIG_SYS_BAUDRATE_TABLE \ 222 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 223 224 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 225 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 226 227 /* 228 * I2C 229 */ 230 #define CONFIG_SYS_I2C 231 #define CONFIG_SYS_I2C_FSL 232 #define CONFIG_SYS_FSL_I2C_SPEED 400000 233 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 234 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 235 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 236 237 /* RapidIO MMU */ 238 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 239 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 240 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 241 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 242 243 /* 244 * General PCI 245 * Memory space is mapped 1-1, but I/O space must start from 0. 246 */ 247 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 248 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 249 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 250 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 251 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 252 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 253 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 254 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 255 256 #if defined(CONFIG_PCI) 257 #undef CONFIG_EEPRO100 258 #undef CONFIG_TULIP 259 260 #if !defined(CONFIG_PCI_PNP) 261 #define PCI_ENET0_IOADDR 0xe0000000 262 #define PCI_ENET0_MEMADDR 0xe0000000 263 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 264 #endif 265 266 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 267 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 268 269 #endif /* CONFIG_PCI */ 270 271 #if defined(CONFIG_TSEC_ENET) 272 273 #define CONFIG_MII 1 /* MII PHY management */ 274 #define CONFIG_TSEC1 1 275 #define CONFIG_TSEC1_NAME "TSEC0" 276 #define CONFIG_TSEC2 1 277 #define CONFIG_TSEC2_NAME "TSEC1" 278 #define TSEC1_PHY_ADDR 0 279 #define TSEC2_PHY_ADDR 1 280 #define TSEC1_PHYIDX 0 281 #define TSEC2_PHYIDX 0 282 #define TSEC1_FLAGS TSEC_GIGABIT 283 #define TSEC2_FLAGS TSEC_GIGABIT 284 285 #if CONFIG_HAS_FEC 286 #define CONFIG_MPC85XX_FEC 1 287 #define CONFIG_MPC85XX_FEC_NAME "FEC" 288 #define FEC_PHY_ADDR 3 289 #define FEC_PHYIDX 0 290 #define FEC_FLAGS 0 291 #endif 292 293 /* Options are: TSEC[0-1], FEC */ 294 #define CONFIG_ETHPRIME "TSEC0" 295 296 #endif /* CONFIG_TSEC_ENET */ 297 298 /* 299 * Environment 300 */ 301 #ifndef CONFIG_SYS_RAMBOOT 302 #define CONFIG_ENV_IS_IN_FLASH 1 303 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 304 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 305 #define CONFIG_ENV_SIZE 0x2000 306 #else 307 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 308 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 309 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 310 #define CONFIG_ENV_SIZE 0x2000 311 #endif 312 313 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 314 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 315 316 /* 317 * BOOTP options 318 */ 319 #define CONFIG_BOOTP_BOOTFILESIZE 320 #define CONFIG_BOOTP_BOOTPATH 321 #define CONFIG_BOOTP_GATEWAY 322 #define CONFIG_BOOTP_HOSTNAME 323 324 /* 325 * Command line configuration. 326 */ 327 #define CONFIG_CMD_IRQ 328 329 #if defined(CONFIG_PCI) 330 #define CONFIG_CMD_PCI 331 #endif 332 333 #undef CONFIG_WATCHDOG /* watchdog disabled */ 334 335 /* 336 * Miscellaneous configurable options 337 */ 338 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 339 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 340 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 341 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 342 343 #if defined(CONFIG_CMD_KGDB) 344 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 345 #else 346 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 347 #endif 348 349 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 350 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 351 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 352 353 /* 354 * For booting Linux, the board info and command line data 355 * have to be in the first 64 MB of memory, since this is 356 * the maximum mapped by the Linux kernel during initialization. 357 */ 358 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 359 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 360 361 #if defined(CONFIG_CMD_KGDB) 362 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 363 #endif 364 365 /* 366 * Environment Configuration 367 */ 368 369 /* The mac addresses for all ethernet interface */ 370 #if defined(CONFIG_TSEC_ENET) 371 #define CONFIG_HAS_ETH0 372 #define CONFIG_HAS_ETH1 373 #define CONFIG_HAS_ETH2 374 #endif 375 376 #define CONFIG_IPADDR 192.168.1.253 377 378 #define CONFIG_HOSTNAME unknown 379 #define CONFIG_ROOTPATH "/nfsroot" 380 #define CONFIG_BOOTFILE "your.uImage" 381 382 #define CONFIG_SERVERIP 192.168.1.1 383 #define CONFIG_GATEWAYIP 192.168.1.1 384 #define CONFIG_NETMASK 255.255.255.0 385 386 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 387 388 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 389 390 #define CONFIG_BAUDRATE 115200 391 392 #define CONFIG_EXTRA_ENV_SETTINGS \ 393 "netdev=eth0\0" \ 394 "consoledev=ttyS0\0" \ 395 "ramdiskaddr=1000000\0" \ 396 "ramdiskfile=your.ramdisk.u-boot\0" \ 397 "fdtaddr=400000\0" \ 398 "fdtfile=your.fdt.dtb\0" 399 400 #define CONFIG_NFSBOOTCOMMAND \ 401 "setenv bootargs root=/dev/nfs rw " \ 402 "nfsroot=$serverip:$rootpath " \ 403 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 404 "console=$consoledev,$baudrate $othbootargs;" \ 405 "tftp $loadaddr $bootfile;" \ 406 "tftp $fdtaddr $fdtfile;" \ 407 "bootm $loadaddr - $fdtaddr" 408 409 #define CONFIG_RAMBOOTCOMMAND \ 410 "setenv bootargs root=/dev/ram rw " \ 411 "console=$consoledev,$baudrate $othbootargs;" \ 412 "tftp $ramdiskaddr $ramdiskfile;" \ 413 "tftp $loadaddr $bootfile;" \ 414 "tftp $fdtaddr $fdtfile;" \ 415 "bootm $loadaddr $ramdiskaddr $fdtaddr" 416 417 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 418 419 #endif /* __CONFIG_H */ 420