1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8540ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_MPC8540 1 /* MPC8540 specific */ 42 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ 43 44 #ifndef CONFIG_HAS_FEC 45 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 46 #endif 47 48 #define CONFIG_PCI 49 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 50 #define CONFIG_ENV_OVERWRITE 51 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 52 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 53 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 54 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 55 56 57 /* 58 * sysclk for MPC85xx 59 * 60 * Two valid values are: 61 * 33000000 62 * 66000000 63 * 64 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 65 * is likely the desired value here, so that is now the default. 66 * The board, however, can run at 66MHz. In any event, this value 67 * must match the settings of some switches. Details can be found 68 * in the README.mpc85xxads. 69 */ 70 71 #ifndef CONFIG_SYS_CLK_FREQ 72 #define CONFIG_SYS_CLK_FREQ 33000000 73 #endif 74 75 76 /* 77 * These can be toggled for performance analysis, otherwise use default. 78 */ 79 #define CONFIG_L2_CACHE /* toggle L2 cache */ 80 #define CONFIG_BTB /* toggle branch predition */ 81 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 82 83 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 84 85 #undef CFG_DRAM_TEST /* memory test, takes time */ 86 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 87 #define CFG_MEMTEST_END 0x00400000 88 89 90 /* 91 * Base addresses -- Note these are effective addresses where the 92 * actual resources get mapped (not physical addresses) 93 */ 94 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 95 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 96 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 97 98 99 /* 100 * DDR Setup 101 */ 102 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 103 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 104 105 #if defined(CONFIG_SPD_EEPROM) 106 /* 107 * Determine DDR configuration from I2C interface. 108 */ 109 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 110 111 #else 112 /* 113 * Manually set up DDR parameters 114 */ 115 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ 116 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 117 #define CFG_DDR_CS0_CONFIG 0x80000002 118 #define CFG_DDR_TIMING_1 0x37344321 119 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 120 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 121 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 122 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 123 #endif 124 125 126 /* 127 * SDRAM on the Local Bus 128 */ 129 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 130 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 131 132 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 133 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ 134 135 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 136 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 137 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 138 #undef CFG_FLASH_CHECKSUM 139 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 140 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 141 142 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 143 144 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 145 #define CFG_RAMBOOT 146 #else 147 #undef CFG_RAMBOOT 148 #endif 149 150 #define CFG_FLASH_CFI_DRIVER 151 #define CFG_FLASH_CFI 152 #define CFG_FLASH_EMPTY_INFO 153 154 #undef CONFIG_CLOCKS_IN_MHZ 155 156 157 /* 158 * Local Bus Definitions 159 */ 160 161 /* 162 * Base Register 2 and Option Register 2 configure SDRAM. 163 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 164 * 165 * For BR2, need: 166 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 167 * port-size = 32-bits = BR2[19:20] = 11 168 * no parity checking = BR2[21:22] = 00 169 * SDRAM for MSEL = BR2[24:26] = 011 170 * Valid = BR[31] = 1 171 * 172 * 0 4 8 12 16 20 24 28 173 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 174 * 175 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 176 * FIXME: the top 17 bits of BR2. 177 */ 178 179 #define CFG_BR2_PRELIM 0xf0001861 180 181 /* 182 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 183 * 184 * For OR2, need: 185 * 64MB mask for AM, OR2[0:7] = 1111 1100 186 * XAM, OR2[17:18] = 11 187 * 9 columns OR2[19-21] = 010 188 * 13 rows OR2[23-25] = 100 189 * EAD set for extra time OR[31] = 1 190 * 191 * 0 4 8 12 16 20 24 28 192 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 193 */ 194 195 #define CFG_OR2_PRELIM 0xfc006901 196 197 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 198 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 199 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 200 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 201 202 /* 203 * LSDMR masks 204 */ 205 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 206 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 207 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 208 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 209 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 210 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 211 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 212 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 213 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 214 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 215 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 216 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 217 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 218 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 219 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 220 221 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 222 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 223 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 224 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 225 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 226 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 227 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 228 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 229 230 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ 231 | CFG_LBC_LSDMR_RFCR5 \ 232 | CFG_LBC_LSDMR_PRETOACT3 \ 233 | CFG_LBC_LSDMR_ACTTORW3 \ 234 | CFG_LBC_LSDMR_BL8 \ 235 | CFG_LBC_LSDMR_WRC2 \ 236 | CFG_LBC_LSDMR_CL3 \ 237 | CFG_LBC_LSDMR_RFEN \ 238 ) 239 240 /* 241 * SDRAM Controller configuration sequence. 242 */ 243 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 244 | CFG_LBC_LSDMR_OP_PCHALL) 245 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 246 | CFG_LBC_LSDMR_OP_ARFRSH) 247 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 248 | CFG_LBC_LSDMR_OP_ARFRSH) 249 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 250 | CFG_LBC_LSDMR_OP_MRW) 251 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 252 | CFG_LBC_LSDMR_OP_NORMAL) 253 254 255 /* 256 * 32KB, 8-bit wide for ADS config reg 257 */ 258 #define CFG_BR4_PRELIM 0xf8000801 259 #define CFG_OR4_PRELIM 0xffffe1f1 260 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) 261 262 #define CONFIG_L1_INIT_RAM 263 #define CFG_INIT_RAM_LOCK 1 264 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 265 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 266 267 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 268 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 269 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 270 271 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 272 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 273 274 /* Serial Port */ 275 #define CONFIG_CONS_INDEX 1 276 #undef CONFIG_SERIAL_SOFTWARE_FIFO 277 #define CFG_NS16550 278 #define CFG_NS16550_SERIAL 279 #define CFG_NS16550_REG_SIZE 1 280 #define CFG_NS16550_CLK get_bus_freq(0) 281 282 #define CFG_BAUDRATE_TABLE \ 283 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 284 285 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 286 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 287 288 /* Use the HUSH parser */ 289 #define CFG_HUSH_PARSER 290 #ifdef CFG_HUSH_PARSER 291 #define CFG_PROMPT_HUSH_PS2 "> " 292 #endif 293 294 /* I2C */ 295 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 296 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 297 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 298 #define CFG_I2C_SLAVE 0x7F 299 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 300 301 /* RapidIO MMU */ 302 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 303 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 304 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 305 306 /* 307 * General PCI 308 * Addresses are mapped 1-1. 309 */ 310 #define CFG_PCI1_MEM_BASE 0x80000000 311 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 312 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 313 #define CFG_PCI1_IO_BASE 0xe2000000 314 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 315 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 316 317 #if defined(CONFIG_PCI) 318 319 #define CONFIG_NET_MULTI 320 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 321 322 #undef CONFIG_EEPRO100 323 #undef CONFIG_TULIP 324 325 #if !defined(CONFIG_PCI_PNP) 326 #define PCI_ENET0_IOADDR 0xe0000000 327 #define PCI_ENET0_MEMADDR 0xe0000000 328 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 329 #endif 330 331 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 332 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 333 334 #endif /* CONFIG_PCI */ 335 336 337 #if defined(CONFIG_TSEC_ENET) 338 339 #ifndef CONFIG_NET_MULTI 340 #define CONFIG_NET_MULTI 1 341 #endif 342 343 #define CONFIG_MII 1 /* MII PHY management */ 344 #define CONFIG_MPC85XX_TSEC1 1 345 #define CONFIG_MPC85XX_TSEC2 1 346 #define TSEC1_PHY_ADDR 0 347 #define TSEC2_PHY_ADDR 1 348 #define TSEC1_PHYIDX 0 349 #define TSEC2_PHYIDX 0 350 351 352 #if CONFIG_HAS_FEC 353 #define CONFIG_MPC85XX_FEC 1 354 #define FEC_PHY_ADDR 3 355 #define FEC_PHYIDX 0 356 #endif 357 358 #define CONFIG_ETHPRIME "MOTO ENET0" 359 360 #endif /* CONFIG_TSEC_ENET */ 361 362 363 /* 364 * Environment 365 */ 366 #ifndef CFG_RAMBOOT 367 #define CFG_ENV_IS_IN_FLASH 1 368 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 369 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 370 #define CFG_ENV_SIZE 0x2000 371 #else 372 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 373 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 374 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 375 #define CFG_ENV_SIZE 0x2000 376 #endif 377 378 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 379 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 380 381 #if defined(CFG_RAMBOOT) 382 #if defined(CONFIG_PCI) 383 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 384 | CFG_CMD_PING \ 385 | CFG_CMD_PCI \ 386 | CFG_CMD_I2C) \ 387 & \ 388 ~(CFG_CMD_ENV \ 389 | CFG_CMD_LOADS)) 390 #else 391 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 392 | CFG_CMD_PING \ 393 | CFG_CMD_I2C) \ 394 & \ 395 ~(CFG_CMD_ENV \ 396 | CFG_CMD_LOADS)) 397 #endif 398 #else 399 #if defined(CONFIG_PCI) 400 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 401 | CFG_CMD_PCI \ 402 | CFG_CMD_PING \ 403 | CFG_CMD_I2C) 404 #else 405 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 406 | CFG_CMD_PING \ 407 | CFG_CMD_I2C) 408 #endif 409 #endif 410 411 #include <cmd_confdefs.h> 412 413 #undef CONFIG_WATCHDOG /* watchdog disabled */ 414 415 /* 416 * Miscellaneous configurable options 417 */ 418 #define CFG_LONGHELP /* undef to save memory */ 419 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 420 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 421 422 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 423 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 424 #else 425 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 426 #endif 427 428 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 429 #define CFG_MAXARGS 16 /* max number of command args */ 430 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 431 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 432 433 /* 434 * For booting Linux, the board info and command line data 435 * have to be in the first 8 MB of memory, since this is 436 * the maximum mapped by the Linux kernel during initialization. 437 */ 438 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 439 440 /* Cache Configuration */ 441 #define CFG_DCACHE_SIZE 32768 442 #define CFG_CACHELINE_SIZE 32 443 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 444 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 445 #endif 446 447 /* 448 * Internal Definitions 449 * 450 * Boot Flags 451 */ 452 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 453 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 454 455 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 456 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 457 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 458 #endif 459 460 461 /* 462 * Environment Configuration 463 */ 464 465 /* The mac addresses for all ethernet interface */ 466 #if defined(CONFIG_TSEC_ENET) 467 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 468 #define CONFIG_HAS_ETH1 469 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 470 #define CONFIG_HAS_ETH2 471 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 472 #endif 473 474 #define CONFIG_IPADDR 192.168.1.253 475 476 #define CONFIG_HOSTNAME unknown 477 #define CONFIG_ROOTPATH /nfsroot 478 #define CONFIG_BOOTFILE your.uImage 479 480 #define CONFIG_SERVERIP 192.168.1.1 481 #define CONFIG_GATEWAYIP 192.168.1.1 482 #define CONFIG_NETMASK 255.255.255.0 483 484 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 485 486 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 487 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 488 489 #define CONFIG_BAUDRATE 115200 490 491 #define CONFIG_EXTRA_ENV_SETTINGS \ 492 "netdev=eth0\0" \ 493 "consoledev=ttyS0\0" \ 494 "ramdiskaddr=400000\0" \ 495 "ramdiskfile=your.ramdisk.u-boot\0" 496 497 #define CONFIG_NFSBOOTCOMMAND \ 498 "setenv bootargs root=/dev/nfs rw " \ 499 "nfsroot=$serverip:$rootpath " \ 500 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 501 "console=$consoledev,$baudrate $othbootargs;" \ 502 "tftp $loadaddr $bootfile;" \ 503 "bootm $loadaddr" 504 505 #define CONFIG_RAMBOOTCOMMAND \ 506 "setenv bootargs root=/dev/ram rw " \ 507 "console=$consoledev,$baudrate $othbootargs;" \ 508 "tftp $ramdiskaddr $ramdiskfile;" \ 509 "tftp $loadaddr $bootfile;" \ 510 "bootm $loadaddr $ramdiskaddr" 511 512 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 513 514 #endif /* __CONFIG_H */ 515