1 /* 2 * Copyright 2007-2009,2010-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8536ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #include "../board/freescale/common/ics307_clk.h" 31 32 #ifdef CONFIG_36BIT 33 #define CONFIG_PHYS_64BIT 1 34 #endif 35 36 #ifdef CONFIG_NAND 37 #define CONFIG_NAND_U_BOOT 1 38 #define CONFIG_RAMBOOT_NAND 1 39 #ifdef CONFIG_NAND_SPL 40 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 41 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 42 #else 43 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 44 #endif /* CONFIG_NAND_SPL */ 45 #endif 46 47 #ifdef CONFIG_SDCARD 48 #define CONFIG_RAMBOOT_SDCARD 1 49 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 50 #endif 51 52 #ifdef CONFIG_SPIFLASH 53 #define CONFIG_RAMBOOT_SPIFLASH 1 54 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 55 #endif 56 57 #ifndef CONFIG_SYS_TEXT_BASE 58 #define CONFIG_SYS_TEXT_BASE 0xeff80000 59 #endif 60 61 #ifndef CONFIG_SYS_MONITOR_BASE 62 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 63 #endif 64 65 /* High Level Configuration Options */ 66 #define CONFIG_BOOKE 1 /* BOOKE */ 67 #define CONFIG_E500 1 /* BOOKE e500 family */ 68 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 69 #define CONFIG_MPC8536 1 70 #define CONFIG_MPC8536DS 1 71 72 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 73 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 74 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 75 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 76 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 77 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 78 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 79 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 80 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 81 82 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 83 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ 84 85 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 86 #define CONFIG_ENV_OVERWRITE 87 88 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 89 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 90 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 91 92 /* 93 * These can be toggled for performance analysis, otherwise use default. 94 */ 95 #define CONFIG_L2_CACHE /* toggle L2 cache */ 96 #define CONFIG_BTB /* toggle branch predition */ 97 98 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 99 100 #define CONFIG_ENABLE_36BIT_PHYS 1 101 102 #ifdef CONFIG_PHYS_64BIT 103 #define CONFIG_ADDR_MAP 1 104 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 105 #endif 106 107 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 108 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 109 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 110 111 /* 112 * Config the L2 Cache as L2 SRAM 113 */ 114 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 115 #ifdef CONFIG_PHYS_64BIT 116 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 117 #else 118 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 119 #endif 120 #define CONFIG_SYS_L2_SIZE (512 << 10) 121 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 122 123 /* 124 * Base addresses -- Note these are effective addresses where the 125 * actual resources get mapped (not physical addresses) 126 */ 127 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 128 #ifdef CONFIG_PHYS_64BIT 129 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 130 #else 131 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 132 #endif 133 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 134 135 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) 136 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR 137 #else 138 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 139 #endif 140 141 /* DDR Setup */ 142 #define CONFIG_VERY_BIG_RAM 143 #define CONFIG_FSL_DDR2 144 #undef CONFIG_FSL_DDR_INTERACTIVE 145 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 146 #define CONFIG_DDR_SPD 147 148 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 149 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 150 151 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 152 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 153 154 #define CONFIG_NUM_DDR_CONTROLLERS 1 155 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 156 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 157 158 /* I2C addresses of SPD EEPROMs */ 159 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 160 #define CONFIG_SYS_SPD_BUS_NUM 1 161 162 /* These are used when DDR doesn't use SPD. */ 163 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 164 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 165 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 166 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 167 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 168 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 169 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 170 #define CONFIG_SYS_DDR_MODE_1 0x00480432 171 #define CONFIG_SYS_DDR_MODE_2 0x00000000 172 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 173 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 174 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 175 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 176 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 177 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 178 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 179 180 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 181 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 182 #define CONFIG_SYS_DDR_SBE 0x00010000 183 184 /* Make sure required options are set */ 185 #ifndef CONFIG_SPD_EEPROM 186 #error ("CONFIG_SPD_EEPROM is required") 187 #endif 188 189 #undef CONFIG_CLOCKS_IN_MHZ 190 191 192 /* 193 * Memory map -- xxx -this is wrong, needs updating 194 * 195 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 196 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 197 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 198 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 199 * 200 * Localbus cacheable (TBD) 201 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 202 * 203 * Localbus non-cacheable 204 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 205 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 206 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 207 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 208 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 209 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 210 */ 211 212 /* 213 * Local Bus Definitions 214 */ 215 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 216 #ifdef CONFIG_PHYS_64BIT 217 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 218 #else 219 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 220 #endif 221 222 #define CONFIG_FLASH_BR_PRELIM \ 223 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ 224 | BR_PS_16 | BR_V) 225 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 226 227 #define CONFIG_SYS_BR1_PRELIM \ 228 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 229 | BR_PS_16 | BR_V) 230 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 231 232 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 233 CONFIG_SYS_FLASH_BASE_PHYS } 234 #define CONFIG_SYS_FLASH_QUIET_TEST 235 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 236 237 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 238 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 239 #undef CONFIG_SYS_FLASH_CHECKSUM 240 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 241 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 242 243 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \ 244 defined(CONFIG_RAMBOOT_SPIFLASH) 245 #define CONFIG_SYS_RAMBOOT 246 #define CONFIG_SYS_EXTRA_ENV_RELOC 247 #else 248 #undef CONFIG_SYS_RAMBOOT 249 #endif 250 251 #define CONFIG_FLASH_CFI_DRIVER 252 #define CONFIG_SYS_FLASH_CFI 253 #define CONFIG_SYS_FLASH_EMPTY_INFO 254 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 255 256 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 257 258 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 259 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 260 #ifdef CONFIG_PHYS_64BIT 261 #define PIXIS_BASE_PHYS 0xfffdf0000ull 262 #else 263 #define PIXIS_BASE_PHYS PIXIS_BASE 264 #endif 265 266 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 267 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 268 269 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 270 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 271 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 272 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 273 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 274 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 275 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 276 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 277 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 278 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 279 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 280 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 281 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 282 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 283 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 284 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 285 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 286 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 287 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 288 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 289 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 290 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 291 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 292 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 293 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 294 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 295 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 296 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 297 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 298 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 299 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 300 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 301 #define PIXIS_LED 0x25 /* LED Register */ 302 303 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 304 305 /* old pixis referenced names */ 306 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 307 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 308 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 309 310 #define CONFIG_SYS_INIT_RAM_LOCK 1 311 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 312 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 313 314 #define CONFIG_SYS_GBL_DATA_OFFSET \ 315 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 316 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 317 318 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 319 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 320 321 #ifndef CONFIG_NAND_SPL 322 #define CONFIG_SYS_NAND_BASE 0xffa00000 323 #ifdef CONFIG_PHYS_64BIT 324 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 325 #else 326 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 327 #endif 328 #else 329 #define CONFIG_SYS_NAND_BASE 0xfff00000 330 #ifdef CONFIG_PHYS_64BIT 331 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 332 #else 333 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 334 #endif 335 #endif 336 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 337 CONFIG_SYS_NAND_BASE + 0x40000, \ 338 CONFIG_SYS_NAND_BASE + 0x80000, \ 339 CONFIG_SYS_NAND_BASE + 0xC0000} 340 #define CONFIG_SYS_MAX_NAND_DEVICE 4 341 #define CONFIG_MTD_NAND_VERIFY_WRITE 342 #define CONFIG_CMD_NAND 1 343 #define CONFIG_NAND_FSL_ELBC 1 344 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 345 346 /* NAND boot: 4K NAND loader config */ 347 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 348 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 349 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 350 #define CONFIG_SYS_NAND_U_BOOT_START \ 351 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 352 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 353 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 354 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 355 356 /* NAND flash config */ 357 #define CONFIG_NAND_BR_PRELIM \ 358 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 359 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 360 | BR_PS_8 /* Port Size = 8 bit */ \ 361 | BR_MS_FCM /* MSEL = FCM */ \ 362 | BR_V) /* valid */ 363 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 364 | OR_FCM_PGS /* Large Page*/ \ 365 | OR_FCM_CSCT \ 366 | OR_FCM_CST \ 367 | OR_FCM_CHT \ 368 | OR_FCM_SCY_1 \ 369 | OR_FCM_TRLX \ 370 | OR_FCM_EHTR) 371 372 #ifdef CONFIG_RAMBOOT_NAND 373 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 374 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 375 #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 376 #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 377 #else 378 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 379 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 380 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 381 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 382 #endif 383 384 #define CONFIG_SYS_BR4_PRELIM \ 385 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \ 386 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 387 | BR_PS_8 /* Port Size = 8 bit */ \ 388 | BR_MS_FCM /* MSEL = FCM */ \ 389 | BR_V) /* valid */ 390 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 391 #define CONFIG_SYS_BR5_PRELIM \ 392 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \ 393 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 394 | BR_PS_8 /* Port Size = 8 bit */ \ 395 | BR_MS_FCM /* MSEL = FCM */ \ 396 | BR_V) /* valid */ 397 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 398 399 #define CONFIG_SYS_BR6_PRELIM \ 400 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \ 401 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 402 | BR_PS_8 /* Port Size = 8 bit */ \ 403 | BR_MS_FCM /* MSEL = FCM */ \ 404 | BR_V) /* valid */ 405 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 406 407 /* Serial Port - controlled on board with jumper J8 408 * open - index 2 409 * shorted - index 1 410 */ 411 #define CONFIG_CONS_INDEX 1 412 #define CONFIG_SYS_NS16550 413 #define CONFIG_SYS_NS16550_SERIAL 414 #define CONFIG_SYS_NS16550_REG_SIZE 1 415 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 416 #ifdef CONFIG_NAND_SPL 417 #define CONFIG_NS16550_MIN_FUNCTIONS 418 #endif 419 420 #define CONFIG_SYS_BAUDRATE_TABLE \ 421 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 422 423 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 424 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 425 426 /* Use the HUSH parser */ 427 #define CONFIG_SYS_HUSH_PARSER 428 #ifdef CONFIG_SYS_HUSH_PARSER 429 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 430 #endif 431 432 /* 433 * Pass open firmware flat tree 434 */ 435 #define CONFIG_OF_LIBFDT 1 436 #define CONFIG_OF_BOARD_SETUP 1 437 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 438 439 /* 440 * I2C 441 */ 442 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 443 #define CONFIG_HARD_I2C /* I2C with hardware support */ 444 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 445 #define CONFIG_I2C_MULTI_BUS 446 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 447 #define CONFIG_SYS_I2C_SLAVE 0x7F 448 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ 449 #define CONFIG_SYS_I2C_OFFSET 0x3000 450 #define CONFIG_SYS_I2C2_OFFSET 0x3100 451 452 /* 453 * I2C2 EEPROM 454 */ 455 #define CONFIG_ID_EEPROM 456 #ifdef CONFIG_ID_EEPROM 457 #define CONFIG_SYS_I2C_EEPROM_NXID 458 #endif 459 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 460 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 461 #define CONFIG_SYS_EEPROM_BUS_NUM 1 462 463 /* 464 * General PCI 465 * Memory space is mapped 1-1, but I/O space must start from 0. 466 */ 467 468 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 469 #ifdef CONFIG_PHYS_64BIT 470 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 471 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 472 #else 473 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 474 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 475 #endif 476 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 477 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 478 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 479 #ifdef CONFIG_PHYS_64BIT 480 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 481 #else 482 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 483 #endif 484 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 485 486 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 487 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 488 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 489 #ifdef CONFIG_PHYS_64BIT 490 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 491 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 492 #else 493 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 494 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 495 #endif 496 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 497 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 498 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 499 #ifdef CONFIG_PHYS_64BIT 500 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 501 #else 502 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 503 #endif 504 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 505 506 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 507 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 508 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 509 #ifdef CONFIG_PHYS_64BIT 510 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 511 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 512 #else 513 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 514 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 515 #endif 516 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 517 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 518 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 519 #ifdef CONFIG_PHYS_64BIT 520 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 521 #else 522 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 523 #endif 524 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 525 526 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 527 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 528 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 529 #ifdef CONFIG_PHYS_64BIT 530 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 531 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 532 #else 533 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 534 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 535 #endif 536 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 537 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 538 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 539 #ifdef CONFIG_PHYS_64BIT 540 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 541 #else 542 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 543 #endif 544 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 545 546 #if defined(CONFIG_PCI) 547 548 #define CONFIG_NET_MULTI 549 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 550 551 /*PCIE video card used*/ 552 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 553 554 /*PCI video card used*/ 555 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 556 557 /* video */ 558 #define CONFIG_VIDEO 559 560 #if defined(CONFIG_VIDEO) 561 #define CONFIG_BIOSEMU 562 #define CONFIG_CFB_CONSOLE 563 #define CONFIG_VIDEO_SW_CURSOR 564 #define CONFIG_VGA_AS_SINGLE_DEVICE 565 #define CONFIG_ATI_RADEON_FB 566 #define CONFIG_VIDEO_LOGO 567 /*#define CONFIG_CONSOLE_CURSOR*/ 568 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 569 #endif 570 571 #undef CONFIG_EEPRO100 572 #undef CONFIG_TULIP 573 #undef CONFIG_RTL8139 574 575 #ifndef CONFIG_PCI_PNP 576 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 577 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 578 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 579 #endif 580 581 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 582 583 #endif /* CONFIG_PCI */ 584 585 /* SATA */ 586 #define CONFIG_LIBATA 587 #define CONFIG_FSL_SATA 588 589 #define CONFIG_SYS_SATA_MAX_DEVICE 2 590 #define CONFIG_SATA1 591 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 592 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 593 #define CONFIG_SATA2 594 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 595 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 596 597 #ifdef CONFIG_FSL_SATA 598 #define CONFIG_LBA48 599 #define CONFIG_CMD_SATA 600 #define CONFIG_DOS_PARTITION 601 #define CONFIG_CMD_EXT2 602 #endif 603 604 #if defined(CONFIG_TSEC_ENET) 605 606 #ifndef CONFIG_NET_MULTI 607 #define CONFIG_NET_MULTI 1 608 #endif 609 610 #define CONFIG_MII 1 /* MII PHY management */ 611 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 612 #define CONFIG_TSEC1 1 613 #define CONFIG_TSEC1_NAME "eTSEC1" 614 #define CONFIG_TSEC3 1 615 #define CONFIG_TSEC3_NAME "eTSEC3" 616 617 #define CONFIG_FSL_SGMII_RISER 1 618 #define SGMII_RISER_PHY_OFFSET 0x1c 619 620 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 621 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 622 623 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 624 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 625 626 #define TSEC1_PHYIDX 0 627 #define TSEC3_PHYIDX 0 628 629 #define CONFIG_ETHPRIME "eTSEC1" 630 631 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 632 633 #endif /* CONFIG_TSEC_ENET */ 634 635 /* 636 * Environment 637 */ 638 639 #if defined(CONFIG_SYS_RAMBOOT) 640 #if defined(CONFIG_RAMBOOT_NAND) 641 #define CONFIG_ENV_IS_IN_NAND 1 642 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 643 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 644 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 645 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 646 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 647 #define CONFIG_ENV_SIZE 0x2000 648 #endif 649 #else 650 #define CONFIG_ENV_IS_IN_FLASH 1 651 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 652 #define CONFIG_ENV_ADDR 0xfff80000 653 #else 654 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 655 #endif 656 #define CONFIG_ENV_SIZE 0x2000 657 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 658 #endif 659 660 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 661 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 662 663 /* 664 * Command line configuration. 665 */ 666 #include <config_cmd_default.h> 667 668 #define CONFIG_CMD_IRQ 669 #define CONFIG_CMD_PING 670 #define CONFIG_CMD_I2C 671 #define CONFIG_CMD_MII 672 #define CONFIG_CMD_ELF 673 #define CONFIG_CMD_IRQ 674 #define CONFIG_CMD_SETEXPR 675 #define CONFIG_CMD_REGINFO 676 677 #if defined(CONFIG_PCI) 678 #define CONFIG_CMD_PCI 679 #define CONFIG_CMD_NET 680 #endif 681 682 #undef CONFIG_WATCHDOG /* watchdog disabled */ 683 684 #define CONFIG_MMC 1 685 686 #ifdef CONFIG_MMC 687 #define CONFIG_FSL_ESDHC 688 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 689 #define CONFIG_CMD_MMC 690 #define CONFIG_GENERIC_MMC 691 #define CONFIG_CMD_EXT2 692 #define CONFIG_CMD_FAT 693 #define CONFIG_DOS_PARTITION 694 #endif 695 696 /* 697 * Miscellaneous configurable options 698 */ 699 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 700 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 701 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 702 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 703 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 704 #if defined(CONFIG_CMD_KGDB) 705 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 706 #else 707 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 708 #endif 709 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 710 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 711 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 712 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 713 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 714 715 /* 716 * For booting Linux, the board info and command line data 717 * have to be in the first 16 MB of memory, since this is 718 * the maximum mapped by the Linux kernel during initialization. 719 */ 720 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ 721 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 722 723 #if defined(CONFIG_CMD_KGDB) 724 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 725 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 726 #endif 727 728 /* 729 * Environment Configuration 730 */ 731 732 /* The mac addresses for all ethernet interface */ 733 #if defined(CONFIG_TSEC_ENET) 734 #define CONFIG_HAS_ETH0 735 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 736 #define CONFIG_HAS_ETH1 737 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 738 #define CONFIG_HAS_ETH2 739 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 740 #define CONFIG_HAS_ETH3 741 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 742 #endif 743 744 #define CONFIG_IPADDR 192.168.1.254 745 746 #define CONFIG_HOSTNAME unknown 747 #define CONFIG_ROOTPATH /opt/nfsroot 748 #define CONFIG_BOOTFILE uImage 749 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 750 751 #define CONFIG_SERVERIP 192.168.1.1 752 #define CONFIG_GATEWAYIP 192.168.1.1 753 #define CONFIG_NETMASK 255.255.255.0 754 755 /* default location for tftp and bootm */ 756 #define CONFIG_LOADADDR 1000000 757 758 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 759 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 760 761 #define CONFIG_BAUDRATE 115200 762 763 #define CONFIG_EXTRA_ENV_SETTINGS \ 764 "netdev=eth0\0" \ 765 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 766 "tftpflash=tftpboot $loadaddr $uboot; " \ 767 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 768 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 769 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 770 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 771 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 772 "consoledev=ttyS0\0" \ 773 "ramdiskaddr=2000000\0" \ 774 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 775 "fdtaddr=c00000\0" \ 776 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 777 "bdev=sda3\0" \ 778 "usb_phy_type=ulpi\0" 779 780 #define CONFIG_HDBOOT \ 781 "setenv bootargs root=/dev/$bdev rw " \ 782 "console=$consoledev,$baudrate $othbootargs;" \ 783 "tftp $loadaddr $bootfile;" \ 784 "tftp $fdtaddr $fdtfile;" \ 785 "bootm $loadaddr - $fdtaddr" 786 787 #define CONFIG_NFSBOOTCOMMAND \ 788 "setenv bootargs root=/dev/nfs rw " \ 789 "nfsroot=$serverip:$rootpath " \ 790 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 791 "console=$consoledev,$baudrate $othbootargs;" \ 792 "tftp $loadaddr $bootfile;" \ 793 "tftp $fdtaddr $fdtfile;" \ 794 "bootm $loadaddr - $fdtaddr" 795 796 #define CONFIG_RAMBOOTCOMMAND \ 797 "setenv bootargs root=/dev/ram rw " \ 798 "console=$consoledev,$baudrate $othbootargs;" \ 799 "tftp $ramdiskaddr $ramdiskfile;" \ 800 "tftp $loadaddr $bootfile;" \ 801 "tftp $fdtaddr $fdtfile;" \ 802 "bootm $loadaddr $ramdiskaddr $fdtaddr" 803 804 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 805 806 #endif /* __CONFIG_H */ 807