1 /* 2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8536ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 1 18 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 19 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 20 #endif 21 22 #ifdef CONFIG_SPIFLASH 23 #define CONFIG_RAMBOOT_SPIFLASH 1 24 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 26 #endif 27 28 #ifndef CONFIG_SYS_TEXT_BASE 29 #define CONFIG_SYS_TEXT_BASE 0xeff40000 30 #endif 31 32 #ifndef CONFIG_RESET_VECTOR_ADDRESS 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 34 #endif 35 36 #ifndef CONFIG_SYS_MONITOR_BASE 37 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 38 #endif 39 40 /* High Level Configuration Options */ 41 #define CONFIG_BOOKE 1 /* BOOKE */ 42 #define CONFIG_E500 1 /* BOOKE e500 family */ 43 #define CONFIG_MPC8536 1 44 #define CONFIG_MPC8536DS 1 45 46 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 47 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 48 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 49 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 50 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 51 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 52 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 53 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 54 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 55 56 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 57 58 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 59 #define CONFIG_ENV_OVERWRITE 60 61 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 62 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 63 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 64 65 /* 66 * These can be toggled for performance analysis, otherwise use default. 67 */ 68 #define CONFIG_L2_CACHE /* toggle L2 cache */ 69 #define CONFIG_BTB /* toggle branch predition */ 70 71 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 72 73 #define CONFIG_ENABLE_36BIT_PHYS 1 74 75 #ifdef CONFIG_PHYS_64BIT 76 #define CONFIG_ADDR_MAP 1 77 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 78 #endif 79 80 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 81 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 82 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 83 84 /* 85 * Config the L2 Cache as L2 SRAM 86 */ 87 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 88 #ifdef CONFIG_PHYS_64BIT 89 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 90 #else 91 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 92 #endif 93 #define CONFIG_SYS_L2_SIZE (512 << 10) 94 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 95 96 #define CONFIG_SYS_CCSRBAR 0xffe00000 97 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 98 99 #if defined(CONFIG_NAND_SPL) 100 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 101 #endif 102 103 /* DDR Setup */ 104 #define CONFIG_VERY_BIG_RAM 105 #define CONFIG_SYS_FSL_DDR2 106 #undef CONFIG_FSL_DDR_INTERACTIVE 107 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 108 #define CONFIG_DDR_SPD 109 110 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 111 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 112 113 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 114 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 115 116 #define CONFIG_NUM_DDR_CONTROLLERS 1 117 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 118 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 119 120 /* I2C addresses of SPD EEPROMs */ 121 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 122 #define CONFIG_SYS_SPD_BUS_NUM 1 123 124 /* These are used when DDR doesn't use SPD. */ 125 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 126 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 127 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 128 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 129 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 130 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 131 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 132 #define CONFIG_SYS_DDR_MODE_1 0x00480432 133 #define CONFIG_SYS_DDR_MODE_2 0x00000000 134 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 135 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 136 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 137 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 138 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 139 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 140 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 141 142 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 143 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 144 #define CONFIG_SYS_DDR_SBE 0x00010000 145 146 /* Make sure required options are set */ 147 #ifndef CONFIG_SPD_EEPROM 148 #error ("CONFIG_SPD_EEPROM is required") 149 #endif 150 151 #undef CONFIG_CLOCKS_IN_MHZ 152 153 /* 154 * Memory map -- xxx -this is wrong, needs updating 155 * 156 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 157 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 158 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 159 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 160 * 161 * Localbus cacheable (TBD) 162 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 163 * 164 * Localbus non-cacheable 165 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 166 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 167 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 168 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 169 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 170 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 171 */ 172 173 /* 174 * Local Bus Definitions 175 */ 176 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 177 #ifdef CONFIG_PHYS_64BIT 178 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 179 #else 180 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 181 #endif 182 183 #define CONFIG_FLASH_BR_PRELIM \ 184 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 185 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 186 187 #define CONFIG_SYS_BR1_PRELIM \ 188 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 189 | BR_PS_16 | BR_V) 190 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 191 192 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 193 CONFIG_SYS_FLASH_BASE_PHYS } 194 #define CONFIG_SYS_FLASH_QUIET_TEST 195 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 196 197 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 198 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 199 #undef CONFIG_SYS_FLASH_CHECKSUM 200 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 201 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 202 203 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 204 #define CONFIG_SYS_RAMBOOT 205 #define CONFIG_SYS_EXTRA_ENV_RELOC 206 #else 207 #undef CONFIG_SYS_RAMBOOT 208 #endif 209 210 #define CONFIG_FLASH_CFI_DRIVER 211 #define CONFIG_SYS_FLASH_CFI 212 #define CONFIG_SYS_FLASH_EMPTY_INFO 213 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 214 215 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 216 217 #define CONFIG_HWCONFIG /* enable hwconfig */ 218 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 219 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 220 #ifdef CONFIG_PHYS_64BIT 221 #define PIXIS_BASE_PHYS 0xfffdf0000ull 222 #else 223 #define PIXIS_BASE_PHYS PIXIS_BASE 224 #endif 225 226 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 227 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 228 229 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 230 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 231 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 232 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 233 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 234 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 235 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 236 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 237 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 238 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 239 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 240 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 241 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 242 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 243 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 244 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 245 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 246 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 247 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 248 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 249 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 250 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 251 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 252 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 253 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 254 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 255 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 256 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 257 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 258 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 259 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 260 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 261 #define PIXIS_LED 0x25 /* LED Register */ 262 263 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 264 265 /* old pixis referenced names */ 266 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 267 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 268 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 269 270 #define CONFIG_SYS_INIT_RAM_LOCK 1 271 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 272 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 273 274 #define CONFIG_SYS_GBL_DATA_OFFSET \ 275 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 276 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 277 278 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 279 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 280 281 #ifndef CONFIG_NAND_SPL 282 #define CONFIG_SYS_NAND_BASE 0xffa00000 283 #ifdef CONFIG_PHYS_64BIT 284 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 285 #else 286 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 287 #endif 288 #else 289 #define CONFIG_SYS_NAND_BASE 0xfff00000 290 #ifdef CONFIG_PHYS_64BIT 291 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 292 #else 293 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 294 #endif 295 #endif 296 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 297 CONFIG_SYS_NAND_BASE + 0x40000, \ 298 CONFIG_SYS_NAND_BASE + 0x80000, \ 299 CONFIG_SYS_NAND_BASE + 0xC0000} 300 #define CONFIG_SYS_MAX_NAND_DEVICE 4 301 #define CONFIG_CMD_NAND 1 302 #define CONFIG_NAND_FSL_ELBC 1 303 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 304 305 /* NAND boot: 4K NAND loader config */ 306 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 307 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 308 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 309 #define CONFIG_SYS_NAND_U_BOOT_START \ 310 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 311 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 312 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 313 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 314 315 /* NAND flash config */ 316 #define CONFIG_SYS_NAND_BR_PRELIM \ 317 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 318 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 319 | BR_PS_8 /* Port Size = 8 bit */ \ 320 | BR_MS_FCM /* MSEL = FCM */ \ 321 | BR_V) /* valid */ 322 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 323 | OR_FCM_PGS /* Large Page*/ \ 324 | OR_FCM_CSCT \ 325 | OR_FCM_CST \ 326 | OR_FCM_CHT \ 327 | OR_FCM_SCY_1 \ 328 | OR_FCM_TRLX \ 329 | OR_FCM_EHTR) 330 331 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 332 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 333 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 334 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 335 336 #define CONFIG_SYS_BR4_PRELIM \ 337 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 338 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 339 | BR_PS_8 /* Port Size = 8 bit */ \ 340 | BR_MS_FCM /* MSEL = FCM */ \ 341 | BR_V) /* valid */ 342 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 343 #define CONFIG_SYS_BR5_PRELIM \ 344 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 345 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 346 | BR_PS_8 /* Port Size = 8 bit */ \ 347 | BR_MS_FCM /* MSEL = FCM */ \ 348 | BR_V) /* valid */ 349 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 350 351 #define CONFIG_SYS_BR6_PRELIM \ 352 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 353 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 354 | BR_PS_8 /* Port Size = 8 bit */ \ 355 | BR_MS_FCM /* MSEL = FCM */ \ 356 | BR_V) /* valid */ 357 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 358 359 /* Serial Port - controlled on board with jumper J8 360 * open - index 2 361 * shorted - index 1 362 */ 363 #define CONFIG_CONS_INDEX 1 364 #define CONFIG_SYS_NS16550_SERIAL 365 #define CONFIG_SYS_NS16550_REG_SIZE 1 366 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 367 #ifdef CONFIG_NAND_SPL 368 #define CONFIG_NS16550_MIN_FUNCTIONS 369 #endif 370 371 #define CONFIG_SYS_BAUDRATE_TABLE \ 372 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 373 374 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 375 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 376 377 /* 378 * I2C 379 */ 380 #define CONFIG_SYS_I2C 381 #define CONFIG_SYS_I2C_FSL 382 #define CONFIG_SYS_FSL_I2C_SPEED 400000 383 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 384 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 385 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 386 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 387 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 388 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 389 390 /* 391 * I2C2 EEPROM 392 */ 393 #define CONFIG_ID_EEPROM 394 #ifdef CONFIG_ID_EEPROM 395 #define CONFIG_SYS_I2C_EEPROM_NXID 396 #endif 397 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 398 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 399 #define CONFIG_SYS_EEPROM_BUS_NUM 1 400 401 /* 402 * eSPI - Enhanced SPI 403 */ 404 #define CONFIG_HARD_SPI 405 406 #if defined(CONFIG_SPI_FLASH) 407 #define CONFIG_SF_DEFAULT_SPEED 10000000 408 #define CONFIG_SF_DEFAULT_MODE 0 409 #endif 410 411 /* 412 * General PCI 413 * Memory space is mapped 1-1, but I/O space must start from 0. 414 */ 415 416 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 417 #ifdef CONFIG_PHYS_64BIT 418 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 419 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 420 #else 421 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 422 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 423 #endif 424 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 425 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 426 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 427 #ifdef CONFIG_PHYS_64BIT 428 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 429 #else 430 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 431 #endif 432 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 433 434 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 435 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 436 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 437 #ifdef CONFIG_PHYS_64BIT 438 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 439 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 440 #else 441 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 442 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 443 #endif 444 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 445 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 446 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 447 #ifdef CONFIG_PHYS_64BIT 448 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 449 #else 450 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 451 #endif 452 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 453 454 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 455 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 456 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 457 #ifdef CONFIG_PHYS_64BIT 458 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 459 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 460 #else 461 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 462 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 463 #endif 464 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 465 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 466 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 467 #ifdef CONFIG_PHYS_64BIT 468 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 469 #else 470 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 471 #endif 472 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 473 474 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 475 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 476 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 477 #ifdef CONFIG_PHYS_64BIT 478 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 479 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 480 #else 481 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 482 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 483 #endif 484 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 485 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 486 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 487 #ifdef CONFIG_PHYS_64BIT 488 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 489 #else 490 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 491 #endif 492 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 493 494 #if defined(CONFIG_PCI) 495 496 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 497 498 /*PCIE video card used*/ 499 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 500 501 /*PCI video card used*/ 502 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 503 504 /* video */ 505 506 #if defined(CONFIG_VIDEO) 507 #define CONFIG_BIOSEMU 508 #define CONFIG_ATI_RADEON_FB 509 #define CONFIG_VIDEO_LOGO 510 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 511 #endif 512 513 #undef CONFIG_EEPRO100 514 #undef CONFIG_TULIP 515 516 #ifndef CONFIG_PCI_PNP 517 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 518 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 519 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 520 #endif 521 522 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 523 524 #endif /* CONFIG_PCI */ 525 526 /* SATA */ 527 #define CONFIG_LIBATA 528 #define CONFIG_FSL_SATA 529 530 #define CONFIG_SYS_SATA_MAX_DEVICE 2 531 #define CONFIG_SATA1 532 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 533 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 534 #define CONFIG_SATA2 535 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 536 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 537 538 #ifdef CONFIG_FSL_SATA 539 #define CONFIG_LBA48 540 #define CONFIG_CMD_SATA 541 #define CONFIG_DOS_PARTITION 542 #endif 543 544 #if defined(CONFIG_TSEC_ENET) 545 546 #define CONFIG_MII 1 /* MII PHY management */ 547 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 548 #define CONFIG_TSEC1 1 549 #define CONFIG_TSEC1_NAME "eTSEC1" 550 #define CONFIG_TSEC3 1 551 #define CONFIG_TSEC3_NAME "eTSEC3" 552 553 #define CONFIG_FSL_SGMII_RISER 1 554 #define SGMII_RISER_PHY_OFFSET 0x1c 555 556 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 557 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 558 559 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 560 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 561 562 #define TSEC1_PHYIDX 0 563 #define TSEC3_PHYIDX 0 564 565 #define CONFIG_ETHPRIME "eTSEC1" 566 567 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 568 569 #endif /* CONFIG_TSEC_ENET */ 570 571 /* 572 * Environment 573 */ 574 575 #if defined(CONFIG_SYS_RAMBOOT) 576 #if defined(CONFIG_RAMBOOT_SPIFLASH) 577 #define CONFIG_ENV_IS_IN_SPI_FLASH 578 #define CONFIG_ENV_SPI_BUS 0 579 #define CONFIG_ENV_SPI_CS 0 580 #define CONFIG_ENV_SPI_MAX_HZ 10000000 581 #define CONFIG_ENV_SPI_MODE 0 582 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 583 #define CONFIG_ENV_OFFSET 0xF0000 584 #define CONFIG_ENV_SECT_SIZE 0x10000 585 #elif defined(CONFIG_RAMBOOT_SDCARD) 586 #define CONFIG_ENV_IS_IN_MMC 587 #define CONFIG_FSL_FIXED_MMC_LOCATION 588 #define CONFIG_ENV_SIZE 0x2000 589 #define CONFIG_SYS_MMC_ENV_DEV 0 590 #else 591 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 592 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 593 #define CONFIG_ENV_SIZE 0x2000 594 #endif 595 #else 596 #define CONFIG_ENV_IS_IN_FLASH 1 597 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 598 #define CONFIG_ENV_SIZE 0x2000 599 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 600 #endif 601 602 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 603 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 604 605 /* 606 * Command line configuration. 607 */ 608 #define CONFIG_CMD_IRQ 609 #define CONFIG_CMD_IRQ 610 #define CONFIG_CMD_REGINFO 611 612 #if defined(CONFIG_PCI) 613 #define CONFIG_CMD_PCI 614 #endif 615 616 #undef CONFIG_WATCHDOG /* watchdog disabled */ 617 618 #define CONFIG_MMC 1 619 620 #ifdef CONFIG_MMC 621 #define CONFIG_FSL_ESDHC 622 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 623 #define CONFIG_GENERIC_MMC 624 #endif 625 626 /* 627 * USB 628 */ 629 #define CONFIG_HAS_FSL_MPH_USB 630 #ifdef CONFIG_HAS_FSL_MPH_USB 631 #define CONFIG_USB_EHCI 632 633 #ifdef CONFIG_USB_EHCI 634 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 635 #define CONFIG_USB_EHCI_FSL 636 #endif 637 #endif 638 639 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 640 #define CONFIG_DOS_PARTITION 641 #endif 642 643 /* 644 * Miscellaneous configurable options 645 */ 646 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 647 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 648 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 649 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 650 #if defined(CONFIG_CMD_KGDB) 651 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 652 #else 653 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 654 #endif 655 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 656 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 657 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 658 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 659 660 /* 661 * For booting Linux, the board info and command line data 662 * have to be in the first 64 MB of memory, since this is 663 * the maximum mapped by the Linux kernel during initialization. 664 */ 665 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 666 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 667 668 #if defined(CONFIG_CMD_KGDB) 669 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 670 #endif 671 672 /* 673 * Environment Configuration 674 */ 675 676 /* The mac addresses for all ethernet interface */ 677 #if defined(CONFIG_TSEC_ENET) 678 #define CONFIG_HAS_ETH0 679 #define CONFIG_HAS_ETH1 680 #define CONFIG_HAS_ETH2 681 #define CONFIG_HAS_ETH3 682 #endif 683 684 #define CONFIG_IPADDR 192.168.1.254 685 686 #define CONFIG_HOSTNAME unknown 687 #define CONFIG_ROOTPATH "/opt/nfsroot" 688 #define CONFIG_BOOTFILE "uImage" 689 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 690 691 #define CONFIG_SERVERIP 192.168.1.1 692 #define CONFIG_GATEWAYIP 192.168.1.1 693 #define CONFIG_NETMASK 255.255.255.0 694 695 /* default location for tftp and bootm */ 696 #define CONFIG_LOADADDR 1000000 697 698 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 699 700 #define CONFIG_BAUDRATE 115200 701 702 #define CONFIG_EXTRA_ENV_SETTINGS \ 703 "netdev=eth0\0" \ 704 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 705 "tftpflash=tftpboot $loadaddr $uboot; " \ 706 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 707 " +$filesize; " \ 708 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 709 " +$filesize; " \ 710 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 711 " $filesize; " \ 712 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 713 " +$filesize; " \ 714 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 715 " $filesize\0" \ 716 "consoledev=ttyS0\0" \ 717 "ramdiskaddr=2000000\0" \ 718 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 719 "fdtaddr=1e00000\0" \ 720 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 721 "bdev=sda3\0" \ 722 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 723 724 #define CONFIG_HDBOOT \ 725 "setenv bootargs root=/dev/$bdev rw " \ 726 "console=$consoledev,$baudrate $othbootargs;" \ 727 "tftp $loadaddr $bootfile;" \ 728 "tftp $fdtaddr $fdtfile;" \ 729 "bootm $loadaddr - $fdtaddr" 730 731 #define CONFIG_NFSBOOTCOMMAND \ 732 "setenv bootargs root=/dev/nfs rw " \ 733 "nfsroot=$serverip:$rootpath " \ 734 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 735 "console=$consoledev,$baudrate $othbootargs;" \ 736 "tftp $loadaddr $bootfile;" \ 737 "tftp $fdtaddr $fdtfile;" \ 738 "bootm $loadaddr - $fdtaddr" 739 740 #define CONFIG_RAMBOOTCOMMAND \ 741 "setenv bootargs root=/dev/ram rw " \ 742 "console=$consoledev,$baudrate $othbootargs;" \ 743 "tftp $ramdiskaddr $ramdiskfile;" \ 744 "tftp $loadaddr $bootfile;" \ 745 "tftp $fdtaddr $fdtfile;" \ 746 "bootm $loadaddr $ramdiskaddr $fdtaddr" 747 748 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 749 750 #endif /* __CONFIG_H */ 751