1 /* 2 * Copyright 2008-2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8536ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #ifdef CONFIG_MK_36BIT 31 #define CONFIG_PHYS_64BIT 1 32 #endif 33 34 #ifdef CONFIG_MK_NAND 35 #define CONFIG_NAND_U_BOOT 1 36 #define CONFIG_RAMBOOT_NAND 1 37 #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 38 #endif 39 40 /* High Level Configuration Options */ 41 #define CONFIG_BOOKE 1 /* BOOKE */ 42 #define CONFIG_E500 1 /* BOOKE e500 family */ 43 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 44 #define CONFIG_MPC8536 1 45 #define CONFIG_MPC8536DS 1 46 47 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 48 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 49 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 50 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 51 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 52 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 53 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 54 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 55 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 56 57 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 58 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ 59 60 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 61 #define CONFIG_ENV_OVERWRITE 62 63 /* 64 * When initializing flash, if we cannot find the manufacturer ID, 65 * assume this is the AMD flash associated with the CDS board. 66 * This allows booting from a promjet. 67 */ 68 #define CONFIG_ASSUME_AMD_FLASH 69 70 #ifndef __ASSEMBLY__ 71 extern unsigned long get_board_sys_clk(unsigned long dummy); 72 extern unsigned long get_board_ddr_clk(unsigned long dummy); 73 #endif 74 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 75 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) 76 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 77 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 78 from ICS307 instead of switches */ 79 80 /* 81 * These can be toggled for performance analysis, otherwise use default. 82 */ 83 #define CONFIG_L2_CACHE /* toggle L2 cache */ 84 #define CONFIG_BTB /* toggle branch predition */ 85 86 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 87 88 #define CONFIG_ENABLE_36BIT_PHYS 1 89 90 #ifdef CONFIG_PHYS_64BIT 91 #define CONFIG_ADDR_MAP 1 92 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 93 #endif 94 95 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 96 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 97 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 98 99 /* 100 * Config the L2 Cache as L2 SRAM 101 */ 102 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 103 #ifdef CONFIG_PHYS_64BIT 104 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 105 #else 106 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 107 #endif 108 #define CONFIG_SYS_L2_SIZE (512 << 10) 109 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 110 111 /* 112 * Base addresses -- Note these are effective addresses where the 113 * actual resources get mapped (not physical addresses) 114 */ 115 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 116 #ifdef CONFIG_PHYS_64BIT 117 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 118 #else 119 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 120 #endif 121 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 122 123 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) 124 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR 125 #else 126 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 127 #endif 128 129 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) 130 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) 131 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) 132 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) 133 134 /* DDR Setup */ 135 #define CONFIG_VERY_BIG_RAM 136 #define CONFIG_FSL_DDR2 137 #undef CONFIG_FSL_DDR_INTERACTIVE 138 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 139 #define CONFIG_DDR_SPD 140 #undef CONFIG_DDR_DLL 141 142 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 143 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 144 145 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 146 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 147 148 #define CONFIG_NUM_DDR_CONTROLLERS 1 149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 150 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 151 152 /* I2C addresses of SPD EEPROMs */ 153 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 154 #define CONFIG_SYS_SPD_BUS_NUM 1 155 156 /* These are used when DDR doesn't use SPD. */ 157 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 158 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 159 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 160 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 161 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 162 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 163 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 164 #define CONFIG_SYS_DDR_MODE_1 0x00480432 165 #define CONFIG_SYS_DDR_MODE_2 0x00000000 166 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 167 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 168 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 169 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 170 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 171 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 172 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 173 174 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 175 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 176 #define CONFIG_SYS_DDR_SBE 0x00010000 177 178 /* Make sure required options are set */ 179 #ifndef CONFIG_SPD_EEPROM 180 #error ("CONFIG_SPD_EEPROM is required") 181 #endif 182 183 #undef CONFIG_CLOCKS_IN_MHZ 184 185 186 /* 187 * Memory map -- xxx -this is wrong, needs updating 188 * 189 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 190 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 191 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 192 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 193 * 194 * Localbus cacheable (TBD) 195 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 196 * 197 * Localbus non-cacheable 198 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 199 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 200 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 201 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 202 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 203 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 204 */ 205 206 /* 207 * Local Bus Definitions 208 */ 209 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 210 #ifdef CONFIG_PHYS_64BIT 211 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 212 #else 213 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 214 #endif 215 216 #define CONFIG_FLASH_BR_PRELIM \ 217 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ 218 | BR_PS_16 | BR_V) 219 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 220 221 #define CONFIG_SYS_BR1_PRELIM \ 222 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 223 | BR_PS_16 | BR_V) 224 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 225 226 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 227 CONFIG_SYS_FLASH_BASE_PHYS } 228 #define CONFIG_SYS_FLASH_QUIET_TEST 229 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 230 231 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 232 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 233 #undef CONFIG_SYS_FLASH_CHECKSUM 234 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 235 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 236 237 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 238 239 #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) 240 #define CONFIG_SYS_RAMBOOT 241 #else 242 #undef CONFIG_SYS_RAMBOOT 243 #endif 244 245 #define CONFIG_FLASH_CFI_DRIVER 246 #define CONFIG_SYS_FLASH_CFI 247 #define CONFIG_SYS_FLASH_EMPTY_INFO 248 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 249 250 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 251 252 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 253 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 254 #ifdef CONFIG_PHYS_64BIT 255 #define PIXIS_BASE_PHYS 0xfffdf0000ull 256 #else 257 #define PIXIS_BASE_PHYS PIXIS_BASE 258 #endif 259 260 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 261 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 262 263 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 264 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 265 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 266 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 267 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 268 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 269 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 270 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 271 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 272 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 273 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 274 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 275 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 276 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 277 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 278 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 279 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 280 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 281 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 282 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 283 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 284 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 285 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 286 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 287 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 288 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 289 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 290 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 291 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 292 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 293 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 294 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 295 #define PIXIS_LED 0x25 /* LED Register */ 296 297 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 298 299 /* old pixis referenced names */ 300 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 301 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 302 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 303 304 #define CONFIG_SYS_INIT_RAM_LOCK 1 305 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 306 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 307 308 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 309 #define CONFIG_SYS_GBL_DATA_OFFSET \ 310 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 311 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 312 313 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 314 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 315 316 #ifndef CONFIG_NAND_SPL 317 #define CONFIG_SYS_NAND_BASE 0xffa00000 318 #ifdef CONFIG_PHYS_64BIT 319 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 320 #else 321 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 322 #endif 323 #else 324 #define CONFIG_SYS_NAND_BASE 0xfff00000 325 #ifdef CONFIG_PHYS_64BIT 326 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 327 #else 328 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 329 #endif 330 #endif 331 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 332 CONFIG_SYS_NAND_BASE + 0x40000, \ 333 CONFIG_SYS_NAND_BASE + 0x80000, \ 334 CONFIG_SYS_NAND_BASE + 0xC0000} 335 #define CONFIG_SYS_MAX_NAND_DEVICE 4 336 #define CONFIG_MTD_NAND_VERIFY_WRITE 337 #define CONFIG_CMD_NAND 1 338 #define CONFIG_NAND_FSL_ELBC 1 339 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 340 341 /* NAND boot: 4K NAND loader config */ 342 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 343 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 344 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 345 #define CONFIG_SYS_NAND_U_BOOT_START \ 346 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 347 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 348 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 349 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 350 351 /* NAND flash config */ 352 #define CONFIG_NAND_BR_PRELIM \ 353 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 354 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 355 | BR_PS_8 /* Port Size = 8 bit */ \ 356 | BR_MS_FCM /* MSEL = FCM */ \ 357 | BR_V) /* valid */ 358 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 359 | OR_FCM_PGS /* Large Page*/ \ 360 | OR_FCM_CSCT \ 361 | OR_FCM_CST \ 362 | OR_FCM_CHT \ 363 | OR_FCM_SCY_1 \ 364 | OR_FCM_TRLX \ 365 | OR_FCM_EHTR) 366 367 #ifdef CONFIG_RAMBOOT_NAND 368 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 369 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 370 #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 371 #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 372 #else 373 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 374 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 375 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 376 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 377 #endif 378 379 #define CONFIG_SYS_BR4_PRELIM \ 380 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \ 381 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 382 | BR_PS_8 /* Port Size = 8 bit */ \ 383 | BR_MS_FCM /* MSEL = FCM */ \ 384 | BR_V) /* valid */ 385 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 386 #define CONFIG_SYS_BR5_PRELIM \ 387 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \ 388 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 389 | BR_PS_8 /* Port Size = 8 bit */ \ 390 | BR_MS_FCM /* MSEL = FCM */ \ 391 | BR_V) /* valid */ 392 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 393 394 #define CONFIG_SYS_BR6_PRELIM \ 395 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \ 396 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 397 | BR_PS_8 /* Port Size = 8 bit */ \ 398 | BR_MS_FCM /* MSEL = FCM */ \ 399 | BR_V) /* valid */ 400 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 401 402 /* Serial Port - controlled on board with jumper J8 403 * open - index 2 404 * shorted - index 1 405 */ 406 #define CONFIG_CONS_INDEX 1 407 #undef CONFIG_SERIAL_SOFTWARE_FIFO 408 #define CONFIG_SYS_NS16550 409 #define CONFIG_SYS_NS16550_SERIAL 410 #define CONFIG_SYS_NS16550_REG_SIZE 1 411 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 412 413 #define CONFIG_SYS_BAUDRATE_TABLE \ 414 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 415 416 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 417 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 418 419 /* Use the HUSH parser */ 420 #define CONFIG_SYS_HUSH_PARSER 421 #ifdef CONFIG_SYS_HUSH_PARSER 422 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 423 #endif 424 425 /* 426 * Pass open firmware flat tree 427 */ 428 #define CONFIG_OF_LIBFDT 1 429 #define CONFIG_OF_BOARD_SETUP 1 430 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 431 432 #define CONFIG_SYS_64BIT_STRTOUL 1 433 #define CONFIG_SYS_64BIT_VSPRINTF 1 434 435 436 /* 437 * I2C 438 */ 439 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 440 #define CONFIG_HARD_I2C /* I2C with hardware support */ 441 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 442 #define CONFIG_I2C_MULTI_BUS 443 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 444 #define CONFIG_SYS_I2C_SLAVE 0x7F 445 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ 446 #define CONFIG_SYS_I2C_OFFSET 0x3000 447 #define CONFIG_SYS_I2C2_OFFSET 0x3100 448 449 /* 450 * I2C2 EEPROM 451 */ 452 #define CONFIG_ID_EEPROM 453 #ifdef CONFIG_ID_EEPROM 454 #define CONFIG_SYS_I2C_EEPROM_NXID 455 #endif 456 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 457 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 458 #define CONFIG_SYS_EEPROM_BUS_NUM 1 459 460 /* 461 * General PCI 462 * Memory space is mapped 1-1, but I/O space must start from 0. 463 */ 464 465 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 466 #ifdef CONFIG_PHYS_64BIT 467 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 468 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 469 #else 470 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 471 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 472 #endif 473 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 474 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 475 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 476 #ifdef CONFIG_PHYS_64BIT 477 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 478 #else 479 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 480 #endif 481 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 482 483 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 484 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 485 #ifdef CONFIG_PHYS_64BIT 486 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 487 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 488 #else 489 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 490 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 491 #endif 492 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 493 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 494 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 495 #ifdef CONFIG_PHYS_64BIT 496 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 497 #else 498 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 499 #endif 500 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 501 502 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 503 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 504 #ifdef CONFIG_PHYS_64BIT 505 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 506 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 507 #else 508 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 509 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 510 #endif 511 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 512 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 513 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 514 #ifdef CONFIG_PHYS_64BIT 515 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 516 #else 517 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 518 #endif 519 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 520 521 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 522 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 523 #ifdef CONFIG_PHYS_64BIT 524 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 525 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 526 #else 527 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 528 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 529 #endif 530 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 531 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 532 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 533 #ifdef CONFIG_PHYS_64BIT 534 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 535 #else 536 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 537 #endif 538 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 539 540 #if defined(CONFIG_PCI) 541 542 #define CONFIG_NET_MULTI 543 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 544 545 /*PCIE video card used*/ 546 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 547 548 /*PCI video card used*/ 549 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 550 551 /* video */ 552 #define CONFIG_VIDEO 553 554 #if defined(CONFIG_VIDEO) 555 #define CONFIG_BIOSEMU 556 #define CONFIG_CFB_CONSOLE 557 #define CONFIG_VIDEO_SW_CURSOR 558 #define CONFIG_VGA_AS_SINGLE_DEVICE 559 #define CONFIG_ATI_RADEON_FB 560 #define CONFIG_VIDEO_LOGO 561 /*#define CONFIG_CONSOLE_CURSOR*/ 562 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 563 #endif 564 565 #undef CONFIG_EEPRO100 566 #undef CONFIG_TULIP 567 #undef CONFIG_RTL8139 568 569 #ifndef CONFIG_PCI_PNP 570 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 571 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 572 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 573 #endif 574 575 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 576 577 #endif /* CONFIG_PCI */ 578 579 /* SATA */ 580 #define CONFIG_LIBATA 581 #define CONFIG_FSL_SATA 582 583 #define CONFIG_SYS_SATA_MAX_DEVICE 2 584 #define CONFIG_SATA1 585 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 586 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 587 #define CONFIG_SATA2 588 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 589 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 590 591 #ifdef CONFIG_FSL_SATA 592 #define CONFIG_LBA48 593 #define CONFIG_CMD_SATA 594 #define CONFIG_DOS_PARTITION 595 #define CONFIG_CMD_EXT2 596 #endif 597 598 #if defined(CONFIG_TSEC_ENET) 599 600 #ifndef CONFIG_NET_MULTI 601 #define CONFIG_NET_MULTI 1 602 #endif 603 604 #define CONFIG_MII 1 /* MII PHY management */ 605 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 606 #define CONFIG_TSEC1 1 607 #define CONFIG_TSEC1_NAME "eTSEC1" 608 #define CONFIG_TSEC3 1 609 #define CONFIG_TSEC3_NAME "eTSEC3" 610 611 #define CONFIG_FSL_SGMII_RISER 1 612 #define SGMII_RISER_PHY_OFFSET 0x1c 613 614 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 615 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 616 617 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 618 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 619 620 #define TSEC1_PHYIDX 0 621 #define TSEC3_PHYIDX 0 622 623 #define CONFIG_ETHPRIME "eTSEC1" 624 625 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 626 627 #endif /* CONFIG_TSEC_ENET */ 628 629 /* 630 * Environment 631 */ 632 633 #if defined(CONFIG_SYS_RAMBOOT) 634 #if defined(CONFIG_RAMBOOT_NAND) 635 #define CONFIG_ENV_IS_IN_NAND 1 636 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 637 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 638 #endif 639 #else 640 #define CONFIG_ENV_IS_IN_FLASH 1 641 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 642 #define CONFIG_ENV_ADDR 0xfff80000 643 #else 644 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 645 #endif 646 #define CONFIG_ENV_SIZE 0x2000 647 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 648 #endif 649 650 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 651 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 652 653 /* 654 * Command line configuration. 655 */ 656 #include <config_cmd_default.h> 657 658 #define CONFIG_CMD_IRQ 659 #define CONFIG_CMD_PING 660 #define CONFIG_CMD_I2C 661 #define CONFIG_CMD_MII 662 #define CONFIG_CMD_ELF 663 #define CONFIG_CMD_IRQ 664 #define CONFIG_CMD_SETEXPR 665 666 #if defined(CONFIG_PCI) 667 #define CONFIG_CMD_PCI 668 #define CONFIG_CMD_NET 669 #endif 670 671 #undef CONFIG_WATCHDOG /* watchdog disabled */ 672 673 #define CONFIG_MMC 1 674 675 #ifdef CONFIG_MMC 676 #define CONFIG_FSL_ESDHC 677 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 678 #define CONFIG_CMD_MMC 679 #define CONFIG_GENERIC_MMC 680 #define CONFIG_CMD_EXT2 681 #define CONFIG_CMD_FAT 682 #define CONFIG_DOS_PARTITION 683 #endif 684 685 /* 686 * Miscellaneous configurable options 687 */ 688 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 689 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 690 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 691 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 692 #if defined(CONFIG_CMD_KGDB) 693 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 694 #else 695 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 696 #endif 697 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 698 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 699 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 700 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 701 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 702 703 /* 704 * For booting Linux, the board info and command line data 705 * have to be in the first 16 MB of memory, since this is 706 * the maximum mapped by the Linux kernel during initialization. 707 */ 708 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ 709 710 /* 711 * Internal Definitions 712 * 713 * Boot Flags 714 */ 715 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 716 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 717 718 #if defined(CONFIG_CMD_KGDB) 719 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 720 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 721 #endif 722 723 /* 724 * Environment Configuration 725 */ 726 727 /* The mac addresses for all ethernet interface */ 728 #if defined(CONFIG_TSEC_ENET) 729 #define CONFIG_HAS_ETH0 730 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 731 #define CONFIG_HAS_ETH1 732 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 733 #define CONFIG_HAS_ETH2 734 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 735 #define CONFIG_HAS_ETH3 736 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 737 #endif 738 739 #define CONFIG_IPADDR 192.168.1.254 740 741 #define CONFIG_HOSTNAME unknown 742 #define CONFIG_ROOTPATH /opt/nfsroot 743 #define CONFIG_BOOTFILE uImage 744 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 745 746 #define CONFIG_SERVERIP 192.168.1.1 747 #define CONFIG_GATEWAYIP 192.168.1.1 748 #define CONFIG_NETMASK 255.255.255.0 749 750 /* default location for tftp and bootm */ 751 #define CONFIG_LOADADDR 1000000 752 753 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 754 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 755 756 #define CONFIG_BAUDRATE 115200 757 758 #define CONFIG_EXTRA_ENV_SETTINGS \ 759 "netdev=eth0\0" \ 760 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 761 "tftpflash=tftpboot $loadaddr $uboot; " \ 762 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 763 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 764 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 765 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 766 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 767 "consoledev=ttyS0\0" \ 768 "ramdiskaddr=2000000\0" \ 769 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 770 "fdtaddr=c00000\0" \ 771 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 772 "bdev=sda3\0" \ 773 "usb_phy_type=ulpi\0" 774 775 #define CONFIG_HDBOOT \ 776 "setenv bootargs root=/dev/$bdev rw " \ 777 "console=$consoledev,$baudrate $othbootargs;" \ 778 "tftp $loadaddr $bootfile;" \ 779 "tftp $fdtaddr $fdtfile;" \ 780 "bootm $loadaddr - $fdtaddr" 781 782 #define CONFIG_NFSBOOTCOMMAND \ 783 "setenv bootargs root=/dev/nfs rw " \ 784 "nfsroot=$serverip:$rootpath " \ 785 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 786 "console=$consoledev,$baudrate $othbootargs;" \ 787 "tftp $loadaddr $bootfile;" \ 788 "tftp $fdtaddr $fdtfile;" \ 789 "bootm $loadaddr - $fdtaddr" 790 791 #define CONFIG_RAMBOOTCOMMAND \ 792 "setenv bootargs root=/dev/ram rw " \ 793 "console=$consoledev,$baudrate $othbootargs;" \ 794 "tftp $ramdiskaddr $ramdiskfile;" \ 795 "tftp $loadaddr $bootfile;" \ 796 "tftp $fdtaddr $fdtfile;" \ 797 "bootm $loadaddr $ramdiskaddr $fdtaddr" 798 799 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 800 801 #endif /* __CONFIG_H */ 802