1 /* 2 * Copyright 2007-2009,2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8536ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #include "../board/freescale/common/ics307_clk.h" 31 32 #ifdef CONFIG_MK_36BIT 33 #define CONFIG_PHYS_64BIT 1 34 #endif 35 36 #ifdef CONFIG_MK_NAND 37 #define CONFIG_NAND_U_BOOT 1 38 #define CONFIG_RAMBOOT_NAND 1 39 #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 40 #endif 41 42 #ifdef CONFIG_MK_SDCARD 43 #define CONFIG_RAMBOOT_SDCARD 1 44 #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 45 #endif 46 47 #ifdef CONFIG_MK_SPIFLASH 48 #define CONFIG_RAMBOOT_SPIFLASH 1 49 #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 50 #endif 51 52 /* High Level Configuration Options */ 53 #define CONFIG_BOOKE 1 /* BOOKE */ 54 #define CONFIG_E500 1 /* BOOKE e500 family */ 55 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 56 #define CONFIG_MPC8536 1 57 #define CONFIG_MPC8536DS 1 58 59 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 60 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 61 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 62 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 63 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 64 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 65 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 66 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 67 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 68 69 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 70 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ 71 72 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 73 #define CONFIG_ENV_OVERWRITE 74 75 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 76 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 77 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 78 79 /* 80 * These can be toggled for performance analysis, otherwise use default. 81 */ 82 #define CONFIG_L2_CACHE /* toggle L2 cache */ 83 #define CONFIG_BTB /* toggle branch predition */ 84 85 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 86 87 #define CONFIG_ENABLE_36BIT_PHYS 1 88 89 #ifdef CONFIG_PHYS_64BIT 90 #define CONFIG_ADDR_MAP 1 91 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 92 #endif 93 94 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 95 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 96 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 97 98 /* 99 * Config the L2 Cache as L2 SRAM 100 */ 101 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 102 #ifdef CONFIG_PHYS_64BIT 103 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 104 #else 105 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 106 #endif 107 #define CONFIG_SYS_L2_SIZE (512 << 10) 108 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 109 110 /* 111 * Base addresses -- Note these are effective addresses where the 112 * actual resources get mapped (not physical addresses) 113 */ 114 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 115 #ifdef CONFIG_PHYS_64BIT 116 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 117 #else 118 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 119 #endif 120 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 121 122 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) 123 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR 124 #else 125 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 126 #endif 127 128 /* DDR Setup */ 129 #define CONFIG_VERY_BIG_RAM 130 #define CONFIG_FSL_DDR2 131 #undef CONFIG_FSL_DDR_INTERACTIVE 132 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 133 #define CONFIG_DDR_SPD 134 #undef CONFIG_DDR_DLL 135 136 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 137 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 138 139 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 140 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 141 142 #define CONFIG_NUM_DDR_CONTROLLERS 1 143 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 144 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 145 146 /* I2C addresses of SPD EEPROMs */ 147 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 148 #define CONFIG_SYS_SPD_BUS_NUM 1 149 150 /* These are used when DDR doesn't use SPD. */ 151 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 152 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 153 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 154 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 155 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 156 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 157 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 158 #define CONFIG_SYS_DDR_MODE_1 0x00480432 159 #define CONFIG_SYS_DDR_MODE_2 0x00000000 160 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 161 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 162 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 163 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 164 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 165 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 166 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 167 168 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 169 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 170 #define CONFIG_SYS_DDR_SBE 0x00010000 171 172 /* Make sure required options are set */ 173 #ifndef CONFIG_SPD_EEPROM 174 #error ("CONFIG_SPD_EEPROM is required") 175 #endif 176 177 #undef CONFIG_CLOCKS_IN_MHZ 178 179 180 /* 181 * Memory map -- xxx -this is wrong, needs updating 182 * 183 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 184 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 185 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 186 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 187 * 188 * Localbus cacheable (TBD) 189 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 190 * 191 * Localbus non-cacheable 192 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 193 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 194 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 195 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 196 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 197 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 198 */ 199 200 /* 201 * Local Bus Definitions 202 */ 203 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 204 #ifdef CONFIG_PHYS_64BIT 205 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 206 #else 207 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 208 #endif 209 210 #define CONFIG_FLASH_BR_PRELIM \ 211 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ 212 | BR_PS_16 | BR_V) 213 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 214 215 #define CONFIG_SYS_BR1_PRELIM \ 216 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 217 | BR_PS_16 | BR_V) 218 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 219 220 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 221 CONFIG_SYS_FLASH_BASE_PHYS } 222 #define CONFIG_SYS_FLASH_QUIET_TEST 223 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 224 225 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 226 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 227 #undef CONFIG_SYS_FLASH_CHECKSUM 228 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 229 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 230 231 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 232 233 #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ 234 || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 235 #define CONFIG_SYS_RAMBOOT 236 #else 237 #undef CONFIG_SYS_RAMBOOT 238 #endif 239 240 #define CONFIG_FLASH_CFI_DRIVER 241 #define CONFIG_SYS_FLASH_CFI 242 #define CONFIG_SYS_FLASH_EMPTY_INFO 243 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 244 245 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 246 247 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 248 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 249 #ifdef CONFIG_PHYS_64BIT 250 #define PIXIS_BASE_PHYS 0xfffdf0000ull 251 #else 252 #define PIXIS_BASE_PHYS PIXIS_BASE 253 #endif 254 255 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 256 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 257 258 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 259 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 260 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 261 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 262 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 263 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 264 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 265 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 266 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 267 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 268 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 269 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 270 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 271 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 272 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 273 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 274 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 275 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 276 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 277 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 278 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 279 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 280 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 281 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 282 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 283 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 284 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 285 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 286 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 287 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 288 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 289 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 290 #define PIXIS_LED 0x25 /* LED Register */ 291 292 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 293 294 /* old pixis referenced names */ 295 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 296 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 297 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 298 299 #define CONFIG_SYS_INIT_RAM_LOCK 1 300 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 301 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 302 303 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 304 #define CONFIG_SYS_GBL_DATA_OFFSET \ 305 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 306 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 307 308 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 309 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 310 311 #ifndef CONFIG_NAND_SPL 312 #define CONFIG_SYS_NAND_BASE 0xffa00000 313 #ifdef CONFIG_PHYS_64BIT 314 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 315 #else 316 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 317 #endif 318 #else 319 #define CONFIG_SYS_NAND_BASE 0xfff00000 320 #ifdef CONFIG_PHYS_64BIT 321 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 322 #else 323 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 324 #endif 325 #endif 326 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 327 CONFIG_SYS_NAND_BASE + 0x40000, \ 328 CONFIG_SYS_NAND_BASE + 0x80000, \ 329 CONFIG_SYS_NAND_BASE + 0xC0000} 330 #define CONFIG_SYS_MAX_NAND_DEVICE 4 331 #define CONFIG_MTD_NAND_VERIFY_WRITE 332 #define CONFIG_CMD_NAND 1 333 #define CONFIG_NAND_FSL_ELBC 1 334 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 335 336 /* NAND boot: 4K NAND loader config */ 337 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 338 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 339 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 340 #define CONFIG_SYS_NAND_U_BOOT_START \ 341 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 342 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 343 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 344 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 345 346 /* NAND flash config */ 347 #define CONFIG_NAND_BR_PRELIM \ 348 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 349 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 350 | BR_PS_8 /* Port Size = 8 bit */ \ 351 | BR_MS_FCM /* MSEL = FCM */ \ 352 | BR_V) /* valid */ 353 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 354 | OR_FCM_PGS /* Large Page*/ \ 355 | OR_FCM_CSCT \ 356 | OR_FCM_CST \ 357 | OR_FCM_CHT \ 358 | OR_FCM_SCY_1 \ 359 | OR_FCM_TRLX \ 360 | OR_FCM_EHTR) 361 362 #ifdef CONFIG_RAMBOOT_NAND 363 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 364 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 365 #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 366 #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 367 #else 368 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 369 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 370 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 371 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 372 #endif 373 374 #define CONFIG_SYS_BR4_PRELIM \ 375 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \ 376 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 377 | BR_PS_8 /* Port Size = 8 bit */ \ 378 | BR_MS_FCM /* MSEL = FCM */ \ 379 | BR_V) /* valid */ 380 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 381 #define CONFIG_SYS_BR5_PRELIM \ 382 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \ 383 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 384 | BR_PS_8 /* Port Size = 8 bit */ \ 385 | BR_MS_FCM /* MSEL = FCM */ \ 386 | BR_V) /* valid */ 387 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 388 389 #define CONFIG_SYS_BR6_PRELIM \ 390 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \ 391 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 392 | BR_PS_8 /* Port Size = 8 bit */ \ 393 | BR_MS_FCM /* MSEL = FCM */ \ 394 | BR_V) /* valid */ 395 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 396 397 /* Serial Port - controlled on board with jumper J8 398 * open - index 2 399 * shorted - index 1 400 */ 401 #define CONFIG_CONS_INDEX 1 402 #undef CONFIG_SERIAL_SOFTWARE_FIFO 403 #define CONFIG_SYS_NS16550 404 #define CONFIG_SYS_NS16550_SERIAL 405 #define CONFIG_SYS_NS16550_REG_SIZE 1 406 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 407 #ifdef CONFIG_NAND_SPL 408 #define CONFIG_NS16550_MIN_FUNCTIONS 409 #endif 410 411 #define CONFIG_SYS_BAUDRATE_TABLE \ 412 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 413 414 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 415 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 416 417 /* Use the HUSH parser */ 418 #define CONFIG_SYS_HUSH_PARSER 419 #ifdef CONFIG_SYS_HUSH_PARSER 420 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 421 #endif 422 423 /* 424 * Pass open firmware flat tree 425 */ 426 #define CONFIG_OF_LIBFDT 1 427 #define CONFIG_OF_BOARD_SETUP 1 428 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 429 430 /* 431 * I2C 432 */ 433 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 434 #define CONFIG_HARD_I2C /* I2C with hardware support */ 435 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 436 #define CONFIG_I2C_MULTI_BUS 437 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 438 #define CONFIG_SYS_I2C_SLAVE 0x7F 439 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ 440 #define CONFIG_SYS_I2C_OFFSET 0x3000 441 #define CONFIG_SYS_I2C2_OFFSET 0x3100 442 443 /* 444 * I2C2 EEPROM 445 */ 446 #define CONFIG_ID_EEPROM 447 #ifdef CONFIG_ID_EEPROM 448 #define CONFIG_SYS_I2C_EEPROM_NXID 449 #endif 450 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 451 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 452 #define CONFIG_SYS_EEPROM_BUS_NUM 1 453 454 /* 455 * General PCI 456 * Memory space is mapped 1-1, but I/O space must start from 0. 457 */ 458 459 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 460 #ifdef CONFIG_PHYS_64BIT 461 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 462 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 463 #else 464 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 465 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 466 #endif 467 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 468 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 469 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 470 #ifdef CONFIG_PHYS_64BIT 471 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 472 #else 473 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 474 #endif 475 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 476 477 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 478 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 479 #ifdef CONFIG_PHYS_64BIT 480 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 481 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 482 #else 483 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 484 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 485 #endif 486 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 487 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 488 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 489 #ifdef CONFIG_PHYS_64BIT 490 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 491 #else 492 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 493 #endif 494 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 495 496 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 497 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 498 #ifdef CONFIG_PHYS_64BIT 499 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 500 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 501 #else 502 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 503 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 504 #endif 505 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 506 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 507 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 508 #ifdef CONFIG_PHYS_64BIT 509 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 510 #else 511 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 512 #endif 513 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 514 515 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 516 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 517 #ifdef CONFIG_PHYS_64BIT 518 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 519 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 520 #else 521 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 522 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 523 #endif 524 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 525 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 526 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 527 #ifdef CONFIG_PHYS_64BIT 528 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 529 #else 530 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 531 #endif 532 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 533 534 #if defined(CONFIG_PCI) 535 536 #define CONFIG_NET_MULTI 537 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 538 539 /*PCIE video card used*/ 540 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 541 542 /*PCI video card used*/ 543 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 544 545 /* video */ 546 #define CONFIG_VIDEO 547 548 #if defined(CONFIG_VIDEO) 549 #define CONFIG_BIOSEMU 550 #define CONFIG_CFB_CONSOLE 551 #define CONFIG_VIDEO_SW_CURSOR 552 #define CONFIG_VGA_AS_SINGLE_DEVICE 553 #define CONFIG_ATI_RADEON_FB 554 #define CONFIG_VIDEO_LOGO 555 /*#define CONFIG_CONSOLE_CURSOR*/ 556 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 557 #endif 558 559 #undef CONFIG_EEPRO100 560 #undef CONFIG_TULIP 561 #undef CONFIG_RTL8139 562 563 #ifndef CONFIG_PCI_PNP 564 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 565 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 566 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 567 #endif 568 569 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 570 571 #endif /* CONFIG_PCI */ 572 573 /* SATA */ 574 #define CONFIG_LIBATA 575 #define CONFIG_FSL_SATA 576 577 #define CONFIG_SYS_SATA_MAX_DEVICE 2 578 #define CONFIG_SATA1 579 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 580 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 581 #define CONFIG_SATA2 582 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 583 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 584 585 #ifdef CONFIG_FSL_SATA 586 #define CONFIG_LBA48 587 #define CONFIG_CMD_SATA 588 #define CONFIG_DOS_PARTITION 589 #define CONFIG_CMD_EXT2 590 #endif 591 592 #if defined(CONFIG_TSEC_ENET) 593 594 #ifndef CONFIG_NET_MULTI 595 #define CONFIG_NET_MULTI 1 596 #endif 597 598 #define CONFIG_MII 1 /* MII PHY management */ 599 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 600 #define CONFIG_TSEC1 1 601 #define CONFIG_TSEC1_NAME "eTSEC1" 602 #define CONFIG_TSEC3 1 603 #define CONFIG_TSEC3_NAME "eTSEC3" 604 605 #define CONFIG_FSL_SGMII_RISER 1 606 #define SGMII_RISER_PHY_OFFSET 0x1c 607 608 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 609 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 610 611 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 612 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 613 614 #define TSEC1_PHYIDX 0 615 #define TSEC3_PHYIDX 0 616 617 #define CONFIG_ETHPRIME "eTSEC1" 618 619 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 620 621 #endif /* CONFIG_TSEC_ENET */ 622 623 /* 624 * Environment 625 */ 626 627 #if defined(CONFIG_SYS_RAMBOOT) 628 #if defined(CONFIG_RAMBOOT_NAND) 629 #define CONFIG_ENV_IS_IN_NAND 1 630 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 631 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 632 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 633 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 634 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 635 #define CONFIG_ENV_SIZE 0x2000 636 #endif 637 #else 638 #define CONFIG_ENV_IS_IN_FLASH 1 639 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 640 #define CONFIG_ENV_ADDR 0xfff80000 641 #else 642 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 643 #endif 644 #define CONFIG_ENV_SIZE 0x2000 645 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 646 #endif 647 648 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 649 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 650 651 /* 652 * Command line configuration. 653 */ 654 #include <config_cmd_default.h> 655 656 #define CONFIG_CMD_IRQ 657 #define CONFIG_CMD_PING 658 #define CONFIG_CMD_I2C 659 #define CONFIG_CMD_MII 660 #define CONFIG_CMD_ELF 661 #define CONFIG_CMD_IRQ 662 #define CONFIG_CMD_SETEXPR 663 #define CONFIG_CMD_REGINFO 664 665 #if defined(CONFIG_PCI) 666 #define CONFIG_CMD_PCI 667 #define CONFIG_CMD_NET 668 #endif 669 670 #undef CONFIG_WATCHDOG /* watchdog disabled */ 671 672 #define CONFIG_MMC 1 673 674 #ifdef CONFIG_MMC 675 #define CONFIG_FSL_ESDHC 676 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 677 #define CONFIG_CMD_MMC 678 #define CONFIG_GENERIC_MMC 679 #define CONFIG_CMD_EXT2 680 #define CONFIG_CMD_FAT 681 #define CONFIG_DOS_PARTITION 682 #endif 683 684 /* 685 * Miscellaneous configurable options 686 */ 687 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 688 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 689 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 690 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 691 #if defined(CONFIG_CMD_KGDB) 692 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 693 #else 694 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 695 #endif 696 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 697 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 698 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 699 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 700 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 701 702 /* 703 * For booting Linux, the board info and command line data 704 * have to be in the first 16 MB of memory, since this is 705 * the maximum mapped by the Linux kernel during initialization. 706 */ 707 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ 708 709 /* 710 * Internal Definitions 711 * 712 * Boot Flags 713 */ 714 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 715 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 716 717 #if defined(CONFIG_CMD_KGDB) 718 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 719 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 720 #endif 721 722 /* 723 * Environment Configuration 724 */ 725 726 /* The mac addresses for all ethernet interface */ 727 #if defined(CONFIG_TSEC_ENET) 728 #define CONFIG_HAS_ETH0 729 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 730 #define CONFIG_HAS_ETH1 731 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 732 #define CONFIG_HAS_ETH2 733 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 734 #define CONFIG_HAS_ETH3 735 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 736 #endif 737 738 #define CONFIG_IPADDR 192.168.1.254 739 740 #define CONFIG_HOSTNAME unknown 741 #define CONFIG_ROOTPATH /opt/nfsroot 742 #define CONFIG_BOOTFILE uImage 743 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 744 745 #define CONFIG_SERVERIP 192.168.1.1 746 #define CONFIG_GATEWAYIP 192.168.1.1 747 #define CONFIG_NETMASK 255.255.255.0 748 749 /* default location for tftp and bootm */ 750 #define CONFIG_LOADADDR 1000000 751 752 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 753 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 754 755 #define CONFIG_BAUDRATE 115200 756 757 #define CONFIG_EXTRA_ENV_SETTINGS \ 758 "netdev=eth0\0" \ 759 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 760 "tftpflash=tftpboot $loadaddr $uboot; " \ 761 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 762 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 763 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 764 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 765 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 766 "consoledev=ttyS0\0" \ 767 "ramdiskaddr=2000000\0" \ 768 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 769 "fdtaddr=c00000\0" \ 770 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 771 "bdev=sda3\0" \ 772 "usb_phy_type=ulpi\0" 773 774 #define CONFIG_HDBOOT \ 775 "setenv bootargs root=/dev/$bdev rw " \ 776 "console=$consoledev,$baudrate $othbootargs;" \ 777 "tftp $loadaddr $bootfile;" \ 778 "tftp $fdtaddr $fdtfile;" \ 779 "bootm $loadaddr - $fdtaddr" 780 781 #define CONFIG_NFSBOOTCOMMAND \ 782 "setenv bootargs root=/dev/nfs rw " \ 783 "nfsroot=$serverip:$rootpath " \ 784 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 785 "console=$consoledev,$baudrate $othbootargs;" \ 786 "tftp $loadaddr $bootfile;" \ 787 "tftp $fdtaddr $fdtfile;" \ 788 "bootm $loadaddr - $fdtaddr" 789 790 #define CONFIG_RAMBOOTCOMMAND \ 791 "setenv bootargs root=/dev/ram rw " \ 792 "console=$consoledev,$baudrate $othbootargs;" \ 793 "tftp $ramdiskaddr $ramdiskfile;" \ 794 "tftp $loadaddr $bootfile;" \ 795 "tftp $fdtaddr $fdtfile;" \ 796 "bootm $loadaddr $ramdiskaddr $fdtaddr" 797 798 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 799 800 #endif /* __CONFIG_H */ 801