1 /* 2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8536ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 1 18 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 19 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 20 #endif 21 22 #ifdef CONFIG_SPIFLASH 23 #define CONFIG_RAMBOOT_SPIFLASH 1 24 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 26 #endif 27 28 #ifndef CONFIG_SYS_TEXT_BASE 29 #define CONFIG_SYS_TEXT_BASE 0xeff40000 30 #endif 31 32 #ifndef CONFIG_RESET_VECTOR_ADDRESS 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 34 #endif 35 36 #ifndef CONFIG_SYS_MONITOR_BASE 37 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 38 #endif 39 40 /* High Level Configuration Options */ 41 #define CONFIG_BOOKE 1 /* BOOKE */ 42 #define CONFIG_E500 1 /* BOOKE e500 family */ 43 #define CONFIG_MPC8536DS 1 44 45 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 46 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 47 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 48 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 49 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 50 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 51 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 52 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 53 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 54 55 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 56 57 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 58 #define CONFIG_ENV_OVERWRITE 59 60 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 61 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 62 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 63 64 /* 65 * These can be toggled for performance analysis, otherwise use default. 66 */ 67 #define CONFIG_L2_CACHE /* toggle L2 cache */ 68 #define CONFIG_BTB /* toggle branch predition */ 69 70 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 71 72 #define CONFIG_ENABLE_36BIT_PHYS 1 73 74 #ifdef CONFIG_PHYS_64BIT 75 #define CONFIG_ADDR_MAP 1 76 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 77 #endif 78 79 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 80 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 81 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 82 83 /* 84 * Config the L2 Cache as L2 SRAM 85 */ 86 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 87 #ifdef CONFIG_PHYS_64BIT 88 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 89 #else 90 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 91 #endif 92 #define CONFIG_SYS_L2_SIZE (512 << 10) 93 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 94 95 #define CONFIG_SYS_CCSRBAR 0xffe00000 96 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 97 98 #if defined(CONFIG_NAND_SPL) 99 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 100 #endif 101 102 /* DDR Setup */ 103 #define CONFIG_VERY_BIG_RAM 104 #define CONFIG_SYS_FSL_DDR2 105 #undef CONFIG_FSL_DDR_INTERACTIVE 106 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 107 #define CONFIG_DDR_SPD 108 109 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 110 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 111 112 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 113 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 114 115 #define CONFIG_NUM_DDR_CONTROLLERS 1 116 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 117 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 118 119 /* I2C addresses of SPD EEPROMs */ 120 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 121 #define CONFIG_SYS_SPD_BUS_NUM 1 122 123 /* These are used when DDR doesn't use SPD. */ 124 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 125 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 126 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 127 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 128 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 129 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 130 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 131 #define CONFIG_SYS_DDR_MODE_1 0x00480432 132 #define CONFIG_SYS_DDR_MODE_2 0x00000000 133 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 134 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 135 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 136 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 137 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 138 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 139 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 140 141 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 142 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 143 #define CONFIG_SYS_DDR_SBE 0x00010000 144 145 /* Make sure required options are set */ 146 #ifndef CONFIG_SPD_EEPROM 147 #error ("CONFIG_SPD_EEPROM is required") 148 #endif 149 150 #undef CONFIG_CLOCKS_IN_MHZ 151 152 /* 153 * Memory map -- xxx -this is wrong, needs updating 154 * 155 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 156 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 157 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 158 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 159 * 160 * Localbus cacheable (TBD) 161 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 162 * 163 * Localbus non-cacheable 164 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 165 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 166 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 167 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 168 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 169 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 170 */ 171 172 /* 173 * Local Bus Definitions 174 */ 175 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 176 #ifdef CONFIG_PHYS_64BIT 177 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 178 #else 179 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 180 #endif 181 182 #define CONFIG_FLASH_BR_PRELIM \ 183 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 184 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 185 186 #define CONFIG_SYS_BR1_PRELIM \ 187 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 188 | BR_PS_16 | BR_V) 189 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 190 191 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 192 CONFIG_SYS_FLASH_BASE_PHYS } 193 #define CONFIG_SYS_FLASH_QUIET_TEST 194 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 195 196 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 197 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 198 #undef CONFIG_SYS_FLASH_CHECKSUM 199 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 200 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 201 202 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 203 #define CONFIG_SYS_RAMBOOT 204 #define CONFIG_SYS_EXTRA_ENV_RELOC 205 #else 206 #undef CONFIG_SYS_RAMBOOT 207 #endif 208 209 #define CONFIG_FLASH_CFI_DRIVER 210 #define CONFIG_SYS_FLASH_CFI 211 #define CONFIG_SYS_FLASH_EMPTY_INFO 212 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 213 214 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 215 216 #define CONFIG_HWCONFIG /* enable hwconfig */ 217 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 218 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 219 #ifdef CONFIG_PHYS_64BIT 220 #define PIXIS_BASE_PHYS 0xfffdf0000ull 221 #else 222 #define PIXIS_BASE_PHYS PIXIS_BASE 223 #endif 224 225 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 226 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 227 228 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 229 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 230 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 231 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 232 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 233 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 234 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 235 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 236 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 237 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 238 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 239 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 240 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 241 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 242 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 243 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 244 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 245 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 246 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 247 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 248 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 249 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 250 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 251 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 252 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 253 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 254 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 255 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 256 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 257 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 258 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 259 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 260 #define PIXIS_LED 0x25 /* LED Register */ 261 262 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 263 264 /* old pixis referenced names */ 265 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 266 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 267 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 268 269 #define CONFIG_SYS_INIT_RAM_LOCK 1 270 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 271 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 272 273 #define CONFIG_SYS_GBL_DATA_OFFSET \ 274 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 275 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 276 277 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 278 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 279 280 #ifndef CONFIG_NAND_SPL 281 #define CONFIG_SYS_NAND_BASE 0xffa00000 282 #ifdef CONFIG_PHYS_64BIT 283 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 284 #else 285 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 286 #endif 287 #else 288 #define CONFIG_SYS_NAND_BASE 0xfff00000 289 #ifdef CONFIG_PHYS_64BIT 290 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 291 #else 292 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 293 #endif 294 #endif 295 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 296 CONFIG_SYS_NAND_BASE + 0x40000, \ 297 CONFIG_SYS_NAND_BASE + 0x80000, \ 298 CONFIG_SYS_NAND_BASE + 0xC0000} 299 #define CONFIG_SYS_MAX_NAND_DEVICE 4 300 #define CONFIG_CMD_NAND 1 301 #define CONFIG_NAND_FSL_ELBC 1 302 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 303 304 /* NAND boot: 4K NAND loader config */ 305 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 306 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 307 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 308 #define CONFIG_SYS_NAND_U_BOOT_START \ 309 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 310 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 311 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 312 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 313 314 /* NAND flash config */ 315 #define CONFIG_SYS_NAND_BR_PRELIM \ 316 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 317 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 318 | BR_PS_8 /* Port Size = 8 bit */ \ 319 | BR_MS_FCM /* MSEL = FCM */ \ 320 | BR_V) /* valid */ 321 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 322 | OR_FCM_PGS /* Large Page*/ \ 323 | OR_FCM_CSCT \ 324 | OR_FCM_CST \ 325 | OR_FCM_CHT \ 326 | OR_FCM_SCY_1 \ 327 | OR_FCM_TRLX \ 328 | OR_FCM_EHTR) 329 330 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 331 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 332 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 333 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 334 335 #define CONFIG_SYS_BR4_PRELIM \ 336 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 337 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 338 | BR_PS_8 /* Port Size = 8 bit */ \ 339 | BR_MS_FCM /* MSEL = FCM */ \ 340 | BR_V) /* valid */ 341 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 342 #define CONFIG_SYS_BR5_PRELIM \ 343 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 344 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 345 | BR_PS_8 /* Port Size = 8 bit */ \ 346 | BR_MS_FCM /* MSEL = FCM */ \ 347 | BR_V) /* valid */ 348 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 349 350 #define CONFIG_SYS_BR6_PRELIM \ 351 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 352 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 353 | BR_PS_8 /* Port Size = 8 bit */ \ 354 | BR_MS_FCM /* MSEL = FCM */ \ 355 | BR_V) /* valid */ 356 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 357 358 /* Serial Port - controlled on board with jumper J8 359 * open - index 2 360 * shorted - index 1 361 */ 362 #define CONFIG_CONS_INDEX 1 363 #define CONFIG_SYS_NS16550_SERIAL 364 #define CONFIG_SYS_NS16550_REG_SIZE 1 365 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 366 #ifdef CONFIG_NAND_SPL 367 #define CONFIG_NS16550_MIN_FUNCTIONS 368 #endif 369 370 #define CONFIG_SYS_BAUDRATE_TABLE \ 371 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 372 373 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 374 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 375 376 /* 377 * I2C 378 */ 379 #define CONFIG_SYS_I2C 380 #define CONFIG_SYS_I2C_FSL 381 #define CONFIG_SYS_FSL_I2C_SPEED 400000 382 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 383 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 384 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 385 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 386 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 387 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 388 389 /* 390 * I2C2 EEPROM 391 */ 392 #define CONFIG_ID_EEPROM 393 #ifdef CONFIG_ID_EEPROM 394 #define CONFIG_SYS_I2C_EEPROM_NXID 395 #endif 396 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 397 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 398 #define CONFIG_SYS_EEPROM_BUS_NUM 1 399 400 /* 401 * eSPI - Enhanced SPI 402 */ 403 #define CONFIG_HARD_SPI 404 405 #if defined(CONFIG_SPI_FLASH) 406 #define CONFIG_SF_DEFAULT_SPEED 10000000 407 #define CONFIG_SF_DEFAULT_MODE 0 408 #endif 409 410 /* 411 * General PCI 412 * Memory space is mapped 1-1, but I/O space must start from 0. 413 */ 414 415 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 416 #ifdef CONFIG_PHYS_64BIT 417 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 418 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 419 #else 420 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 421 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 422 #endif 423 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 424 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 425 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 426 #ifdef CONFIG_PHYS_64BIT 427 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 428 #else 429 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 430 #endif 431 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 432 433 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 434 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 435 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 436 #ifdef CONFIG_PHYS_64BIT 437 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 438 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 439 #else 440 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 441 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 442 #endif 443 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 444 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 445 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 446 #ifdef CONFIG_PHYS_64BIT 447 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 448 #else 449 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 450 #endif 451 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 452 453 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 454 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 455 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 456 #ifdef CONFIG_PHYS_64BIT 457 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 458 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 459 #else 460 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 461 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 462 #endif 463 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 464 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 465 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 466 #ifdef CONFIG_PHYS_64BIT 467 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 468 #else 469 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 470 #endif 471 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 472 473 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 474 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 475 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 476 #ifdef CONFIG_PHYS_64BIT 477 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 478 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 479 #else 480 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 481 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 482 #endif 483 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 484 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 485 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 486 #ifdef CONFIG_PHYS_64BIT 487 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 488 #else 489 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 490 #endif 491 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 492 493 #if defined(CONFIG_PCI) 494 /*PCIE video card used*/ 495 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 496 497 /*PCI video card used*/ 498 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 499 500 /* video */ 501 502 #if defined(CONFIG_VIDEO) 503 #define CONFIG_BIOSEMU 504 #define CONFIG_ATI_RADEON_FB 505 #define CONFIG_VIDEO_LOGO 506 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 507 #endif 508 509 #undef CONFIG_EEPRO100 510 #undef CONFIG_TULIP 511 512 #ifndef CONFIG_PCI_PNP 513 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 514 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 515 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 516 #endif 517 518 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 519 520 #endif /* CONFIG_PCI */ 521 522 /* SATA */ 523 #define CONFIG_LIBATA 524 #define CONFIG_FSL_SATA 525 526 #define CONFIG_SYS_SATA_MAX_DEVICE 2 527 #define CONFIG_SATA1 528 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 529 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 530 #define CONFIG_SATA2 531 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 532 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 533 534 #ifdef CONFIG_FSL_SATA 535 #define CONFIG_LBA48 536 #define CONFIG_CMD_SATA 537 #define CONFIG_DOS_PARTITION 538 #endif 539 540 #if defined(CONFIG_TSEC_ENET) 541 542 #define CONFIG_MII 1 /* MII PHY management */ 543 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 544 #define CONFIG_TSEC1 1 545 #define CONFIG_TSEC1_NAME "eTSEC1" 546 #define CONFIG_TSEC3 1 547 #define CONFIG_TSEC3_NAME "eTSEC3" 548 549 #define CONFIG_FSL_SGMII_RISER 1 550 #define SGMII_RISER_PHY_OFFSET 0x1c 551 552 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 553 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 554 555 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 556 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 557 558 #define TSEC1_PHYIDX 0 559 #define TSEC3_PHYIDX 0 560 561 #define CONFIG_ETHPRIME "eTSEC1" 562 563 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 564 565 #endif /* CONFIG_TSEC_ENET */ 566 567 /* 568 * Environment 569 */ 570 571 #if defined(CONFIG_SYS_RAMBOOT) 572 #if defined(CONFIG_RAMBOOT_SPIFLASH) 573 #define CONFIG_ENV_IS_IN_SPI_FLASH 574 #define CONFIG_ENV_SPI_BUS 0 575 #define CONFIG_ENV_SPI_CS 0 576 #define CONFIG_ENV_SPI_MAX_HZ 10000000 577 #define CONFIG_ENV_SPI_MODE 0 578 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 579 #define CONFIG_ENV_OFFSET 0xF0000 580 #define CONFIG_ENV_SECT_SIZE 0x10000 581 #elif defined(CONFIG_RAMBOOT_SDCARD) 582 #define CONFIG_ENV_IS_IN_MMC 583 #define CONFIG_FSL_FIXED_MMC_LOCATION 584 #define CONFIG_ENV_SIZE 0x2000 585 #define CONFIG_SYS_MMC_ENV_DEV 0 586 #else 587 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 588 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 589 #define CONFIG_ENV_SIZE 0x2000 590 #endif 591 #else 592 #define CONFIG_ENV_IS_IN_FLASH 1 593 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 594 #define CONFIG_ENV_SIZE 0x2000 595 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 596 #endif 597 598 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 599 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 600 601 /* 602 * Command line configuration. 603 */ 604 #define CONFIG_CMD_IRQ 605 #define CONFIG_CMD_IRQ 606 #define CONFIG_CMD_REGINFO 607 608 #if defined(CONFIG_PCI) 609 #define CONFIG_CMD_PCI 610 #endif 611 612 #undef CONFIG_WATCHDOG /* watchdog disabled */ 613 614 #define CONFIG_MMC 1 615 616 #ifdef CONFIG_MMC 617 #define CONFIG_FSL_ESDHC 618 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 619 #define CONFIG_GENERIC_MMC 620 #endif 621 622 /* 623 * USB 624 */ 625 #define CONFIG_HAS_FSL_MPH_USB 626 #ifdef CONFIG_HAS_FSL_MPH_USB 627 #define CONFIG_USB_EHCI 628 629 #ifdef CONFIG_USB_EHCI 630 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 631 #define CONFIG_USB_EHCI_FSL 632 #endif 633 #endif 634 635 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 636 #define CONFIG_DOS_PARTITION 637 #endif 638 639 /* 640 * Miscellaneous configurable options 641 */ 642 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 643 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 644 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 645 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 646 #if defined(CONFIG_CMD_KGDB) 647 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 648 #else 649 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 650 #endif 651 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 652 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 653 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 654 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 655 656 /* 657 * For booting Linux, the board info and command line data 658 * have to be in the first 64 MB of memory, since this is 659 * the maximum mapped by the Linux kernel during initialization. 660 */ 661 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 662 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 663 664 #if defined(CONFIG_CMD_KGDB) 665 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 666 #endif 667 668 /* 669 * Environment Configuration 670 */ 671 672 /* The mac addresses for all ethernet interface */ 673 #if defined(CONFIG_TSEC_ENET) 674 #define CONFIG_HAS_ETH0 675 #define CONFIG_HAS_ETH1 676 #define CONFIG_HAS_ETH2 677 #define CONFIG_HAS_ETH3 678 #endif 679 680 #define CONFIG_IPADDR 192.168.1.254 681 682 #define CONFIG_HOSTNAME unknown 683 #define CONFIG_ROOTPATH "/opt/nfsroot" 684 #define CONFIG_BOOTFILE "uImage" 685 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 686 687 #define CONFIG_SERVERIP 192.168.1.1 688 #define CONFIG_GATEWAYIP 192.168.1.1 689 #define CONFIG_NETMASK 255.255.255.0 690 691 /* default location for tftp and bootm */ 692 #define CONFIG_LOADADDR 1000000 693 694 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 695 696 #define CONFIG_BAUDRATE 115200 697 698 #define CONFIG_EXTRA_ENV_SETTINGS \ 699 "netdev=eth0\0" \ 700 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 701 "tftpflash=tftpboot $loadaddr $uboot; " \ 702 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 703 " +$filesize; " \ 704 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 705 " +$filesize; " \ 706 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 707 " $filesize; " \ 708 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 709 " +$filesize; " \ 710 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 711 " $filesize\0" \ 712 "consoledev=ttyS0\0" \ 713 "ramdiskaddr=2000000\0" \ 714 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 715 "fdtaddr=1e00000\0" \ 716 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 717 "bdev=sda3\0" \ 718 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 719 720 #define CONFIG_HDBOOT \ 721 "setenv bootargs root=/dev/$bdev rw " \ 722 "console=$consoledev,$baudrate $othbootargs;" \ 723 "tftp $loadaddr $bootfile;" \ 724 "tftp $fdtaddr $fdtfile;" \ 725 "bootm $loadaddr - $fdtaddr" 726 727 #define CONFIG_NFSBOOTCOMMAND \ 728 "setenv bootargs root=/dev/nfs rw " \ 729 "nfsroot=$serverip:$rootpath " \ 730 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 731 "console=$consoledev,$baudrate $othbootargs;" \ 732 "tftp $loadaddr $bootfile;" \ 733 "tftp $fdtaddr $fdtfile;" \ 734 "bootm $loadaddr - $fdtaddr" 735 736 #define CONFIG_RAMBOOTCOMMAND \ 737 "setenv bootargs root=/dev/ram rw " \ 738 "console=$consoledev,$baudrate $othbootargs;" \ 739 "tftp $ramdiskaddr $ramdiskfile;" \ 740 "tftp $loadaddr $bootfile;" \ 741 "tftp $fdtaddr $fdtfile;" \ 742 "bootm $loadaddr $ramdiskaddr $fdtaddr" 743 744 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 745 746 #endif /* __CONFIG_H */ 747