1 /* 2 * Copyright 2008-2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8536ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #ifdef CONFIG_MK_36BIT 31 #define CONFIG_PHYS_64BIT 1 32 #endif 33 34 /* High Level Configuration Options */ 35 #define CONFIG_BOOKE 1 /* BOOKE */ 36 #define CONFIG_E500 1 /* BOOKE e500 family */ 37 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 38 #define CONFIG_MPC8536 1 39 #define CONFIG_MPC8536DS 1 40 41 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 42 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 43 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 44 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 45 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 46 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 47 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 48 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 49 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 50 51 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 52 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ 53 54 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 55 #define CONFIG_ENV_OVERWRITE 56 57 /* 58 * When initializing flash, if we cannot find the manufacturer ID, 59 * assume this is the AMD flash associated with the CDS board. 60 * This allows booting from a promjet. 61 */ 62 #define CONFIG_ASSUME_AMD_FLASH 63 64 #ifndef __ASSEMBLY__ 65 extern unsigned long get_board_sys_clk(unsigned long dummy); 66 extern unsigned long get_board_ddr_clk(unsigned long dummy); 67 #endif 68 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 69 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) 70 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 71 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 72 from ICS307 instead of switches */ 73 74 /* 75 * These can be toggled for performance analysis, otherwise use default. 76 */ 77 #define CONFIG_L2_CACHE /* toggle L2 cache */ 78 #define CONFIG_BTB /* toggle branch predition */ 79 80 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 81 82 #define CONFIG_ENABLE_36BIT_PHYS 1 83 84 #ifdef CONFIG_PHYS_64BIT 85 #define CONFIG_ADDR_MAP 1 86 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 87 #endif 88 89 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 90 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 91 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 92 93 /* 94 * Base addresses -- Note these are effective addresses where the 95 * actual resources get mapped (not physical addresses) 96 */ 97 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 98 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 99 #ifdef CONFIG_PHYS_64BIT 100 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 101 #else 102 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 103 #endif 104 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 105 106 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) 107 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) 108 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) 109 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) 110 111 /* DDR Setup */ 112 #define CONFIG_VERY_BIG_RAM 113 #define CONFIG_FSL_DDR2 114 #undef CONFIG_FSL_DDR_INTERACTIVE 115 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 116 #define CONFIG_DDR_SPD 117 #undef CONFIG_DDR_DLL 118 119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 120 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 121 122 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 123 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 124 125 #define CONFIG_NUM_DDR_CONTROLLERS 1 126 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 127 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 128 129 /* I2C addresses of SPD EEPROMs */ 130 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 131 #define CONFIG_SYS_SPD_BUS_NUM 1 132 133 /* These are used when DDR doesn't use SPD. */ 134 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 135 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 136 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 137 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 138 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 139 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 140 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 141 #define CONFIG_SYS_DDR_MODE_1 0x00480432 142 #define CONFIG_SYS_DDR_MODE_2 0x00000000 143 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 144 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 145 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 146 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 147 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 148 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 149 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 150 151 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 152 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 153 #define CONFIG_SYS_DDR_SBE 0x00010000 154 155 /* Make sure required options are set */ 156 #ifndef CONFIG_SPD_EEPROM 157 #error ("CONFIG_SPD_EEPROM is required") 158 #endif 159 160 #undef CONFIG_CLOCKS_IN_MHZ 161 162 163 /* 164 * Memory map -- xxx -this is wrong, needs updating 165 * 166 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 167 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 168 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 169 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 170 * 171 * Localbus cacheable (TBD) 172 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 173 * 174 * Localbus non-cacheable 175 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 176 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 177 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 178 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 179 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 180 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 181 */ 182 183 /* 184 * Local Bus Definitions 185 */ 186 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 187 #ifdef CONFIG_PHYS_64BIT 188 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 189 #else 190 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 191 #endif 192 193 #define CONFIG_SYS_BR0_PRELIM \ 194 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ 195 | BR_PS_16 | BR_V) 196 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 197 198 #define CONFIG_SYS_BR1_PRELIM \ 199 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 200 | BR_PS_16 | BR_V) 201 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 202 203 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 204 CONFIG_SYS_FLASH_BASE_PHYS } 205 #define CONFIG_SYS_FLASH_QUIET_TEST 206 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 207 208 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 209 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 210 #undef CONFIG_SYS_FLASH_CHECKSUM 211 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 212 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 213 214 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 215 216 #define CONFIG_FLASH_CFI_DRIVER 217 #define CONFIG_SYS_FLASH_CFI 218 #define CONFIG_SYS_FLASH_EMPTY_INFO 219 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 220 221 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 222 223 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 224 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 225 #ifdef CONFIG_PHYS_64BIT 226 #define PIXIS_BASE_PHYS 0xfffdf0000ull 227 #else 228 #define PIXIS_BASE_PHYS PIXIS_BASE 229 #endif 230 231 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 232 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 233 234 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 235 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 236 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 237 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 238 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 239 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 240 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 241 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 242 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 243 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 244 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 245 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 246 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 247 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 248 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 249 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 250 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 251 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 252 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 253 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 254 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 255 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 256 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 257 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 258 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 259 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 260 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 261 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 262 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 263 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 264 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 265 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 266 #define PIXIS_LED 0x25 /* LED Register */ 267 268 /* old pixis referenced names */ 269 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 270 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 271 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 272 273 #define CONFIG_SYS_INIT_RAM_LOCK 1 274 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 275 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 276 277 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 278 #define CONFIG_SYS_GBL_DATA_OFFSET \ 279 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 280 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 281 282 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 283 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 284 285 #define CONFIG_SYS_NAND_BASE 0xffa00000 286 #ifdef CONFIG_PHYS_64BIT 287 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 288 #else 289 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 290 #endif 291 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 292 CONFIG_SYS_NAND_BASE + 0x40000, \ 293 CONFIG_SYS_NAND_BASE + 0x80000, \ 294 CONFIG_SYS_NAND_BASE + 0xC0000} 295 #define CONFIG_SYS_MAX_NAND_DEVICE 4 296 #define CONFIG_MTD_NAND_VERIFY_WRITE 297 #define CONFIG_CMD_NAND 1 298 #define CONFIG_NAND_FSL_ELBC 1 299 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 300 301 /* NAND flash config */ 302 #define CONFIG_NAND_BR_PRELIM \ 303 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 304 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 305 | BR_PS_8 /* Port Size = 8 bit */ \ 306 | BR_MS_FCM /* MSEL = FCM */ \ 307 | BR_V) /* valid */ 308 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 309 | OR_FCM_PGS /* Large Page*/ \ 310 | OR_FCM_CSCT \ 311 | OR_FCM_CST \ 312 | OR_FCM_CHT \ 313 | OR_FCM_SCY_1 \ 314 | OR_FCM_TRLX \ 315 | OR_FCM_EHTR) 316 317 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 318 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 319 320 #define CONFIG_SYS_BR4_PRELIM \ 321 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \ 322 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 323 | BR_PS_8 /* Port Size = 8 bit */ \ 324 | BR_MS_FCM /* MSEL = FCM */ \ 325 | BR_V) /* valid */ 326 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 327 #define CONFIG_SYS_BR5_PRELIM \ 328 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \ 329 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 330 | BR_PS_8 /* Port Size = 8 bit */ \ 331 | BR_MS_FCM /* MSEL = FCM */ \ 332 | BR_V) /* valid */ 333 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 334 335 #define CONFIG_SYS_BR6_PRELIM \ 336 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \ 337 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 338 | BR_PS_8 /* Port Size = 8 bit */ \ 339 | BR_MS_FCM /* MSEL = FCM */ \ 340 | BR_V) /* valid */ 341 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 342 343 /* Serial Port - controlled on board with jumper J8 344 * open - index 2 345 * shorted - index 1 346 */ 347 #define CONFIG_CONS_INDEX 1 348 #undef CONFIG_SERIAL_SOFTWARE_FIFO 349 #define CONFIG_SYS_NS16550 350 #define CONFIG_SYS_NS16550_SERIAL 351 #define CONFIG_SYS_NS16550_REG_SIZE 1 352 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 353 354 #define CONFIG_SYS_BAUDRATE_TABLE \ 355 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 356 357 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 358 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 359 360 /* Use the HUSH parser */ 361 #define CONFIG_SYS_HUSH_PARSER 362 #ifdef CONFIG_SYS_HUSH_PARSER 363 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 364 #endif 365 366 /* 367 * Pass open firmware flat tree 368 */ 369 #define CONFIG_OF_LIBFDT 1 370 #define CONFIG_OF_BOARD_SETUP 1 371 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 372 373 #define CONFIG_SYS_64BIT_STRTOUL 1 374 #define CONFIG_SYS_64BIT_VSPRINTF 1 375 376 377 /* 378 * I2C 379 */ 380 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 381 #define CONFIG_HARD_I2C /* I2C with hardware support */ 382 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 383 #define CONFIG_I2C_MULTI_BUS 384 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 385 #define CONFIG_SYS_I2C_SLAVE 0x7F 386 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ 387 #define CONFIG_SYS_I2C_OFFSET 0x3000 388 #define CONFIG_SYS_I2C2_OFFSET 0x3100 389 390 /* 391 * I2C2 EEPROM 392 */ 393 #define CONFIG_ID_EEPROM 394 #ifdef CONFIG_ID_EEPROM 395 #define CONFIG_SYS_I2C_EEPROM_NXID 396 #endif 397 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 398 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 399 #define CONFIG_SYS_EEPROM_BUS_NUM 1 400 401 /* 402 * General PCI 403 * Memory space is mapped 1-1, but I/O space must start from 0. 404 */ 405 406 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 407 #ifdef CONFIG_PHYS_64BIT 408 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 409 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 410 #else 411 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 412 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 413 #endif 414 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 415 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 416 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 417 #ifdef CONFIG_PHYS_64BIT 418 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 419 #else 420 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 421 #endif 422 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 423 424 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 425 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 426 #ifdef CONFIG_PHYS_64BIT 427 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 428 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 429 #else 430 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 431 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 432 #endif 433 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 434 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 435 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 436 #ifdef CONFIG_PHYS_64BIT 437 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 438 #else 439 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 440 #endif 441 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 442 443 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 444 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 445 #ifdef CONFIG_PHYS_64BIT 446 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 447 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 448 #else 449 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 450 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 451 #endif 452 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 453 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 454 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 455 #ifdef CONFIG_PHYS_64BIT 456 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 457 #else 458 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 459 #endif 460 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 461 462 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 463 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 464 #ifdef CONFIG_PHYS_64BIT 465 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 466 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 467 #else 468 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 469 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 470 #endif 471 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 472 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 473 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 474 #ifdef CONFIG_PHYS_64BIT 475 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 476 #else 477 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 478 #endif 479 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 480 481 #if defined(CONFIG_PCI) 482 483 #define CONFIG_NET_MULTI 484 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 485 486 /*PCIE video card used*/ 487 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 488 489 /*PCI video card used*/ 490 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 491 492 /* video */ 493 #define CONFIG_VIDEO 494 495 #if defined(CONFIG_VIDEO) 496 #define CONFIG_BIOSEMU 497 #define CONFIG_CFB_CONSOLE 498 #define CONFIG_VIDEO_SW_CURSOR 499 #define CONFIG_VGA_AS_SINGLE_DEVICE 500 #define CONFIG_ATI_RADEON_FB 501 #define CONFIG_VIDEO_LOGO 502 /*#define CONFIG_CONSOLE_CURSOR*/ 503 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 504 #endif 505 506 #undef CONFIG_EEPRO100 507 #undef CONFIG_TULIP 508 #undef CONFIG_RTL8139 509 510 #ifndef CONFIG_PCI_PNP 511 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 512 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 513 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 514 #endif 515 516 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 517 518 #endif /* CONFIG_PCI */ 519 520 /* SATA */ 521 #define CONFIG_LIBATA 522 #define CONFIG_FSL_SATA 523 524 #define CONFIG_SYS_SATA_MAX_DEVICE 2 525 #define CONFIG_SATA1 526 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 527 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 528 #define CONFIG_SATA2 529 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 530 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 531 532 #ifdef CONFIG_FSL_SATA 533 #define CONFIG_LBA48 534 #define CONFIG_CMD_SATA 535 #define CONFIG_DOS_PARTITION 536 #define CONFIG_CMD_EXT2 537 #endif 538 539 /* 540 * USB 541 */ 542 #define CONFIG_CMD_USB 543 #define CONFIG_USB_STORAGE 544 #define CONFIG_USB_EHCI 545 #define CONFIG_USB_EHCI_FSL 546 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 547 548 #if defined(CONFIG_TSEC_ENET) 549 550 #ifndef CONFIG_NET_MULTI 551 #define CONFIG_NET_MULTI 1 552 #endif 553 554 #define CONFIG_MII 1 /* MII PHY management */ 555 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 556 #define CONFIG_TSEC1 1 557 #define CONFIG_TSEC1_NAME "eTSEC1" 558 #define CONFIG_TSEC3 1 559 #define CONFIG_TSEC3_NAME "eTSEC3" 560 561 #define CONFIG_FSL_SGMII_RISER 1 562 #define SGMII_RISER_PHY_OFFSET 0x1c 563 564 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 565 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 566 567 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 568 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 569 570 #define TSEC1_PHYIDX 0 571 #define TSEC3_PHYIDX 0 572 573 #define CONFIG_ETHPRIME "eTSEC1" 574 575 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 576 577 #endif /* CONFIG_TSEC_ENET */ 578 579 /* 580 * Environment 581 */ 582 #define CONFIG_ENV_IS_IN_FLASH 1 583 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 584 #define CONFIG_ENV_ADDR 0xfff80000 585 #else 586 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 587 #endif 588 #define CONFIG_ENV_SIZE 0x2000 589 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 590 591 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 592 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 593 594 /* 595 * Command line configuration. 596 */ 597 #include <config_cmd_default.h> 598 599 #define CONFIG_CMD_IRQ 600 #define CONFIG_CMD_PING 601 #define CONFIG_CMD_I2C 602 #define CONFIG_CMD_MII 603 #define CONFIG_CMD_ELF 604 #define CONFIG_CMD_IRQ 605 #define CONFIG_CMD_SETEXPR 606 607 #if defined(CONFIG_PCI) 608 #define CONFIG_CMD_PCI 609 #define CONFIG_CMD_NET 610 #endif 611 612 #undef CONFIG_WATCHDOG /* watchdog disabled */ 613 614 #define CONFIG_MMC 1 615 616 #ifdef CONFIG_MMC 617 #define CONFIG_FSL_ESDHC 618 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 619 #define CONFIG_CMD_MMC 620 #define CONFIG_GENERIC_MMC 621 #define CONFIG_CMD_EXT2 622 #define CONFIG_CMD_FAT 623 #define CONFIG_DOS_PARTITION 624 #endif 625 626 /* 627 * Miscellaneous configurable options 628 */ 629 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 630 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 631 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 632 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 633 #if defined(CONFIG_CMD_KGDB) 634 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 635 #else 636 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 637 #endif 638 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 639 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 640 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 641 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 642 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 643 644 /* 645 * For booting Linux, the board info and command line data 646 * have to be in the first 16 MB of memory, since this is 647 * the maximum mapped by the Linux kernel during initialization. 648 */ 649 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ 650 651 /* 652 * Internal Definitions 653 * 654 * Boot Flags 655 */ 656 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 657 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 658 659 #if defined(CONFIG_CMD_KGDB) 660 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 661 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 662 #endif 663 664 /* 665 * Environment Configuration 666 */ 667 668 /* The mac addresses for all ethernet interface */ 669 #if defined(CONFIG_TSEC_ENET) 670 #define CONFIG_HAS_ETH0 671 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 672 #define CONFIG_HAS_ETH1 673 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 674 #define CONFIG_HAS_ETH2 675 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 676 #define CONFIG_HAS_ETH3 677 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 678 #endif 679 680 #define CONFIG_IPADDR 192.168.1.254 681 682 #define CONFIG_HOSTNAME unknown 683 #define CONFIG_ROOTPATH /opt/nfsroot 684 #define CONFIG_BOOTFILE uImage 685 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 686 687 #define CONFIG_SERVERIP 192.168.1.1 688 #define CONFIG_GATEWAYIP 192.168.1.1 689 #define CONFIG_NETMASK 255.255.255.0 690 691 /* default location for tftp and bootm */ 692 #define CONFIG_LOADADDR 1000000 693 694 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 695 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 696 697 #define CONFIG_BAUDRATE 115200 698 699 #define CONFIG_EXTRA_ENV_SETTINGS \ 700 "netdev=eth0\0" \ 701 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 702 "tftpflash=tftpboot $loadaddr $uboot; " \ 703 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 704 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 705 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 706 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 707 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 708 "consoledev=ttyS0\0" \ 709 "ramdiskaddr=2000000\0" \ 710 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 711 "fdtaddr=c00000\0" \ 712 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 713 "bdev=sda3\0" \ 714 "usb_phy_type=ulpi\0" 715 716 #define CONFIG_HDBOOT \ 717 "setenv bootargs root=/dev/$bdev rw " \ 718 "console=$consoledev,$baudrate $othbootargs;" \ 719 "tftp $loadaddr $bootfile;" \ 720 "tftp $fdtaddr $fdtfile;" \ 721 "bootm $loadaddr - $fdtaddr" 722 723 #define CONFIG_NFSBOOTCOMMAND \ 724 "setenv bootargs root=/dev/nfs rw " \ 725 "nfsroot=$serverip:$rootpath " \ 726 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 727 "console=$consoledev,$baudrate $othbootargs;" \ 728 "tftp $loadaddr $bootfile;" \ 729 "tftp $fdtaddr $fdtfile;" \ 730 "bootm $loadaddr - $fdtaddr" 731 732 #define CONFIG_RAMBOOTCOMMAND \ 733 "setenv bootargs root=/dev/ram rw " \ 734 "console=$consoledev,$baudrate $othbootargs;" \ 735 "tftp $ramdiskaddr $ramdiskfile;" \ 736 "tftp $loadaddr $bootfile;" \ 737 "tftp $fdtaddr $fdtfile;" \ 738 "bootm $loadaddr $ramdiskaddr $fdtaddr" 739 740 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 741 742 #endif /* __CONFIG_H */ 743