1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Kevin Lam <kevin.lam@freescale.com> 4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef __CONFIG_H 23 #define __CONFIG_H 24 25 /* 26 * High Level Configuration Options 27 */ 28 #define CONFIG_E300 1 /* E300 family */ 29 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 30 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 31 #define CONFIG_MPC837XERDB 1 32 33 #define CONFIG_PCI 1 34 35 #define CONFIG_BOARD_EARLY_INIT_F 36 #define CONFIG_MISC_INIT_R 37 #define CONFIG_HWCONFIG 38 39 /* 40 * On-board devices 41 */ 42 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 43 #define CONFIG_VSC7385_ENET 44 45 /* 46 * System Clock Setup 47 */ 48 #ifdef CONFIG_PCISLAVE 49 #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ 50 #else 51 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 52 #define CONFIG_83XX_GENERIC_PCI 1 53 #define CONFIG_83XX_GENERIC_PCIE 1 54 #endif 55 56 #ifndef CONFIG_SYS_CLK_FREQ 57 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 58 #endif 59 60 /* 61 * Hardware Reset Configuration Word 62 */ 63 #define CONFIG_SYS_HRCW_LOW (\ 64 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 65 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 66 HRCWL_SVCOD_DIV_2 |\ 67 HRCWL_CSB_TO_CLKIN_5X1 |\ 68 HRCWL_CORE_TO_CSB_2X1) 69 70 #ifdef CONFIG_PCISLAVE 71 #define CONFIG_SYS_HRCW_HIGH (\ 72 HRCWH_PCI_AGENT |\ 73 HRCWH_PCI1_ARBITER_DISABLE |\ 74 HRCWH_CORE_ENABLE |\ 75 HRCWH_FROM_0XFFF00100 |\ 76 HRCWH_BOOTSEQ_DISABLE |\ 77 HRCWH_SW_WATCHDOG_DISABLE |\ 78 HRCWH_ROM_LOC_LOCAL_16BIT |\ 79 HRCWH_RL_EXT_LEGACY |\ 80 HRCWH_TSEC1M_IN_RGMII |\ 81 HRCWH_TSEC2M_IN_RGMII |\ 82 HRCWH_BIG_ENDIAN |\ 83 HRCWH_LDP_CLEAR) 84 #else 85 #define CONFIG_SYS_HRCW_HIGH (\ 86 HRCWH_PCI_HOST |\ 87 HRCWH_PCI1_ARBITER_ENABLE |\ 88 HRCWH_CORE_ENABLE |\ 89 HRCWH_FROM_0X00000100 |\ 90 HRCWH_BOOTSEQ_DISABLE |\ 91 HRCWH_SW_WATCHDOG_DISABLE |\ 92 HRCWH_ROM_LOC_LOCAL_16BIT |\ 93 HRCWH_RL_EXT_LEGACY |\ 94 HRCWH_TSEC1M_IN_RGMII |\ 95 HRCWH_TSEC2M_IN_RGMII |\ 96 HRCWH_BIG_ENDIAN |\ 97 HRCWH_LDP_CLEAR) 98 #endif 99 100 /* System performance - define the value i.e. CONFIG_SYS_XXX 101 */ 102 103 /* Arbiter Configuration Register */ 104 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 105 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 106 107 /* System Priority Control Regsiter */ 108 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ 109 110 /* System Clock Configuration Register */ 111 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ 112 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ 113 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ 114 115 /* 116 * System IO Config 117 */ 118 #define CONFIG_SYS_SICRH 0x08200000 119 #define CONFIG_SYS_SICRL 0x00000000 120 121 /* 122 * Output Buffer Impedance 123 */ 124 #define CONFIG_SYS_OBIR 0x30100000 125 126 /* 127 * IMMR new address 128 */ 129 #define CONFIG_SYS_IMMR 0xE0000000 130 131 /* 132 * Device configurations 133 */ 134 135 /* Vitesse 7385 */ 136 137 #ifdef CONFIG_VSC7385_ENET 138 139 #define CONFIG_TSEC2 140 141 /* The flash address and size of the VSC7385 firmware image */ 142 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 143 #define CONFIG_VSC7385_IMAGE_SIZE 8192 144 145 #endif 146 147 /* 148 * DDR Setup 149 */ 150 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 151 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 152 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 153 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 154 #define CONFIG_SYS_83XX_DDR_USES_CS0 155 156 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) 157 158 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 159 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 160 161 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 162 163 /* 164 * Manually set up DDR parameters 165 */ 166 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 167 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 168 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \ 169 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 170 171 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 172 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 173 | (0 << TIMING_CFG0_WRT_SHIFT) \ 174 | (0 << TIMING_CFG0_RRT_SHIFT) \ 175 | (0 << TIMING_CFG0_WWT_SHIFT) \ 176 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 177 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 178 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 179 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 180 /* 0x00220802 */ 181 /* 0x00260802 */ /* DDR400 */ 182 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 183 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 184 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 185 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 186 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 187 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 188 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 189 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 190 /* 0x3935d322 */ 191 /* 0x3937d322 */ 192 #define CONFIG_SYS_DDR_TIMING_2 0x02984cc8 193 194 #define CONFIG_SYS_DDR_INTERVAL ((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \ 195 | (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 196 /* 0x06090100 */ 197 198 #if defined(CONFIG_DDR_2T_TIMING) 199 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 200 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ 201 | SDRAM_CFG_2T_EN \ 202 | SDRAM_CFG_DBW_32) 203 #else 204 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 205 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT) 206 /* 0x43000000 */ 207 #endif 208 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 209 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 210 | (0x0442 << SDRAM_MODE_SD_SHIFT)) 211 /* 0x04400442 */ /* DDR400 */ 212 #define CONFIG_SYS_DDR_MODE2 0x00000000 213 214 /* 215 * Memory test 216 */ 217 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 218 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 219 #define CONFIG_SYS_MEMTEST_END 0x0ef70010 220 221 /* 222 * The reserved memory 223 */ 224 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 225 226 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 227 #define CONFIG_SYS_RAMBOOT 228 #else 229 #undef CONFIG_SYS_RAMBOOT 230 #endif 231 232 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 233 #define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */ 234 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 235 236 /* 237 * Initial RAM Base Address Setup 238 */ 239 #define CONFIG_SYS_INIT_RAM_LOCK 1 240 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 241 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ 242 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 243 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 244 245 /* 246 * Local Bus Configuration & Clock Setup 247 */ 248 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) 249 #define CONFIG_SYS_LBC_LBCR 0x00000000 250 251 /* 252 * FLASH on the Local Bus 253 */ 254 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 255 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 256 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 257 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ 258 259 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 260 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 261 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 262 263 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ 264 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 265 266 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ 267 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 268 BR_V) /* valid */ 269 #define CONFIG_SYS_OR0_PRELIM (0xFF800000 /* 8 MByte */ \ 270 | OR_GPCM_XACS \ 271 | OR_GPCM_SCY_9 \ 272 | OR_GPCM_EHTR \ 273 | OR_GPCM_EAD) 274 /* 0xFF806FF7 TODO SLOW 8 MB flash size */ 275 276 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 277 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 278 279 #undef CONFIG_SYS_FLASH_CHECKSUM 280 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 281 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 282 283 /* 284 * NAND Flash on the Local Bus 285 */ 286 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 287 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | \ 288 (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \ 289 BR_PS_8 | /* Port Size = 8 bit */ \ 290 BR_MS_FCM | /* MSEL = FCM */ \ 291 BR_V) /* valid */ 292 #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | /* length 32K */ \ 293 OR_FCM_CSCT | \ 294 OR_FCM_CST | \ 295 OR_FCM_CHT | \ 296 OR_FCM_SCY_1 | \ 297 OR_FCM_TRLX | \ 298 OR_FCM_EHTR) 299 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 300 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 301 302 /* Vitesse 7385 */ 303 304 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 305 306 #ifdef CONFIG_VSC7385_ENET 307 308 #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* Base address */ 309 #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* 128K bytes*/ 310 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE /* Access Base */ 311 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */ 312 313 #endif 314 315 /* 316 * Serial Port 317 */ 318 #define CONFIG_CONS_INDEX 1 319 #undef CONFIG_SERIAL_SOFTWARE_FIFO 320 #define CONFIG_SYS_NS16550 321 #define CONFIG_SYS_NS16550_SERIAL 322 #define CONFIG_SYS_NS16550_REG_SIZE 1 323 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 324 325 #define CONFIG_SYS_BAUDRATE_TABLE \ 326 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 327 328 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 329 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 330 331 /* SERDES */ 332 #define CONFIG_FSL_SERDES 333 #define CONFIG_FSL_SERDES1 0xe3000 334 #define CONFIG_FSL_SERDES2 0xe3100 335 336 /* Use the HUSH parser */ 337 #define CONFIG_SYS_HUSH_PARSER 338 #ifdef CONFIG_SYS_HUSH_PARSER 339 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 340 #endif 341 342 /* Pass open firmware flat tree */ 343 #define CONFIG_OF_LIBFDT 1 344 #define CONFIG_OF_BOARD_SETUP 1 345 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 346 347 #define CONFIG_SYS_64BIT_STRTOUL 1 348 #define CONFIG_SYS_64BIT_VSPRINTF 1 349 350 /* I2C */ 351 #define CONFIG_HARD_I2C /* I2C with hardware support */ 352 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 353 #define CONFIG_FSL_I2C 354 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 355 #define CONFIG_SYS_I2C_SLAVE 0x7F 356 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 357 #define CONFIG_SYS_I2C_OFFSET 0x3000 358 #define CONFIG_SYS_I2C2_OFFSET 0x3100 359 360 /* 361 * Config on-board RTC 362 */ 363 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 364 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 365 366 /* 367 * General PCI 368 * Addresses are mapped 1-1. 369 */ 370 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 371 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 372 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 373 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 374 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 375 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 376 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 377 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 378 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 379 380 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 381 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 382 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 383 384 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 385 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 386 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 387 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 388 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 389 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 390 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 391 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 392 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 393 394 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 395 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 396 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 397 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 398 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 399 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 400 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 401 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 402 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 403 404 #ifdef CONFIG_PCI 405 #define CONFIG_NET_MULTI 406 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 407 408 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 409 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 410 #endif /* CONFIG_PCI */ 411 412 /* 413 * TSEC 414 */ 415 #ifdef CONFIG_TSEC_ENET 416 417 #define CONFIG_NET_MULTI 418 #define CONFIG_GMII /* MII PHY management */ 419 420 #define CONFIG_TSEC1 421 422 #ifdef CONFIG_TSEC1 423 #define CONFIG_HAS_ETH0 424 #define CONFIG_TSEC1_NAME "TSEC0" 425 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 426 #define TSEC1_PHY_ADDR 2 427 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 428 #define TSEC1_PHYIDX 0 429 #endif 430 431 #ifdef CONFIG_TSEC2 432 #define CONFIG_HAS_ETH1 433 #define CONFIG_TSEC2_NAME "TSEC1" 434 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 435 #define TSEC2_PHY_ADDR 0x1c 436 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 437 #define TSEC2_PHYIDX 0 438 #endif 439 440 /* Options are: TSEC[0-1] */ 441 #define CONFIG_ETHPRIME "TSEC0" 442 443 #endif 444 445 /* 446 * SATA 447 */ 448 #define CONFIG_LIBATA 449 #define CONFIG_FSL_SATA 450 451 #define CONFIG_SYS_SATA_MAX_DEVICE 2 452 #define CONFIG_SATA1 453 #define CONFIG_SYS_SATA1_OFFSET 0x18000 454 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 455 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 456 #define CONFIG_SATA2 457 #define CONFIG_SYS_SATA2_OFFSET 0x19000 458 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 459 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 460 461 #ifdef CONFIG_FSL_SATA 462 #define CONFIG_LBA48 463 #define CONFIG_CMD_SATA 464 #define CONFIG_DOS_PARTITION 465 #define CONFIG_CMD_EXT2 466 #endif 467 468 /* 469 * Environment 470 */ 471 #ifndef CONFIG_SYS_RAMBOOT 472 #define CONFIG_ENV_IS_IN_FLASH 1 473 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) 474 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ 475 #define CONFIG_ENV_SIZE 0x4000 476 #else 477 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 478 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 479 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) 480 #define CONFIG_ENV_SIZE 0x2000 481 #endif 482 483 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 484 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 485 486 /* 487 * BOOTP options 488 */ 489 #define CONFIG_BOOTP_BOOTFILESIZE 490 #define CONFIG_BOOTP_BOOTPATH 491 #define CONFIG_BOOTP_GATEWAY 492 #define CONFIG_BOOTP_HOSTNAME 493 494 495 /* 496 * Command line configuration. 497 */ 498 #include <config_cmd_default.h> 499 500 #define CONFIG_CMD_PING 501 #define CONFIG_CMD_I2C 502 #define CONFIG_CMD_MII 503 #define CONFIG_CMD_DATE 504 505 #if defined(CONFIG_PCI) 506 #define CONFIG_CMD_PCI 507 #endif 508 509 #if defined(CONFIG_SYS_RAMBOOT) 510 #undef CONFIG_CMD_SAVEENV 511 #undef CONFIG_CMD_LOADS 512 #endif 513 514 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 515 516 #undef CONFIG_WATCHDOG /* watchdog disabled */ 517 518 #define CONFIG_MMC 1 519 520 #ifdef CONFIG_MMC 521 #define CONFIG_FSL_ESDHC 522 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 523 #define CONFIG_CMD_MMC 524 #define CONFIG_GENERIC_MMC 525 #define CONFIG_CMD_EXT2 526 #define CONFIG_CMD_FAT 527 #define CONFIG_DOS_PARTITION 528 #endif 529 530 /* 531 * Miscellaneous configurable options 532 */ 533 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 534 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 535 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 536 537 #if defined(CONFIG_CMD_KGDB) 538 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 539 #else 540 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 541 #endif 542 543 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 544 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 545 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 546 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 547 548 /* 549 * For booting Linux, the board info and command line data 550 * have to be in the first 8 MB of memory, since this is 551 * the maximum mapped by the Linux kernel during initialization. 552 */ 553 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 554 555 /* 556 * Core HID Setup 557 */ 558 #define CONFIG_SYS_HID0_INIT 0x000000000 559 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 560 #define CONFIG_SYS_HID2 HID2_HBE 561 562 /* 563 * MMU Setup 564 */ 565 566 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 567 568 /* DDR: cache cacheable */ 569 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 570 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 571 572 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) 573 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) 574 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 575 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 576 577 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) 578 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) 579 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 580 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 581 582 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 583 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 584 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 585 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) 586 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 587 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 588 589 /* L2 Switch: cache-inhibit and guarded */ 590 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE | BATL_PP_10 | \ 591 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 592 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP) 593 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 594 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 595 596 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 597 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 598 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 599 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ 600 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 601 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 602 603 /* Stack in dcache: cacheable, no memory coherence */ 604 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) 605 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 606 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 607 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 608 609 #ifdef CONFIG_PCI 610 /* PCI MEM space: cacheable */ 611 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 612 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 613 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 614 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 615 /* PCI MMIO space: cache-inhibit and guarded */ 616 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ 617 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 618 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 619 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 620 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 621 #else 622 #define CONFIG_SYS_IBAT6L (0) 623 #define CONFIG_SYS_IBAT6U (0) 624 #define CONFIG_SYS_IBAT7L (0) 625 #define CONFIG_SYS_IBAT7U (0) 626 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 627 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 628 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 629 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 630 #endif 631 632 /* 633 * Internal Definitions 634 * 635 * Boot Flags 636 */ 637 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 638 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 639 640 #if defined(CONFIG_CMD_KGDB) 641 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 642 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 643 #endif 644 645 /* 646 * Environment Configuration 647 */ 648 #define CONFIG_ENV_OVERWRITE 649 650 #ifdef CONFIG_HAS_ETH0 651 #define CONFIG_ETHADDR 00:04:9f:ef:04:01 652 #endif 653 654 #ifdef CONFIG_HAS_ETH1 655 #define CONFIG_ETH1ADDR 00:04:9f:ef:04:02 656 #endif 657 658 #define CONFIG_HAS_FSL_DR_USB 659 660 #define CONFIG_IPADDR 10.0.0.2 661 #define CONFIG_SERVERIP 10.0.0.1 662 #define CONFIG_GATEWAYIP 10.0.0.1 663 #define CONFIG_NETMASK 255.0.0.0 664 #define CONFIG_NETDEV eth1 665 666 #define CONFIG_HOSTNAME mpc837x_rdb 667 #define CONFIG_ROOTPATH /nfsroot 668 #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot 669 #define CONFIG_BOOTFILE uImage 670 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 671 #define CONFIG_FDTFILE mpc8379_rdb.dtb 672 673 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ 674 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 675 #define CONFIG_BAUDRATE 115200 676 677 #define XMK_STR(x) #x 678 #define MK_STR(x) XMK_STR(x) 679 680 #define CONFIG_EXTRA_ENV_SETTINGS \ 681 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 682 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 683 "tftpflash=tftp $loadaddr $uboot;" \ 684 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 685 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 686 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 687 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 688 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 689 "fdtaddr=400000\0" \ 690 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 691 "ramdiskaddr=1000000\0" \ 692 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ 693 "console=ttyS0\0" \ 694 "setbootargs=setenv bootargs " \ 695 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 696 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 697 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 698 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 699 700 #define CONFIG_NFSBOOTCOMMAND \ 701 "setenv rootdev /dev/nfs;" \ 702 "run setbootargs;" \ 703 "run setipargs;" \ 704 "tftp $loadaddr $bootfile;" \ 705 "tftp $fdtaddr $fdtfile;" \ 706 "bootm $loadaddr - $fdtaddr" 707 708 #define CONFIG_RAMBOOTCOMMAND \ 709 "setenv rootdev /dev/ram;" \ 710 "run setbootargs;" \ 711 "tftp $ramdiskaddr $ramdiskfile;" \ 712 "tftp $loadaddr $bootfile;" \ 713 "tftp $fdtaddr $fdtfile;" \ 714 "bootm $loadaddr $ramdiskaddr $fdtaddr" 715 716 #undef MK_STR 717 #undef XMK_STR 718 719 #endif /* __CONFIG_H */ 720