1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Kevin Lam <kevin.lam@freescale.com> 4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef __CONFIG_H 23 #define __CONFIG_H 24 25 /* 26 * High Level Configuration Options 27 */ 28 #define CONFIG_E300 1 /* E300 family */ 29 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 30 #define CONFIG_MPC837X 1 /* MPC837X CPU specific */ 31 #define CONFIG_MPC837XERDB 1 32 33 #define CONFIG_PCI 1 34 35 #define CONFIG_MISC_INIT_R 36 37 /* 38 * On-board devices 39 */ 40 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 41 #define CONFIG_VSC7385_ENET 42 43 /* 44 * System Clock Setup 45 */ 46 #ifdef CONFIG_PCISLAVE 47 #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ 48 #else 49 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 50 #define CONFIG_83XX_GENERIC_PCI 1 51 #endif 52 53 #ifndef CONFIG_SYS_CLK_FREQ 54 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 55 #endif 56 57 /* 58 * Hardware Reset Configuration Word 59 */ 60 #define CFG_HRCW_LOW (\ 61 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 62 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 63 HRCWL_SVCOD_DIV_2 |\ 64 HRCWL_CSB_TO_CLKIN_5X1 |\ 65 HRCWL_CORE_TO_CSB_2X1) 66 67 #ifdef CONFIG_PCISLAVE 68 #define CFG_HRCW_HIGH (\ 69 HRCWH_PCI_AGENT |\ 70 HRCWH_PCI1_ARBITER_DISABLE |\ 71 HRCWH_CORE_ENABLE |\ 72 HRCWH_FROM_0XFFF00100 |\ 73 HRCWH_BOOTSEQ_DISABLE |\ 74 HRCWH_SW_WATCHDOG_DISABLE |\ 75 HRCWH_ROM_LOC_LOCAL_16BIT |\ 76 HRCWH_RL_EXT_LEGACY |\ 77 HRCWH_TSEC1M_IN_RGMII |\ 78 HRCWH_TSEC2M_IN_RGMII |\ 79 HRCWH_BIG_ENDIAN |\ 80 HRCWH_LDP_CLEAR) 81 #else 82 #define CFG_HRCW_HIGH (\ 83 HRCWH_PCI_HOST |\ 84 HRCWH_PCI1_ARBITER_ENABLE |\ 85 HRCWH_CORE_ENABLE |\ 86 HRCWH_FROM_0X00000100 |\ 87 HRCWH_BOOTSEQ_DISABLE |\ 88 HRCWH_SW_WATCHDOG_DISABLE |\ 89 HRCWH_ROM_LOC_LOCAL_16BIT |\ 90 HRCWH_RL_EXT_LEGACY |\ 91 HRCWH_TSEC1M_IN_RGMII |\ 92 HRCWH_TSEC2M_IN_RGMII |\ 93 HRCWH_BIG_ENDIAN |\ 94 HRCWH_LDP_CLEAR) 95 #endif 96 97 /* System performance - define the value i.e. CFG_XXX 98 */ 99 100 /* Arbiter Configuration Register */ 101 #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 102 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 103 104 /* System Priority Control Regsiter */ 105 #define CFG_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ 106 107 /* System Clock Configuration Register */ 108 #define CFG_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ 109 #define CFG_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ 110 #define CFG_SCCR_SATACM SCCR_SATACM_1 /* SATA1-4 clock mode (0-3) */ 111 112 /* 113 * System IO Config 114 */ 115 #define CFG_SICRH 0x08200000 116 #define CFG_SICRL 0x00000000 117 118 /* 119 * Output Buffer Impedance 120 */ 121 #define CFG_OBIR 0x30100000 122 123 /* 124 * IMMR new address 125 */ 126 #define CFG_IMMR 0xE0000000 127 128 /* 129 * Device configurations 130 */ 131 132 /* Vitesse 7385 */ 133 134 #ifdef CONFIG_VSC7385_ENET 135 136 #define CONFIG_TSEC2 137 138 /* The flash address and size of the VSC7385 firmware image */ 139 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 140 #define CONFIG_VSC7385_IMAGE_SIZE 8192 141 142 #endif 143 144 /* 145 * DDR Setup 146 */ 147 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ 148 #define CFG_SDRAM_BASE CFG_DDR_BASE 149 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 150 #define CFG_DDR_SDRAM_CLK_CNTL 0x03000000 151 #define CFG_83XX_DDR_USES_CS0 152 153 #define CFG_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) 154 155 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 156 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 157 158 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 159 160 /* 161 * Manually set up DDR parameters 162 */ 163 #define CFG_DDR_SIZE 256 /* MB */ 164 #define CFG_DDR_CS0_BNDS 0x0000000f 165 #define CFG_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \ 166 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 167 168 #define CFG_DDR_TIMING_3 0x00000000 169 #define CFG_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 170 | (0 << TIMING_CFG0_WRT_SHIFT) \ 171 | (0 << TIMING_CFG0_RRT_SHIFT) \ 172 | (0 << TIMING_CFG0_WWT_SHIFT) \ 173 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 174 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 175 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 176 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 177 /* 0x00220802 */ 178 /* 0x00260802 */ /* DDR400 */ 179 #define CFG_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 180 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 181 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 182 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 183 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 184 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 185 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 186 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 187 /* 0x3935d322 */ 188 /* 0x3937d322 */ 189 #define CFG_DDR_TIMING_2 0x02984cc8 190 191 #define CFG_DDR_INTERVAL ((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \ 192 | (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 193 /* 0x06090100 */ 194 195 #if defined(CONFIG_DDR_2T_TIMING) 196 #define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 197 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ 198 | SDRAM_CFG_2T_EN \ 199 | SDRAM_CFG_DBW_32) 200 #else 201 #define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 202 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT) 203 /* 0x43000000 */ 204 #endif 205 #define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 206 #define CFG_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 207 | (0x0442 << SDRAM_MODE_SD_SHIFT)) 208 /* 0x04400442 */ /* DDR400 */ 209 #define CFG_DDR_MODE2 0x00000000; 210 211 /* 212 * Memory test 213 */ 214 #undef CFG_DRAM_TEST /* memory test, takes time */ 215 #define CFG_MEMTEST_START 0x00040000 /* memtest region */ 216 #define CFG_MEMTEST_END 0x0ef70010 217 218 /* 219 * The reserved memory 220 */ 221 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 222 223 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 224 #define CFG_RAMBOOT 225 #else 226 #undef CFG_RAMBOOT 227 #endif 228 229 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 230 #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 231 232 /* 233 * Initial RAM Base Address Setup 234 */ 235 #define CFG_INIT_RAM_LOCK 1 236 #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 237 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ 238 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 239 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 240 241 /* 242 * Local Bus Configuration & Clock Setup 243 */ 244 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) 245 #define CFG_LBC_LBCR 0x00000000 246 247 /* 248 * FLASH on the Local Bus 249 */ 250 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 251 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 252 #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ 253 #define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */ 254 255 #define CFG_FLASH_EMPTY_INFO /* display empty sectors */ 256 #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 257 258 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 259 #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 260 261 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ 262 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 263 BR_V) /* valid */ 264 #define CFG_OR0_PRELIM (0xFF800000 /* 8 MByte */ \ 265 | OR_GPCM_XACS \ 266 | OR_GPCM_SCY_9 \ 267 | OR_GPCM_EHTR \ 268 | OR_GPCM_EAD) 269 /* 0xFF806FF7 TODO SLOW 8 MB flash size */ 270 271 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 272 #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ 273 274 #undef CFG_FLASH_CHECKSUM 275 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 276 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 277 278 /* 279 * NAND Flash on the Local Bus 280 */ 281 #define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ 282 #define CFG_BR1_PRELIM (CFG_NAND_BASE | \ 283 (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \ 284 BR_PS_8 | /* Port Size = 8 bit */ \ 285 BR_MS_FCM | /* MSEL = FCM */ \ 286 BR_V) /* valid */ 287 #define CFG_OR1_PRELIM (0xFFFF8000 | /* length 32K */ \ 288 OR_FCM_CSCT | \ 289 OR_FCM_CST | \ 290 OR_FCM_CHT | \ 291 OR_FCM_SCY_1 | \ 292 OR_FCM_TRLX | \ 293 OR_FCM_EHTR) 294 #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE 295 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 296 297 /* Vitesse 7385 */ 298 299 #define CFG_VSC7385_BASE 0xF0000000 300 301 #ifdef CONFIG_VSC7385_ENET 302 303 #define CFG_BR2_PRELIM 0xf0000801 /* Base address */ 304 #define CFG_OR2_PRELIM 0xfffe09ff /* 128K bytes*/ 305 #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE /* Access Base */ 306 #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */ 307 308 #endif 309 310 /* 311 * Serial Port 312 */ 313 #define CONFIG_CONS_INDEX 1 314 #undef CONFIG_SERIAL_SOFTWARE_FIFO 315 #define CFG_NS16550 316 #define CFG_NS16550_SERIAL 317 #define CFG_NS16550_REG_SIZE 1 318 #define CFG_NS16550_CLK get_bus_freq(0) 319 320 #define CFG_BAUDRATE_TABLE \ 321 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 322 323 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 324 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 325 326 /* Use the HUSH parser */ 327 #define CFG_HUSH_PARSER 328 #ifdef CFG_HUSH_PARSER 329 #define CFG_PROMPT_HUSH_PS2 "> " 330 #endif 331 332 /* Pass open firmware flat tree */ 333 #define CONFIG_OF_LIBFDT 1 334 #define CONFIG_OF_BOARD_SETUP 1 335 336 /* I2C */ 337 #define CONFIG_HARD_I2C /* I2C with hardware support */ 338 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 339 #define CONFIG_FSL_I2C 340 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 341 #define CFG_I2C_SLAVE 0x7F 342 #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 343 #define CFG_I2C_OFFSET 0x3000 344 #define CFG_I2C2_OFFSET 0x3100 345 346 /* 347 * Config on-board RTC 348 */ 349 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 350 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 351 352 /* 353 * General PCI 354 * Addresses are mapped 1-1. 355 */ 356 #define CFG_PCI_MEM_BASE 0x80000000 357 #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE 358 #define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ 359 #define CFG_PCI_MMIO_BASE 0x90000000 360 #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE 361 #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ 362 #define CFG_PCI_IO_BASE 0xE0300000 363 #define CFG_PCI_IO_PHYS 0xE0300000 364 #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ 365 366 #define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE 367 #define CFG_PCI_SLV_MEM_BUS 0x00000000 368 #define CFG_PCI_SLV_MEM_SIZE 0x80000000 369 370 #ifdef CONFIG_PCI 371 #define CONFIG_NET_MULTI 372 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 373 374 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 375 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 376 #endif /* CONFIG_PCI */ 377 378 /* 379 * TSEC 380 */ 381 #ifdef CONFIG_TSEC_ENET 382 383 #define CONFIG_NET_MULTI 384 #define CONFIG_GMII /* MII PHY management */ 385 386 #define CONFIG_TSEC1 387 388 #ifdef CONFIG_TSEC1 389 #define CONFIG_HAS_ETH0 390 #define CONFIG_TSEC1_NAME "TSEC0" 391 #define CFG_TSEC1_OFFSET 0x24000 392 #define TSEC1_PHY_ADDR 2 393 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 394 #define TSEC1_PHYIDX 0 395 #endif 396 397 #ifdef CONFIG_TSEC2 398 #define CONFIG_HAS_ETH1 399 #define CONFIG_TSEC2_NAME "TSEC1" 400 #define CFG_TSEC2_OFFSET 0x25000 401 #define TSEC2_PHY_ADDR 0x1c 402 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 403 #define TSEC2_PHYIDX 0 404 #endif 405 406 /* Options are: TSEC[0-1] */ 407 #define CONFIG_ETHPRIME "TSEC0" 408 409 #endif 410 411 /* 412 * Environment 413 */ 414 #ifndef CFG_RAMBOOT 415 #define CFG_ENV_IS_IN_FLASH 1 416 #define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN) 417 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ 418 #define CFG_ENV_SIZE 0x4000 419 #else 420 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 421 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 422 #define CFG_ENV_ADDR (CFG_MONITOR_BASE-0x1000) 423 #define CFG_ENV_SIZE 0x2000 424 #endif 425 426 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 427 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 428 429 /* 430 * BOOTP options 431 */ 432 #define CONFIG_BOOTP_BOOTFILESIZE 433 #define CONFIG_BOOTP_BOOTPATH 434 #define CONFIG_BOOTP_GATEWAY 435 #define CONFIG_BOOTP_HOSTNAME 436 437 438 /* 439 * Command line configuration. 440 */ 441 #include <config_cmd_default.h> 442 443 #define CONFIG_CMD_PING 444 #define CONFIG_CMD_I2C 445 #define CONFIG_CMD_MII 446 #define CONFIG_CMD_DATE 447 448 #if defined(CONFIG_PCI) 449 #define CONFIG_CMD_PCI 450 #endif 451 452 #if defined(CFG_RAMBOOT) 453 #undef CONFIG_CMD_ENV 454 #undef CONFIG_CMD_LOADS 455 #endif 456 457 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 458 459 #undef CONFIG_WATCHDOG /* watchdog disabled */ 460 461 /* 462 * Miscellaneous configurable options 463 */ 464 #define CFG_LONGHELP /* undef to save memory */ 465 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 466 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 467 468 #if defined(CONFIG_CMD_KGDB) 469 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 470 #else 471 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 472 #endif 473 474 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 475 #define CFG_MAXARGS 16 /* max number of command args */ 476 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 477 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 478 479 /* 480 * For booting Linux, the board info and command line data 481 * have to be in the first 8 MB of memory, since this is 482 * the maximum mapped by the Linux kernel during initialization. 483 */ 484 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 485 486 /* 487 * Core HID Setup 488 */ 489 #define CFG_HID0_INIT 0x000000000 490 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 491 #define CFG_HID2 HID2_HBE 492 493 /* 494 * MMU Setup 495 */ 496 497 /* DDR: cache cacheable */ 498 #define CFG_SDRAM_LOWER CFG_SDRAM_BASE 499 #define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) 500 501 #define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) 502 #define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) 503 #define CFG_DBAT0L CFG_IBAT0L 504 #define CFG_DBAT0U CFG_IBAT0U 505 506 #define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) 507 #define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) 508 #define CFG_DBAT1L CFG_IBAT1L 509 #define CFG_DBAT1U CFG_IBAT1U 510 511 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 512 #define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \ 513 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 514 #define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) 515 #define CFG_DBAT2L CFG_IBAT2L 516 #define CFG_DBAT2U CFG_IBAT2U 517 518 /* L2 Switch: cache-inhibit and guarded */ 519 #define CFG_IBAT3L (CFG_VSC7385_BASE | BATL_PP_10 | \ 520 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 521 #define CFG_IBAT3U (CFG_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP) 522 #define CFG_DBAT3L CFG_IBAT3L 523 #define CFG_DBAT3U CFG_IBAT3U 524 525 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 526 #define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 527 #define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 528 #define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \ 529 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 530 #define CFG_DBAT4U CFG_IBAT4U 531 532 /* Stack in dcache: cacheable, no memory coherence */ 533 #define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) 534 #define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 535 #define CFG_DBAT5L CFG_IBAT5L 536 #define CFG_DBAT5U CFG_IBAT5U 537 538 #ifdef CONFIG_PCI 539 /* PCI MEM space: cacheable */ 540 #define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 541 #define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 542 #define CFG_DBAT6L CFG_IBAT6L 543 #define CFG_DBAT6U CFG_IBAT6U 544 /* PCI MMIO space: cache-inhibit and guarded */ 545 #define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ 546 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 547 #define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 548 #define CFG_DBAT7L CFG_IBAT7L 549 #define CFG_DBAT7U CFG_IBAT7U 550 #else 551 #define CFG_IBAT6L (0) 552 #define CFG_IBAT6U (0) 553 #define CFG_IBAT7L (0) 554 #define CFG_IBAT7U (0) 555 #define CFG_DBAT6L CFG_IBAT6L 556 #define CFG_DBAT6U CFG_IBAT6U 557 #define CFG_DBAT7L CFG_IBAT7L 558 #define CFG_DBAT7U CFG_IBAT7U 559 #endif 560 561 /* 562 * Internal Definitions 563 * 564 * Boot Flags 565 */ 566 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 567 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 568 569 #if defined(CONFIG_CMD_KGDB) 570 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 571 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 572 #endif 573 574 /* 575 * Environment Configuration 576 */ 577 #define CONFIG_ENV_OVERWRITE 578 579 #ifdef CONFIG_HAS_ETH0 580 #define CONFIG_ETHADDR 00:04:9f:ef:04:01 581 #endif 582 583 #ifdef CONFIG_HAS_ETH1 584 #define CONFIG_ETH1ADDR 00:04:9f:ef:04:02 585 #endif 586 587 #define CONFIG_IPADDR 10.0.0.2 588 #define CONFIG_SERVERIP 10.0.0.1 589 #define CONFIG_GATEWAYIP 10.0.0.1 590 #define CONFIG_NETMASK 255.0.0.0 591 #define CONFIG_NETDEV eth1 592 593 #define CONFIG_HOSTNAME mpc837x_rdb 594 #define CONFIG_ROOTPATH /nfsroot 595 #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot 596 #define CONFIG_BOOTFILE uImage 597 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 598 #define CONFIG_FDTFILE mpc8379_rdb.dtb 599 600 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 601 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 602 #define CONFIG_BAUDRATE 115200 603 604 #define XMK_STR(x) #x 605 #define MK_STR(x) XMK_STR(x) 606 607 #define CONFIG_EXTRA_ENV_SETTINGS \ 608 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 609 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 610 "tftpflash=tftp $loadaddr $uboot;" \ 611 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 612 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 613 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 614 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 615 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 616 "fdtaddr=400000\0" \ 617 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 618 "ramdiskaddr=1000000\0" \ 619 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ 620 "console=ttyS0\0" \ 621 "setbootargs=setenv bootargs " \ 622 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 623 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 624 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 625 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 626 627 #define CONFIG_NFSBOOTCOMMAND \ 628 "setenv rootdev /dev/nfs;" \ 629 "run setbootargs;" \ 630 "run setipargs;" \ 631 "tftp $loadaddr $bootfile;" \ 632 "tftp $fdtaddr $fdtfile;" \ 633 "bootm $loadaddr - $fdtaddr" 634 635 #define CONFIG_RAMBOOTCOMMAND \ 636 "setenv rootdev /dev/ram;" \ 637 "run setbootargs;" \ 638 "tftp $ramdiskaddr $ramdiskfile;" \ 639 "tftp $loadaddr $bootfile;" \ 640 "tftp $fdtaddr $fdtfile;" \ 641 "bootm $loadaddr $ramdiskaddr $fdtaddr" 642 643 #undef MK_STR 644 #undef XMK_STR 645 646 #endif /* __CONFIG_H */ 647