1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Kevin Lam <kevin.lam@freescale.com> 4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef __CONFIG_H 23 #define __CONFIG_H 24 25 /* 26 * High Level Configuration Options 27 */ 28 #define CONFIG_E300 1 /* E300 family */ 29 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 30 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 31 #define CONFIG_MPC837XERDB 1 32 33 #define CONFIG_SYS_TEXT_BASE 0xFE000000 34 35 #define CONFIG_PCI 1 36 37 #define CONFIG_BOARD_EARLY_INIT_F 38 #define CONFIG_MISC_INIT_R 39 #define CONFIG_HWCONFIG 40 41 /* 42 * On-board devices 43 */ 44 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 45 #define CONFIG_VSC7385_ENET 46 47 /* 48 * System Clock Setup 49 */ 50 #ifdef CONFIG_PCISLAVE 51 #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ 52 #else 53 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 54 #define CONFIG_PCIE 55 #endif 56 57 #ifndef CONFIG_SYS_CLK_FREQ 58 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 59 #endif 60 61 /* 62 * Hardware Reset Configuration Word 63 */ 64 #define CONFIG_SYS_HRCW_LOW (\ 65 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 66 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 67 HRCWL_SVCOD_DIV_2 |\ 68 HRCWL_CSB_TO_CLKIN_5X1 |\ 69 HRCWL_CORE_TO_CSB_2X1) 70 71 #ifdef CONFIG_PCISLAVE 72 #define CONFIG_SYS_HRCW_HIGH (\ 73 HRCWH_PCI_AGENT |\ 74 HRCWH_PCI1_ARBITER_DISABLE |\ 75 HRCWH_CORE_ENABLE |\ 76 HRCWH_FROM_0XFFF00100 |\ 77 HRCWH_BOOTSEQ_DISABLE |\ 78 HRCWH_SW_WATCHDOG_DISABLE |\ 79 HRCWH_ROM_LOC_LOCAL_16BIT |\ 80 HRCWH_RL_EXT_LEGACY |\ 81 HRCWH_TSEC1M_IN_RGMII |\ 82 HRCWH_TSEC2M_IN_RGMII |\ 83 HRCWH_BIG_ENDIAN |\ 84 HRCWH_LDP_CLEAR) 85 #else 86 #define CONFIG_SYS_HRCW_HIGH (\ 87 HRCWH_PCI_HOST |\ 88 HRCWH_PCI1_ARBITER_ENABLE |\ 89 HRCWH_CORE_ENABLE |\ 90 HRCWH_FROM_0X00000100 |\ 91 HRCWH_BOOTSEQ_DISABLE |\ 92 HRCWH_SW_WATCHDOG_DISABLE |\ 93 HRCWH_ROM_LOC_LOCAL_16BIT |\ 94 HRCWH_RL_EXT_LEGACY |\ 95 HRCWH_TSEC1M_IN_RGMII |\ 96 HRCWH_TSEC2M_IN_RGMII |\ 97 HRCWH_BIG_ENDIAN |\ 98 HRCWH_LDP_CLEAR) 99 #endif 100 101 /* System performance - define the value i.e. CONFIG_SYS_XXX 102 */ 103 104 /* Arbiter Configuration Register */ 105 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 106 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 107 108 /* System Priority Control Regsiter */ 109 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ 110 111 /* System Clock Configuration Register */ 112 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ 113 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ 114 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ 115 116 /* 117 * System IO Config 118 */ 119 #define CONFIG_SYS_SICRH 0x08200000 120 #define CONFIG_SYS_SICRL 0x00000000 121 122 /* 123 * Output Buffer Impedance 124 */ 125 #define CONFIG_SYS_OBIR 0x30100000 126 127 /* 128 * IMMR new address 129 */ 130 #define CONFIG_SYS_IMMR 0xE0000000 131 132 /* 133 * Device configurations 134 */ 135 136 /* Vitesse 7385 */ 137 138 #ifdef CONFIG_VSC7385_ENET 139 140 #define CONFIG_TSEC2 141 142 /* The flash address and size of the VSC7385 firmware image */ 143 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 144 #define CONFIG_VSC7385_IMAGE_SIZE 8192 145 146 #endif 147 148 /* 149 * DDR Setup 150 */ 151 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 152 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 153 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 154 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 155 #define CONFIG_SYS_83XX_DDR_USES_CS0 156 157 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) 158 159 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 160 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 161 162 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 163 164 /* 165 * Manually set up DDR parameters 166 */ 167 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 168 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 169 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \ 170 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 171 172 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 173 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 174 | (0 << TIMING_CFG0_WRT_SHIFT) \ 175 | (0 << TIMING_CFG0_RRT_SHIFT) \ 176 | (0 << TIMING_CFG0_WWT_SHIFT) \ 177 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 178 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 179 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 180 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 181 /* 0x00220802 */ 182 /* 0x00260802 */ /* DDR400 */ 183 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 184 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 185 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 186 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 187 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 188 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 189 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 190 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 191 /* 0x3935d322 */ 192 /* 0x3937d322 */ 193 #define CONFIG_SYS_DDR_TIMING_2 0x02984cc8 194 195 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ 196 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 197 /* 0x06090100 */ 198 199 #if defined(CONFIG_DDR_2T_TIMING) 200 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 201 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ 202 | SDRAM_CFG_2T_EN \ 203 | SDRAM_CFG_DBW_32) 204 #else 205 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 206 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT) 207 /* 0x43000000 */ 208 #endif 209 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 210 #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ 211 | (0x0442 << SDRAM_MODE_SD_SHIFT)) 212 /* 0x04400442 */ /* DDR400 */ 213 #define CONFIG_SYS_DDR_MODE2 0x00000000 214 215 /* 216 * Memory test 217 */ 218 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 219 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 220 #define CONFIG_SYS_MEMTEST_END 0x0ef70010 221 222 /* 223 * The reserved memory 224 */ 225 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 226 227 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 228 #define CONFIG_SYS_RAMBOOT 229 #else 230 #undef CONFIG_SYS_RAMBOOT 231 #endif 232 233 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 234 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 235 236 /* 237 * Initial RAM Base Address Setup 238 */ 239 #define CONFIG_SYS_INIT_RAM_LOCK 1 240 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 241 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ 242 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 243 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 244 245 /* 246 * Local Bus Configuration & Clock Setup 247 */ 248 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 249 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 250 #define CONFIG_SYS_LBC_LBCR 0x00000000 251 #define CONFIG_FSL_ELBC 1 252 253 /* 254 * FLASH on the Local Bus 255 */ 256 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 257 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 258 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 259 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ 260 261 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 262 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 263 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 264 265 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ 266 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 267 268 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ 269 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 270 BR_V) /* valid */ 271 #define CONFIG_SYS_OR0_PRELIM (0xFF800000 /* 8 MByte */ \ 272 | OR_GPCM_XACS \ 273 | OR_GPCM_SCY_9 \ 274 | OR_GPCM_EHTR \ 275 | OR_GPCM_EAD) 276 /* 0xFF806FF7 TODO SLOW 8 MB flash size */ 277 278 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 279 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 280 281 #undef CONFIG_SYS_FLASH_CHECKSUM 282 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 283 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 284 285 /* 286 * NAND Flash on the Local Bus 287 */ 288 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 289 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | \ 290 (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \ 291 BR_PS_8 | /* Port Size = 8 bit */ \ 292 BR_MS_FCM | /* MSEL = FCM */ \ 293 BR_V) /* valid */ 294 #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | /* length 32K */ \ 295 OR_FCM_CSCT | \ 296 OR_FCM_CST | \ 297 OR_FCM_CHT | \ 298 OR_FCM_SCY_1 | \ 299 OR_FCM_TRLX | \ 300 OR_FCM_EHTR) 301 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 302 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 303 304 /* Vitesse 7385 */ 305 306 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 307 308 #ifdef CONFIG_VSC7385_ENET 309 310 #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* Base address */ 311 #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* 128K bytes*/ 312 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE /* Access Base */ 313 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */ 314 315 #endif 316 317 /* 318 * Serial Port 319 */ 320 #define CONFIG_CONS_INDEX 1 321 #define CONFIG_SYS_NS16550 322 #define CONFIG_SYS_NS16550_SERIAL 323 #define CONFIG_SYS_NS16550_REG_SIZE 1 324 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 325 326 #define CONFIG_SYS_BAUDRATE_TABLE \ 327 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 328 329 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 330 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 331 332 /* SERDES */ 333 #define CONFIG_FSL_SERDES 334 #define CONFIG_FSL_SERDES1 0xe3000 335 #define CONFIG_FSL_SERDES2 0xe3100 336 337 /* Use the HUSH parser */ 338 #define CONFIG_SYS_HUSH_PARSER 339 #ifdef CONFIG_SYS_HUSH_PARSER 340 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 341 #endif 342 343 /* Pass open firmware flat tree */ 344 #define CONFIG_OF_LIBFDT 1 345 #define CONFIG_OF_BOARD_SETUP 1 346 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 347 348 /* I2C */ 349 #define CONFIG_HARD_I2C /* I2C with hardware support */ 350 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 351 #define CONFIG_FSL_I2C 352 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 353 #define CONFIG_SYS_I2C_SLAVE 0x7F 354 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 355 #define CONFIG_SYS_I2C_OFFSET 0x3000 356 #define CONFIG_SYS_I2C2_OFFSET 0x3100 357 358 /* 359 * Config on-board RTC 360 */ 361 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 362 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 363 364 /* 365 * General PCI 366 * Addresses are mapped 1-1. 367 */ 368 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 369 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 370 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 371 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 372 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 373 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 374 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 375 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 376 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 377 378 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 379 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 380 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 381 382 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 383 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 384 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 385 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 386 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 387 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 388 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 389 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 390 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 391 392 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 393 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 394 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 395 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 396 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 397 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 398 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 399 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 400 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 401 402 #ifdef CONFIG_PCI 403 #define CONFIG_NET_MULTI 404 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 405 406 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 407 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 408 #endif /* CONFIG_PCI */ 409 410 /* 411 * TSEC 412 */ 413 #ifdef CONFIG_TSEC_ENET 414 415 #define CONFIG_NET_MULTI 416 #define CONFIG_GMII /* MII PHY management */ 417 418 #define CONFIG_TSEC1 419 420 #ifdef CONFIG_TSEC1 421 #define CONFIG_HAS_ETH0 422 #define CONFIG_TSEC1_NAME "TSEC0" 423 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 424 #define TSEC1_PHY_ADDR 2 425 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 426 #define TSEC1_PHYIDX 0 427 #endif 428 429 #ifdef CONFIG_TSEC2 430 #define CONFIG_HAS_ETH1 431 #define CONFIG_TSEC2_NAME "TSEC1" 432 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 433 #define TSEC2_PHY_ADDR 0x1c 434 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 435 #define TSEC2_PHYIDX 0 436 #endif 437 438 /* Options are: TSEC[0-1] */ 439 #define CONFIG_ETHPRIME "TSEC0" 440 441 #endif 442 443 /* 444 * SATA 445 */ 446 #define CONFIG_LIBATA 447 #define CONFIG_FSL_SATA 448 449 #define CONFIG_SYS_SATA_MAX_DEVICE 2 450 #define CONFIG_SATA1 451 #define CONFIG_SYS_SATA1_OFFSET 0x18000 452 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 453 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 454 #define CONFIG_SATA2 455 #define CONFIG_SYS_SATA2_OFFSET 0x19000 456 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 457 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 458 459 #ifdef CONFIG_FSL_SATA 460 #define CONFIG_LBA48 461 #define CONFIG_CMD_SATA 462 #define CONFIG_DOS_PARTITION 463 #define CONFIG_CMD_EXT2 464 #endif 465 466 /* 467 * Environment 468 */ 469 #ifndef CONFIG_SYS_RAMBOOT 470 #define CONFIG_ENV_IS_IN_FLASH 1 471 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) 472 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ 473 #define CONFIG_ENV_SIZE 0x4000 474 #else 475 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 476 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 477 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) 478 #define CONFIG_ENV_SIZE 0x2000 479 #endif 480 481 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 482 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 483 484 /* 485 * BOOTP options 486 */ 487 #define CONFIG_BOOTP_BOOTFILESIZE 488 #define CONFIG_BOOTP_BOOTPATH 489 #define CONFIG_BOOTP_GATEWAY 490 #define CONFIG_BOOTP_HOSTNAME 491 492 493 /* 494 * Command line configuration. 495 */ 496 #include <config_cmd_default.h> 497 498 #define CONFIG_CMD_PING 499 #define CONFIG_CMD_I2C 500 #define CONFIG_CMD_MII 501 #define CONFIG_CMD_DATE 502 503 #if defined(CONFIG_PCI) 504 #define CONFIG_CMD_PCI 505 #endif 506 507 #if defined(CONFIG_SYS_RAMBOOT) 508 #undef CONFIG_CMD_SAVEENV 509 #undef CONFIG_CMD_LOADS 510 #endif 511 512 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 513 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 514 515 #undef CONFIG_WATCHDOG /* watchdog disabled */ 516 517 #define CONFIG_MMC 1 518 519 #ifdef CONFIG_MMC 520 #define CONFIG_FSL_ESDHC 521 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 522 #define CONFIG_CMD_MMC 523 #define CONFIG_GENERIC_MMC 524 #define CONFIG_CMD_EXT2 525 #define CONFIG_CMD_FAT 526 #define CONFIG_DOS_PARTITION 527 #endif 528 529 /* 530 * Miscellaneous configurable options 531 */ 532 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 533 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 534 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 535 536 #if defined(CONFIG_CMD_KGDB) 537 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 538 #else 539 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 540 #endif 541 542 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 543 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 544 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 545 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 546 547 /* 548 * For booting Linux, the board info and command line data 549 * have to be in the first 256 MB of memory, since this is 550 * the maximum mapped by the Linux kernel during initialization. 551 */ 552 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 553 554 /* 555 * Core HID Setup 556 */ 557 #define CONFIG_SYS_HID0_INIT 0x000000000 558 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 559 HID0_ENABLE_INSTRUCTION_CACHE) 560 #define CONFIG_SYS_HID2 HID2_HBE 561 562 /* 563 * MMU Setup 564 */ 565 566 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 567 568 /* DDR: cache cacheable */ 569 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 570 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 571 572 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) 573 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) 574 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 575 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 576 577 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) 578 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) 579 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 580 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 581 582 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 583 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 584 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 585 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) 586 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 587 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 588 589 /* L2 Switch: cache-inhibit and guarded */ 590 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE | BATL_PP_10 | \ 591 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 592 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP) 593 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 594 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 595 596 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 597 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 598 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 599 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ 600 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 601 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 602 603 /* Stack in dcache: cacheable, no memory coherence */ 604 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) 605 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 606 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 607 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 608 609 #ifdef CONFIG_PCI 610 /* PCI MEM space: cacheable */ 611 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 612 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 613 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 614 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 615 /* PCI MMIO space: cache-inhibit and guarded */ 616 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ 617 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 618 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 619 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 620 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 621 #else 622 #define CONFIG_SYS_IBAT6L (0) 623 #define CONFIG_SYS_IBAT6U (0) 624 #define CONFIG_SYS_IBAT7L (0) 625 #define CONFIG_SYS_IBAT7U (0) 626 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 627 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 628 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 629 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 630 #endif 631 632 /* 633 * Internal Definitions 634 * 635 * Boot Flags 636 */ 637 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 638 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 639 640 #if defined(CONFIG_CMD_KGDB) 641 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 642 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 643 #endif 644 645 /* 646 * Environment Configuration 647 */ 648 #define CONFIG_ENV_OVERWRITE 649 650 #define CONFIG_HAS_FSL_DR_USB 651 652 #define CONFIG_NETDEV eth1 653 654 #define CONFIG_HOSTNAME mpc837x_rdb 655 #define CONFIG_ROOTPATH /nfsroot 656 #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot 657 #define CONFIG_BOOTFILE uImage 658 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 659 #define CONFIG_FDTFILE mpc8379_rdb.dtb 660 661 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 662 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 663 #define CONFIG_BAUDRATE 115200 664 665 #define XMK_STR(x) #x 666 #define MK_STR(x) XMK_STR(x) 667 668 #define CONFIG_EXTRA_ENV_SETTINGS \ 669 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 670 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 671 "tftpflash=tftp $loadaddr $uboot;" \ 672 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 673 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 674 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 675 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 676 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 677 "fdtaddr=780000\0" \ 678 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 679 "ramdiskaddr=1000000\0" \ 680 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ 681 "console=ttyS0\0" \ 682 "setbootargs=setenv bootargs " \ 683 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 684 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 685 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 686 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 687 688 #define CONFIG_NFSBOOTCOMMAND \ 689 "setenv rootdev /dev/nfs;" \ 690 "run setbootargs;" \ 691 "run setipargs;" \ 692 "tftp $loadaddr $bootfile;" \ 693 "tftp $fdtaddr $fdtfile;" \ 694 "bootm $loadaddr - $fdtaddr" 695 696 #define CONFIG_RAMBOOTCOMMAND \ 697 "setenv rootdev /dev/ram;" \ 698 "run setbootargs;" \ 699 "tftp $ramdiskaddr $ramdiskfile;" \ 700 "tftp $loadaddr $bootfile;" \ 701 "tftp $fdtaddr $fdtfile;" \ 702 "bootm $loadaddr $ramdiskaddr $fdtaddr" 703 704 #undef MK_STR 705 #undef XMK_STR 706 707 #endif /* __CONFIG_H */ 708