1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 25 26 Memory map: 27 28 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 29 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 30 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 31 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 32 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 33 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 34 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 35 0xF001_0000-0xF001_FFFF Local bus expansion slot 36 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 37 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 38 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 39 40 I2C address list: 41 Align. Board 42 Bus Addr Part No. Description Length Location 43 ---------------------------------------------------------------- 44 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 45 46 I2C1 0x20 PCF8574 I2C Expander 0 U8 47 I2C1 0x21 PCF8574 I2C Expander 0 U10 48 I2C1 0x38 PCF8574A I2C Expander 0 U8 49 I2C1 0x39 PCF8574A I2C Expander 0 U10 50 I2C1 0x51 (DDR) DDR EEPROM 1 U1 51 I2C1 0x68 DS1339 RTC 1 U68 52 53 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 54 */ 55 56 #ifndef __CONFIG_H 57 #define __CONFIG_H 58 59 #if (TEXT_BASE == 0xFE000000) 60 #define CONFIG_SYS_LOWBOOT 61 #endif 62 63 /* 64 * High Level Configuration Options 65 */ 66 #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ 67 #define CONFIG_MPC8349 /* MPC8349 specific */ 68 69 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 70 71 #define CONFIG_MISC_INIT_F 72 #define CONFIG_MISC_INIT_R 73 74 /* 75 * On-board devices 76 */ 77 78 #ifdef CONFIG_MPC8349ITX 79 #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ 80 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 81 #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 82 #endif 83 84 #define CONFIG_PCI 85 #define CONFIG_RTC_DS1337 86 #define CONFIG_HARD_I2C 87 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 88 89 /* 90 * Device configurations 91 */ 92 93 /* I2C */ 94 #ifdef CONFIG_HARD_I2C 95 96 #define CONFIG_FSL_I2C 97 #define CONFIG_I2C_MULTI_BUS 98 #define CONFIG_I2C_CMD_TREE 99 #define CONFIG_SYS_I2C_OFFSET 0x3000 100 #define CONFIG_SYS_I2C2_OFFSET 0x3100 101 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 102 103 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 104 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 105 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 106 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 107 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 108 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 109 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 110 111 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 112 #define CONFIG_SYS_I2C_SLAVE 0x7F 113 114 /* Don't probe these addresses: */ 115 #define CONFIG_SYS_I2C_NOPROBES {{1, CONFIG_SYS_I2C_8574_ADDR1}, \ 116 {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 117 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 118 {1, CONFIG_SYS_I2C_8574A_ADDR2}} 119 /* Bit definitions for the 8574[A] I2C expander */ 120 #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 121 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 122 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 123 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 124 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 125 126 #undef CONFIG_SOFT_I2C 127 128 #endif 129 130 /* Compact Flash */ 131 #ifdef CONFIG_COMPACT_FLASH 132 133 #define CONFIG_SYS_IDE_MAXBUS 1 134 #define CONFIG_SYS_IDE_MAXDEVICE 1 135 136 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 137 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 138 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 139 #define CONFIG_SYS_ATA_REG_OFFSET 0 140 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 141 #define CONFIG_SYS_ATA_STRIDE 2 142 143 #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ 144 145 #endif 146 147 /* 148 * SATA 149 */ 150 #ifdef CONFIG_SATA_SIL3114 151 152 #define CONFIG_SYS_SATA_MAX_DEVICE 4 153 #define CONFIG_LIBATA 154 #define CONFIG_LBA48 155 156 #endif 157 158 /* 159 * DDR Setup 160 */ 161 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 162 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 163 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 164 #define CONFIG_SYS_83XX_DDR_USES_CS0 165 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 166 #define CONFIG_SYS_MEMTEST_END 0x2000 167 168 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 169 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 170 171 #ifdef CONFIG_HARD_I2C 172 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 173 #endif 174 175 #ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ 176 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 177 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 178 179 #define CONFIG_SYS_DDR_TIMING_1 0x26242321 180 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 181 #endif 182 183 /* 184 *Flash on the Local Bus 185 */ 186 187 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 188 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 189 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 190 #define CONFIG_SYS_FLASH_EMPTY_INFO 191 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ 192 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 193 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 194 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 195 196 /* The ITX has two flash chips, but the ITX-GP has only one. To support both 197 boards, we say we have two, but don't display a message if we find only one. */ 198 #define CONFIG_SYS_FLASH_QUIET_TEST 199 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 200 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 201 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 202 #define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ 203 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 204 205 /* Vitesse 7385 */ 206 207 #ifdef CONFIG_VSC7385_ENET 208 209 #define CONFIG_TSEC2 210 211 /* The flash address and size of the VSC7385 firmware image */ 212 #define CONFIG_VSC7385_IMAGE 0xFEFFE000 213 #define CONFIG_VSC7385_IMAGE_SIZE 8192 214 215 #endif 216 217 /* 218 * BRx, ORx, LBLAWBARx, and LBLAWARx 219 */ 220 221 /* Flash */ 222 223 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) 224 #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 225 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 226 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 227 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 228 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT)) 229 230 /* Vitesse 7385 */ 231 232 #define CONFIG_SYS_VSC7385_BASE 0xF8000000 233 234 #ifdef CONFIG_VSC7385_ENET 235 236 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V) 237 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 238 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ 239 OR_GPCM_EHTR | OR_GPCM_EAD) 240 241 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 242 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 243 244 #endif 245 246 /* LED */ 247 248 #define CONFIG_SYS_LED_BASE 0xF9000000 249 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V) 250 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 251 OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ 252 OR_GPCM_EHTR | OR_GPCM_EAD) 253 254 /* Compact Flash */ 255 256 #ifdef CONFIG_COMPACT_FLASH 257 258 #define CONFIG_SYS_CF_BASE 0xF0000000 259 260 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) 261 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 262 263 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 264 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 265 266 #endif 267 268 /* 269 * U-Boot memory configuration 270 */ 271 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 272 273 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 274 #define CONFIG_SYS_RAMBOOT 275 #else 276 #undef CONFIG_SYS_RAMBOOT 277 #endif 278 279 #define CONFIG_SYS_INIT_RAM_LOCK 280 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 281 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 282 283 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 284 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 285 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 286 287 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 288 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 289 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 290 291 /* 292 * Local Bus LCRR and LBCR regs 293 * LCRR: DLL bypass, Clock divider is 4 294 * External Local Bus rate is 295 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 296 */ 297 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 298 #define CONFIG_SYS_LBC_LBCR 0x00000000 299 300 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 301 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ 302 303 /* 304 * Serial Port 305 */ 306 #define CONFIG_CONS_INDEX 1 307 #undef CONFIG_SERIAL_SOFTWARE_FIFO 308 #define CONFIG_SYS_NS16550 309 #define CONFIG_SYS_NS16550_SERIAL 310 #define CONFIG_SYS_NS16550_REG_SIZE 1 311 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 312 313 #define CONFIG_SYS_BAUDRATE_TABLE \ 314 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 315 316 #define CONFIG_CONSOLE ttyS0 317 #define CONFIG_BAUDRATE 115200 318 319 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 320 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 321 322 /* pass open firmware flat tree */ 323 #define CONFIG_OF_LIBFDT 1 324 #define CONFIG_OF_BOARD_SETUP 1 325 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 326 327 /* 328 * PCI 329 */ 330 #ifdef CONFIG_PCI 331 332 #define CONFIG_MPC83XX_PCI2 333 334 /* 335 * General PCI 336 * Addresses are mapped 1-1. 337 */ 338 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 339 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 340 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 341 #define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 342 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 343 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 344 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 345 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 346 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 347 348 #ifdef CONFIG_MPC83XX_PCI2 349 #define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 350 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 351 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 352 #define CONFIG_SYS_PCI2_MMIO_BASE (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 353 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 354 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 355 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 356 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 357 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 358 #endif 359 360 #define _IO_BASE 0x00000000 /* points to PCI I/O space */ 361 362 #define CONFIG_NET_MULTI 363 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 364 365 #ifdef CONFIG_RTL8139 366 /* This macro is used by RTL8139 but not defined in PPC architecture */ 367 #define KSEG1ADDR(x) (x) 368 #endif 369 370 #ifndef CONFIG_PCI_PNP 371 #define PCI_ENET0_IOADDR 0x00000000 372 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 373 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 374 #endif 375 376 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 377 378 #endif 379 380 #define PCI_66M 381 #ifdef PCI_66M 382 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 383 #else 384 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 385 #endif 386 387 /* TSEC */ 388 389 #ifdef CONFIG_TSEC_ENET 390 391 #define CONFIG_NET_MULTI 392 #define CONFIG_MII 393 #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 394 395 #define CONFIG_TSEC1 396 397 #ifdef CONFIG_TSEC1 398 #define CONFIG_HAS_ETH0 399 #define CONFIG_TSEC1_NAME "TSEC0" 400 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 401 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 402 #define TSEC1_PHYIDX 0 403 #define TSEC1_FLAGS TSEC_GIGABIT 404 #endif 405 406 #ifdef CONFIG_TSEC2 407 #define CONFIG_HAS_ETH1 408 #define CONFIG_TSEC2_NAME "TSEC1" 409 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 410 411 #define TSEC2_PHY_ADDR 4 412 #define TSEC2_PHYIDX 0 413 #define TSEC2_FLAGS TSEC_GIGABIT 414 #endif 415 416 #define CONFIG_ETHPRIME "Freescale TSEC" 417 418 #endif 419 420 /* 421 * Environment 422 */ 423 #define CONFIG_ENV_OVERWRITE 424 425 #ifndef CONFIG_SYS_RAMBOOT 426 #define CONFIG_ENV_IS_IN_FLASH 427 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 428 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 429 #define CONFIG_ENV_SIZE 0x2000 430 #else 431 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 432 #undef CONFIG_FLASH_CFI_DRIVER 433 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 434 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 435 #define CONFIG_ENV_SIZE 0x2000 436 #endif 437 438 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 439 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 440 441 /* 442 * BOOTP options 443 */ 444 #define CONFIG_BOOTP_BOOTFILESIZE 445 #define CONFIG_BOOTP_BOOTPATH 446 #define CONFIG_BOOTP_GATEWAY 447 #define CONFIG_BOOTP_HOSTNAME 448 449 450 /* 451 * Command line configuration. 452 */ 453 #include <config_cmd_default.h> 454 455 #define CONFIG_CMD_CACHE 456 #define CONFIG_CMD_DATE 457 #define CONFIG_CMD_IRQ 458 #define CONFIG_CMD_NET 459 #define CONFIG_CMD_PING 460 #define CONFIG_CMD_SDRAM 461 462 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) 463 #define CONFIG_DOS_PARTITION 464 #define CONFIG_CMD_FAT 465 #endif 466 467 #ifdef CONFIG_COMPACT_FLASH 468 #define CONFIG_CMD_IDE 469 #endif 470 471 #ifdef CONFIG_SATA_SIL3114 472 #define CONFIG_CMD_SATA 473 #define CONFIG_CMD_EXT2 474 #endif 475 476 #ifdef CONFIG_PCI 477 #define CONFIG_CMD_PCI 478 #endif 479 480 #ifdef CONFIG_HARD_I2C 481 #define CONFIG_CMD_I2C 482 #endif 483 484 /* Watchdog */ 485 #undef CONFIG_WATCHDOG /* watchdog disabled */ 486 487 /* 488 * Miscellaneous configurable options 489 */ 490 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 491 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 492 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 493 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 494 495 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 496 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ 497 498 #ifdef CONFIG_MPC8349ITX 499 #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 500 #else 501 #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 502 #endif 503 504 #if defined(CONFIG_CMD_KGDB) 505 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 506 #else 507 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 508 #endif 509 510 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 511 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 512 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 513 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 514 515 /* 516 * For booting Linux, the board info and command line data 517 * have to be in the first 8 MB of memory, since this is 518 * the maximum mapped by the Linux kernel during initialization. 519 */ 520 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 521 522 #define CONFIG_SYS_HRCW_LOW (\ 523 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 524 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 525 HRCWL_CSB_TO_CLKIN_4X1 |\ 526 HRCWL_VCO_1X2 |\ 527 HRCWL_CORE_TO_CSB_2X1) 528 529 #ifdef CONFIG_SYS_LOWBOOT 530 #define CONFIG_SYS_HRCW_HIGH (\ 531 HRCWH_PCI_HOST |\ 532 HRCWH_32_BIT_PCI |\ 533 HRCWH_PCI1_ARBITER_ENABLE |\ 534 HRCWH_PCI2_ARBITER_ENABLE |\ 535 HRCWH_CORE_ENABLE |\ 536 HRCWH_FROM_0X00000100 |\ 537 HRCWH_BOOTSEQ_DISABLE |\ 538 HRCWH_SW_WATCHDOG_DISABLE |\ 539 HRCWH_ROM_LOC_LOCAL_16BIT |\ 540 HRCWH_TSEC1M_IN_GMII |\ 541 HRCWH_TSEC2M_IN_GMII ) 542 #else 543 #define CONFIG_SYS_HRCW_HIGH (\ 544 HRCWH_PCI_HOST |\ 545 HRCWH_32_BIT_PCI |\ 546 HRCWH_PCI1_ARBITER_ENABLE |\ 547 HRCWH_PCI2_ARBITER_ENABLE |\ 548 HRCWH_CORE_ENABLE |\ 549 HRCWH_FROM_0XFFF00100 |\ 550 HRCWH_BOOTSEQ_DISABLE |\ 551 HRCWH_SW_WATCHDOG_DISABLE |\ 552 HRCWH_ROM_LOC_LOCAL_16BIT |\ 553 HRCWH_TSEC1M_IN_GMII |\ 554 HRCWH_TSEC2M_IN_GMII ) 555 #endif 556 557 /* 558 * System performance 559 */ 560 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 561 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 562 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 563 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 564 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 565 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 566 567 /* 568 * System IO Config 569 */ 570 #define CONFIG_SYS_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ 571 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 572 573 #define CONFIG_SYS_HID0_INIT 0x000000000 574 #define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT 575 576 #define CONFIG_SYS_HID2 HID2_HBE 577 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 578 579 /* DDR */ 580 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 581 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 582 583 /* PCI */ 584 #ifdef CONFIG_PCI 585 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 586 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 587 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 588 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 589 #else 590 #define CONFIG_SYS_IBAT1L 0 591 #define CONFIG_SYS_IBAT1U 0 592 #define CONFIG_SYS_IBAT2L 0 593 #define CONFIG_SYS_IBAT2U 0 594 #endif 595 596 #ifdef CONFIG_MPC83XX_PCI2 597 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 598 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 599 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 600 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 601 #else 602 #define CONFIG_SYS_IBAT3L 0 603 #define CONFIG_SYS_IBAT3U 0 604 #define CONFIG_SYS_IBAT4L 0 605 #define CONFIG_SYS_IBAT4U 0 606 #endif 607 608 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 609 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 610 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 611 612 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 613 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 614 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 615 616 #define CONFIG_SYS_IBAT7L 0 617 #define CONFIG_SYS_IBAT7U 0 618 619 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 620 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 621 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 622 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 623 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 624 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 625 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 626 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 627 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 628 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 629 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 630 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 631 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 632 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 633 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 634 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 635 636 /* 637 * Internal Definitions 638 * 639 * Boot Flags 640 */ 641 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 642 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 643 644 #if defined(CONFIG_CMD_KGDB) 645 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 646 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 647 #endif 648 649 650 /* 651 * Environment Configuration 652 */ 653 #define CONFIG_ENV_OVERWRITE 654 655 #ifdef CONFIG_HAS_ETH0 656 #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 657 #endif 658 659 #ifdef CONFIG_HAS_ETH1 660 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 661 #endif 662 663 #define CONFIG_IPADDR 192.168.1.253 664 #define CONFIG_SERVERIP 192.168.1.1 665 #define CONFIG_GATEWAYIP 192.168.1.1 666 #define CONFIG_NETMASK 255.255.252.0 667 #define CONFIG_NETDEV eth0 668 669 #ifdef CONFIG_MPC8349ITX 670 #define CONFIG_HOSTNAME mpc8349emitx 671 #else 672 #define CONFIG_HOSTNAME mpc8349emitxgp 673 #endif 674 675 /* Default path and filenames */ 676 #define CONFIG_ROOTPATH /nfsroot/rootfs 677 #define CONFIG_BOOTFILE uImage 678 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 679 680 #ifdef CONFIG_MPC8349ITX 681 #define CONFIG_FDTFILE mpc8349emitx.dtb 682 #else 683 #define CONFIG_FDTFILE mpc8349emitxgp.dtb 684 #endif 685 686 #define CONFIG_BOOTDELAY 0 687 688 #define XMK_STR(x) #x 689 #define MK_STR(x) XMK_STR(x) 690 691 #define CONFIG_BOOTARGS \ 692 "root=/dev/nfs rw" \ 693 " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ 694 " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ 695 MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ 696 MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ 697 " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) 698 699 #define CONFIG_EXTRA_ENV_SETTINGS \ 700 "console=" MK_STR(CONFIG_CONSOLE) "\0" \ 701 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 702 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 703 "tftpflash=tftpboot $loadaddr $uboot; " \ 704 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 705 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 706 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 707 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 708 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 709 "fdtaddr=400000\0" \ 710 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" 711 712 #define CONFIG_NFSBOOTCOMMAND \ 713 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 714 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 715 " console=$console,$baudrate $othbootargs; " \ 716 "tftp $loadaddr $bootfile;" \ 717 "tftp $fdtaddr $fdtfile;" \ 718 "bootm $loadaddr - $fdtaddr" 719 720 #define CONFIG_RAMBOOTCOMMAND \ 721 "setenv bootargs root=/dev/ram rw" \ 722 " console=$console,$baudrate $othbootargs; " \ 723 "tftp $ramdiskaddr $ramdiskfile;" \ 724 "tftp $loadaddr $bootfile;" \ 725 "tftp $fdtaddr $fdtfile;" \ 726 "bootm $loadaddr $ramdiskaddr $fdtaddr" 727 728 #undef MK_STR 729 #undef XMK_STR 730 731 #endif 732