1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 MPC8349E-mITX board configuration file 25 26 Memory map: 27 28 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 29 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 30 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 31 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 32 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 33 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 34 0xF000_0000-0xF000_FFFF Compact Flash 35 0xF001_0000-0xF001_FFFF Local bus expansion slot 36 0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385 37 0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB) 38 0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB) 39 40 I2C address list: 41 Align. Board 42 Bus Addr Part No. Description Length Location 43 ---------------------------------------------------------------- 44 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 45 46 I2C1 0x20 PCF8574 I2C Expander 0 U8 47 I2C1 0x21 PCF8574 I2C Expander 0 U10 48 I2C1 0x38 PCF8574A I2C Expander 0 U8 49 I2C1 0x39 PCF8574A I2C Expander 0 U10 50 I2C1 0x51 (DDR) DDR EEPROM 1 U1 51 I2C1 0x68 DS1339 RTC 1 U68 52 53 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 54 */ 55 56 #ifndef __CONFIG_H 57 #define __CONFIG_H 58 59 #undef DEBUG 60 61 /* 62 * High Level Configuration Options 63 */ 64 #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ 65 #define CONFIG_MPC8349 /* MPC8349 specific */ 66 67 #define CONFIG_PCI 68 69 #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ 70 #define CONFIG_RTC_DS1337 71 72 /* I2C */ 73 #define CONFIG_HARD_I2C 74 75 #ifdef CONFIG_HARD_I2C 76 77 #define CONFIG_MISC_INIT_F 78 #define CONFIG_MISC_INIT_R 79 80 #define CONFIG_FSL_I2C 81 #define CONFIG_I2C_MULTI_BUS 82 #define CONFIG_I2C_CMD_TREE 83 #define CFG_I2C_OFFSET 0x3000 84 #define CFG_I2C2_OFFSET 0x3100 85 #define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 86 87 #define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 88 #define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 89 #define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 90 #define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 91 #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 92 #define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 93 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 94 95 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 96 #define CFG_I2C_SLAVE 0x7F 97 98 /* Don't probe these addresses: */ 99 #define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ 100 {1, CFG_I2C_8574_ADDR2}, \ 101 {1, CFG_I2C_8574A_ADDR1}, \ 102 {1, CFG_I2C_8574A_ADDR2}} 103 /* Bit definitions for the 8574[A] I2C expander */ 104 #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 105 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 106 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 107 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 108 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 109 110 #undef CONFIG_SOFT_I2C 111 112 #endif 113 114 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 115 #define CONFIG_ENV_OVERWRITE 116 117 #define PCI_66M 118 #ifdef PCI_66M 119 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 120 #else 121 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 122 #endif 123 124 #ifndef CONFIG_SYS_CLK_FREQ 125 #ifdef PCI_66M 126 #define CONFIG_SYS_CLK_FREQ 66666666 127 #else 128 #define CONFIG_SYS_CLK_FREQ 33333333 129 #endif 130 #endif 131 132 #define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ 133 134 #undef CFG_DRAM_TEST /* memory test, takes time */ 135 #define CFG_MEMTEST_START 0x00003000 /* memtest region */ 136 #define CFG_MEMTEST_END 0x07100000 /* only has 128M */ 137 138 /* 139 * DDR Setup 140 */ 141 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 142 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 143 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 144 145 /* 146 * 32-bit data path mode. 147 * 148 * Please note that using this mode for devices with the real density of 64-bit 149 * effectively reduces the amount of available memory due to the effect of 150 * wrapping around while translating address to row/columns, for example in the 151 * 256MB module the upper 128MB get aliased with contents of the lower 152 * 128MB); normally this define should be used for devices with real 32-bit 153 * data path. 154 */ 155 #undef CONFIG_DDR_32BIT 156 157 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 158 #define CFG_SDRAM_BASE CFG_DDR_BASE 159 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 160 #undef CONFIG_DDR_2T_TIMING 161 #define CFG_83XX_DDR_USES_CS0 162 163 #ifndef CONFIG_SPD_EEPROM 164 /* 165 * Manually set up DDR parameters 166 */ 167 #define CFG_DDR_SIZE 256 /* Mb */ 168 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 169 170 #define CFG_DDR_TIMING_1 0x26242321 171 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 172 #endif 173 174 /* FLASH on the Local Bus */ 175 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 176 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 177 #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 178 #define CFG_FLASH_SIZE 16 /* FLASH size in MB */ 179 #define CFG_FLASH_EMPTY_INFO 180 181 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) 182 #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 183 OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 184 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 185 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 186 #define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */ 187 188 /* VSC7385 on the Local Bus */ 189 #define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */ 190 191 #define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) 192 #define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \ 193 OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 194 OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 195 196 #define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */ 197 #define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */ 198 199 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 200 #define CFG_MAX_FLASH_SECT 135 /* sectors per device */ 201 202 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} 203 204 #undef CFG_FLASH_CHECKSUM 205 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 206 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 207 208 #define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */ 209 #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) 210 #define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \ 211 OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \ 212 OR_GPCM_SCY_9 | \ 213 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 214 215 #ifdef CONFIG_COMPACT_FLASH 216 217 #define CFG_CF_BASE 0xF0000000 218 219 #define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) 220 #define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 221 222 #define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */ 223 #define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ 224 225 #undef CONFIG_IDE_RESET 226 #undef CONFIG_IDE_PREINIT 227 228 #define CFG_IDE_MAXBUS 1 229 #define CFG_IDE_MAXDEVICE 1 230 231 #define CFG_ATA_IDE0_OFFSET 0x0000 232 #define CFG_ATA_BASE_ADDR CFG_CF_BASE 233 #define CFG_ATA_DATA_OFFSET 0x0000 234 #define CFG_ATA_REG_OFFSET 0 235 #define CFG_ATA_ALT_OFFSET 0x0200 236 #define CFG_ATA_STRIDE 2 237 238 #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ 239 240 #endif 241 242 #define CONFIG_DOS_PARTITION 243 244 #define CFG_MID_FLASH_JUMP 0x7F000000 245 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 246 247 248 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 249 #define CFG_RAMBOOT 250 #else 251 #undef CFG_RAMBOOT 252 #endif 253 254 #define CONFIG_L1_INIT_RAM 255 #define CFG_INIT_RAM_LOCK 256 #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 257 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 258 259 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 260 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 261 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 262 263 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 264 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 265 266 /* 267 * Local Bus LCRR and LBCR regs 268 * LCRR: DLL bypass, Clock divider is 4 269 * External Local Bus rate is 270 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 271 */ 272 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 273 #define CFG_LBC_LBCR 0x00000000 274 275 #undef CFG_LB_SDRAM /* if board has SRDAM on local bus */ 276 277 #ifdef CFG_LB_SDRAM 278 /*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ 279 /* 280 * Base Register 2 and Option Register 2 configure SDRAM. 281 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 282 * 283 * For BR2, need: 284 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 285 * port-size = 32-bits = BR2[19:20] = 11 286 * no parity checking = BR2[21:22] = 00 287 * SDRAM for MSEL = BR2[24:26] = 011 288 * Valid = BR[31] = 1 289 * 290 * 0 4 8 12 16 20 24 28 291 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 292 */ 293 294 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 295 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 296 297 #define CFG_LBLAWBAR2_PRELIM 0xF0000000 298 #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 299 300 #define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V) 301 #define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \ 302 OR_SDRAM_XAM | \ 303 ((9 - 7) << OR_SDRAM_COLS_SHIFT) | \ 304 ((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \ 305 OR_SDRAM_EAD) 306 307 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 308 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ 309 310 /* 311 * LSDMR masks 312 */ 313 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 314 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 315 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 316 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 317 #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) 318 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 319 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 320 #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) 321 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 322 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 323 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 324 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 325 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 326 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 327 #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) 328 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 329 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 330 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 331 332 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 333 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 334 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 335 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 336 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 337 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 338 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 339 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 340 341 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ 342 | CFG_LBC_LSDMR_BSMA1516 \ 343 | CFG_LBC_LSDMR_RFCR8 \ 344 | CFG_LBC_LSDMR_PRETOACT6 \ 345 | CFG_LBC_LSDMR_ACTTORW3 \ 346 | CFG_LBC_LSDMR_BL8 \ 347 | CFG_LBC_LSDMR_WRC3 \ 348 | CFG_LBC_LSDMR_CL3 \ 349 ) 350 351 /* 352 * SDRAM Controller configuration sequence. 353 */ 354 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 355 | CFG_LBC_LSDMR_OP_PCHALL) 356 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 357 | CFG_LBC_LSDMR_OP_ARFRSH) 358 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 359 | CFG_LBC_LSDMR_OP_ARFRSH) 360 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 361 | CFG_LBC_LSDMR_OP_MRW) 362 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 363 | CFG_LBC_LSDMR_OP_NORMAL) 364 #endif 365 366 /* 367 * Serial Port 368 */ 369 #define CONFIG_CONS_INDEX 1 370 #undef CONFIG_SERIAL_SOFTWARE_FIFO 371 #define CFG_NS16550 372 #define CFG_NS16550_SERIAL 373 #define CFG_NS16550_REG_SIZE 1 374 #define CFG_NS16550_CLK get_bus_freq(0) 375 376 #define CFG_BAUDRATE_TABLE \ 377 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 378 379 #define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) 380 #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) 381 382 /* Use the HUSH parser */ 383 #define CFG_HUSH_PARSER 384 #ifdef CFG_HUSH_PARSER 385 #define CFG_PROMPT_HUSH_PS2 "> " 386 #endif 387 388 /* pass open firmware flat tree */ 389 #define CONFIG_OF_FLAT_TREE 1 390 #define CONFIG_OF_BOARD_SETUP 1 391 392 /* maximum size of the flat tree (8K) */ 393 #define OF_FLAT_TREE_MAX_SIZE 8192 394 395 #define OF_CPU "PowerPC,8349@0" 396 #define OF_SOC "soc8349@e0000000" 397 #define OF_TBCLK (bd->bi_busfreq / 4) 398 #define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" 399 400 #ifdef CONFIG_PCI 401 402 #define CONFIG_MPC83XX_PCI2 403 404 /* 405 * General PCI 406 * Addresses are mapped 1-1. 407 */ 408 #define CFG_PCI1_MEM_BASE 0x80000000 409 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 410 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 411 #define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) 412 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 413 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 414 #define CFG_PCI1_IO_BASE 0x00000000 415 #define CFG_PCI1_IO_PHYS 0xE2000000 416 #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ 417 418 #ifdef CONFIG_MPC83XX_PCI2 419 #define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE) 420 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 421 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 422 #define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE) 423 #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE 424 #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 425 #define CFG_PCI2_IO_BASE 0x00000000 426 #define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE) 427 #define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ 428 #endif 429 430 #define _IO_BASE 0x00000000 /* points to PCI I/O space */ 431 432 #define CONFIG_NET_MULTI 433 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 434 435 #ifdef CONFIG_RTL8139 436 /* This macro is used by RTL8139 but not defined in PPC architecture */ 437 #define KSEG1ADDR(x) (x) 438 #endif 439 440 #ifndef CONFIG_PCI_PNP 441 #define PCI_ENET0_IOADDR 0x00000000 442 #define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE 443 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 444 #endif 445 446 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 447 448 #endif 449 450 /* TSEC */ 451 452 #ifdef CONFIG_TSEC_ENET 453 454 #ifndef CONFIG_NET_MULTI 455 #define CONFIG_NET_MULTI 456 #endif 457 458 #define CONFIG_MII 459 #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ 460 461 #define CONFIG_MPC83XX_TSEC1 462 463 #ifdef CONFIG_MPC83XX_TSEC1 464 #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" 465 #define CFG_TSEC1_OFFSET 0x24000 466 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 467 #define TSEC1_PHYIDX 0 468 #endif 469 470 #ifdef CONFIG_MPC83XX_TSEC2 471 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" 472 #define CFG_TSEC2_OFFSET 0x25000 473 #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ 474 #define TSEC2_PHY_ADDR 4 475 #define TSEC2_PHYIDX 0 476 #endif 477 478 #define CONFIG_ETHPRIME "Freescale TSEC" 479 480 #endif 481 482 483 /* 484 * Environment 485 */ 486 #ifndef CFG_RAMBOOT 487 #define CFG_ENV_IS_IN_FLASH 488 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 489 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 490 #define CFG_ENV_SIZE 0x2000 491 #else 492 #define CFG_NO_FLASH /* Flash is not usable now */ 493 #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ 494 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 495 #define CFG_ENV_SIZE 0x2000 496 #endif 497 498 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 499 #define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ 500 501 /* CONFIG_COMMANDS */ 502 503 #ifdef CONFIG_COMPACT_FLASH 504 #define CONFIG_COMMANDS_CF (CFG_CMD_IDE | CFG_CMD_FAT) 505 #else 506 #define CONFIG_COMMANDS_CF 0 507 #endif 508 509 #ifdef CONFIG_PCI 510 #define CONFIG_COMMANDS_PCI CFG_CMD_PCI 511 #else 512 #define CONFIG_COMMANDS_PCI 0 513 #endif 514 515 #ifdef CONFIG_HARD_I2C 516 #define CONFIG_COMMANDS_I2C CFG_CMD_I2C 517 #else 518 #define CONFIG_COMMANDS_I2C 0 519 #endif 520 521 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ 522 CONFIG_COMMANDS_CF | \ 523 CFG_CMD_NET | \ 524 CFG_CMD_PING | \ 525 CONFIG_COMMANDS_I2C | \ 526 CONFIG_COMMANDS_PCI | \ 527 CFG_CMD_SDRAM | \ 528 CFG_CMD_DATE | \ 529 CFG_CMD_CACHE | \ 530 CFG_CMD_IRQ) 531 #include <cmd_confdefs.h> 532 533 /* Watchdog */ 534 535 #undef CONFIG_WATCHDOG /* watchdog disabled */ 536 #ifdef CONFIG_WATCHDOG 537 #define CFG_WATCHDOG_VALUE 0xFFFFFFC3 538 #endif 539 540 /* 541 * Miscellaneous configurable options 542 */ 543 #define CFG_LONGHELP /* undef to save memory */ 544 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 545 #define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 546 547 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 548 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 549 #else 550 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 551 #endif 552 553 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ 554 #define CFG_MAXARGS 16 /* max number of command args */ 555 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 556 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 557 558 /* 559 * For booting Linux, the board info and command line data 560 * have to be in the first 8 MB of memory, since this is 561 * the maximum mapped by the Linux kernel during initialization. 562 */ 563 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 564 565 /* Cache Configuration */ 566 #define CFG_DCACHE_SIZE 32768 567 #define CFG_CACHELINE_SIZE 32 568 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 569 #define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ 570 #endif 571 572 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 573 574 #define CFG_HRCW_LOW (\ 575 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 576 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 577 HRCWL_CSB_TO_CLKIN_4X1 |\ 578 HRCWL_VCO_1X2 |\ 579 HRCWL_CORE_TO_CSB_2X1) 580 581 #ifdef PCI_64BIT 582 #define CFG_HRCW_HIGH (\ 583 HRCWH_PCI_HOST |\ 584 HRCWH_64_BIT_PCI |\ 585 HRCWH_PCI1_ARBITER_ENABLE |\ 586 HRCWH_PCI2_ARBITER_DISABLE |\ 587 HRCWH_CORE_ENABLE |\ 588 HRCWH_FROM_0X00000100 |\ 589 HRCWH_BOOTSEQ_DISABLE |\ 590 HRCWH_SW_WATCHDOG_DISABLE |\ 591 HRCWH_ROM_LOC_LOCAL_16BIT |\ 592 HRCWH_TSEC1M_IN_GMII |\ 593 HRCWH_TSEC2M_IN_GMII ) 594 #else 595 #define CFG_HRCW_HIGH (\ 596 HRCWH_PCI_HOST |\ 597 HRCWH_32_BIT_PCI |\ 598 HRCWH_PCI1_ARBITER_ENABLE |\ 599 HRCWH_PCI2_ARBITER_DISABLE |\ 600 HRCWH_CORE_ENABLE |\ 601 HRCWH_FROM_0XFFF00100 |\ 602 HRCWH_BOOTSEQ_DISABLE |\ 603 HRCWH_SW_WATCHDOG_DISABLE |\ 604 HRCWH_ROM_LOC_LOCAL_16BIT |\ 605 HRCWH_TSEC1M_IN_GMII |\ 606 HRCWH_TSEC2M_IN_GMII ) 607 #endif 608 609 /* System performance */ 610 #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 611 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 612 #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 613 #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 614 #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 615 #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 616 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */ 617 618 /* System IO Config */ 619 #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ 620 #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) 621 622 #define CFG_HID0_INIT 0x000000000 623 624 #define CFG_HID0_FINAL CFG_HID0_INIT 625 626 #define CFG_HID2 HID2_HBE 627 628 /* DDR @ 0x00000000 */ 629 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 630 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 631 632 /* PCI @ 0x80000000 */ 633 #ifdef CONFIG_PCI 634 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 635 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 636 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 637 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 638 #else 639 #define CFG_IBAT1L 0 640 #define CFG_IBAT1U 0 641 #define CFG_IBAT2L 0 642 #define CFG_IBAT2U 0 643 #endif 644 645 #ifdef CONFIG_MPC83XX_PCI2 646 #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 647 #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 648 #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 649 #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 650 #else 651 #define CFG_IBAT3L 0 652 #define CFG_IBAT3U 0 653 #define CFG_IBAT4L 0 654 #define CFG_IBAT4U 0 655 #endif 656 657 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 658 #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 659 #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 660 661 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 662 #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 663 #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 664 665 #define CFG_IBAT7L 0 666 #define CFG_IBAT7U 0 667 668 #define CFG_DBAT0L CFG_IBAT0L 669 #define CFG_DBAT0U CFG_IBAT0U 670 #define CFG_DBAT1L CFG_IBAT1L 671 #define CFG_DBAT1U CFG_IBAT1U 672 #define CFG_DBAT2L CFG_IBAT2L 673 #define CFG_DBAT2U CFG_IBAT2U 674 #define CFG_DBAT3L CFG_IBAT3L 675 #define CFG_DBAT3U CFG_IBAT3U 676 #define CFG_DBAT4L CFG_IBAT4L 677 #define CFG_DBAT4U CFG_IBAT4U 678 #define CFG_DBAT5L CFG_IBAT5L 679 #define CFG_DBAT5U CFG_IBAT5U 680 #define CFG_DBAT6L CFG_IBAT6L 681 #define CFG_DBAT6U CFG_IBAT6U 682 #define CFG_DBAT7L CFG_IBAT7L 683 #define CFG_DBAT7U CFG_IBAT7U 684 685 /* 686 * Internal Definitions 687 * 688 * Boot Flags 689 */ 690 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 691 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 692 693 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 694 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 695 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 696 #endif 697 698 699 /* 700 * Environment Configuration 701 */ 702 #define CONFIG_ENV_OVERWRITE 703 704 #ifdef CONFIG_MPC83XX_TSEC1 705 #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 706 #endif 707 708 #ifdef CONFIG_MPC83XX_TSEC2 709 #define CONFIG_HAS_ETH1 710 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 711 #endif 712 713 #if 1 714 #define CONFIG_IPADDR 10.82.19.159 715 #define CONFIG_SERVERIP 10.82.48.106 716 #define CONFIG_GATEWAYIP 10.82.19.254 717 #define CONFIG_NETMASK 255.255.252.0 718 #define CONFIG_NETDEV eth0 719 720 #define CONFIG_HOSTNAME mpc8349emitx 721 #define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs 722 #define CONFIG_BOOTFILE timur/uImage 723 724 #define CONFIG_UBOOTPATH timur/u-boot.bin 725 #else 726 #define CONFIG_IPADDR 192.168.1.253 727 #define CONFIG_SERVERIP 192.168.1.1 728 #define CONFIG_GATEWAYIP 192.168.1.1 729 #define CONFIG_NETMASK 255.255.252.0 730 #define CONFIG_NETDEV eth0 731 732 #define CONFIG_HOSTNAME mpc8349emitx 733 #define CONFIG_ROOTPATH /nfsroot/rootfs 734 #define CONFIG_BOOTFILE uImage 735 736 #define CONFIG_UBOOTPATH u-boot.bin 737 #endif 738 739 #define CONFIG_UBOOTSTART fe700000 740 #define CONFIG_UBOOTEND fe77ffff 741 742 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 743 744 #define CONFIG_BAUDRATE 115200 745 746 #undef CONFIG_BOOTCOMMAND 747 #ifdef CONFIG_BOOTCOMMAND 748 #define CONFIG_BOOTDELAY 6 749 #else 750 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 751 #endif 752 753 #define XMK_STR(x) #x 754 #define MK_STR(x) XMK_STR(x) 755 756 #define CONFIG_BOOTARGS \ 757 "root=/dev/nfs rw" \ 758 " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ 759 " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ 760 MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ 761 MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ 762 " console=ttyS0," MK_STR(CONFIG_BAUDRATE) 763 764 #define CONFIG_EXTRA_ENV_SETTINGS \ 765 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 766 "tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ 767 "erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ 768 "cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \ 769 "cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \ 770 "tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ 771 "protect off FEF00000 FEF7FFFF; " \ 772 "erase FEF00000 FEF7FFFF; " \ 773 "cp.b $loadaddr FEF00000 $filesize; " \ 774 "protect on FEF00000 FEF7FFFF; " \ 775 "cmp.b $loadaddr FEF00000 $filesize\0" \ 776 "tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \ 777 "copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ 778 "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" \ 779 "fdtaddr=400000\0" \ 780 "fdtfile=mpc8349emitx.dtb\0" \ 781 "" 782 783 #define CONFIG_NFSBOOTCOMMAND \ 784 "setenv bootargs root=/dev/nfs rw " \ 785 "nfsroot=$serverip:$rootpath " \ 786 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 787 "console=$consoledev,$baudrate $othbootargs;" \ 788 "tftp $loadaddr $bootfile;" \ 789 "tftp $fdtaddr $fdtfile;" \ 790 "bootm $loadaddr - $fdtaddr" 791 792 #define CONFIG_RAMBOOTCOMMAND \ 793 "setenv bootargs root=/dev/ram rw " \ 794 "console=$consoledev,$baudrate $othbootargs;" \ 795 "tftp $ramdiskaddr $ramdiskfile;" \ 796 "tftp $loadaddr $bootfile;" \ 797 "tftp $fdtaddr $fdtfile;" \ 798 "bootm $loadaddr $ramdiskaddr $fdtaddr" 799 800 801 #undef MK_STR 802 #undef XMK_STR 803 804 #endif 805