1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 25 26 Memory map: 27 28 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 29 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 30 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 31 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 32 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 33 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 34 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 35 0xF001_0000-0xF001_FFFF Local bus expansion slot 36 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 37 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 38 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 39 40 I2C address list: 41 Align. Board 42 Bus Addr Part No. Description Length Location 43 ---------------------------------------------------------------- 44 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 45 46 I2C1 0x20 PCF8574 I2C Expander 0 U8 47 I2C1 0x21 PCF8574 I2C Expander 0 U10 48 I2C1 0x38 PCF8574A I2C Expander 0 U8 49 I2C1 0x39 PCF8574A I2C Expander 0 U10 50 I2C1 0x51 (DDR) DDR EEPROM 1 U1 51 I2C1 0x68 DS1339 RTC 1 U68 52 53 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 54 */ 55 56 #ifndef __CONFIG_H 57 #define __CONFIG_H 58 59 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 60 #define CONFIG_SYS_LOWBOOT 61 #endif 62 63 /* 64 * High Level Configuration Options 65 */ 66 #define CONFIG_MPC83xx 1 67 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 68 #define CONFIG_MPC8349 /* MPC8349 specific */ 69 70 #ifndef CONFIG_SYS_TEXT_BASE 71 #define CONFIG_SYS_TEXT_BASE 0xFEF00000 72 #endif 73 74 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 75 76 #define CONFIG_MISC_INIT_F 77 #define CONFIG_MISC_INIT_R 78 79 /* 80 * On-board devices 81 */ 82 83 #ifdef CONFIG_MPC8349ITX 84 /* The CF card interface on the back of the board */ 85 #define CONFIG_COMPACT_FLASH 86 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 87 #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 88 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 89 #endif 90 91 #define CONFIG_PCI 92 #define CONFIG_RTC_DS1337 93 #define CONFIG_HARD_I2C 94 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 95 96 /* 97 * Device configurations 98 */ 99 100 /* I2C */ 101 #ifdef CONFIG_HARD_I2C 102 103 #define CONFIG_FSL_I2C 104 #define CONFIG_I2C_MULTI_BUS 105 #define CONFIG_SYS_I2C_OFFSET 0x3000 106 #define CONFIG_SYS_I2C2_OFFSET 0x3100 107 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 108 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 109 110 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 111 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 112 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 113 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 114 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 115 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 116 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 117 118 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 119 #define CONFIG_SYS_I2C_SLAVE 0x7F 120 121 /* Don't probe these addresses: */ 122 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 123 {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 124 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 125 {1, CONFIG_SYS_I2C_8574A_ADDR2} } 126 /* Bit definitions for the 8574[A] I2C expander */ 127 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 128 #define I2C_8574_REVISION 0x03 129 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 130 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 131 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 132 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 133 134 #undef CONFIG_SOFT_I2C 135 136 #endif 137 138 /* Compact Flash */ 139 #ifdef CONFIG_COMPACT_FLASH 140 141 #define CONFIG_SYS_IDE_MAXBUS 1 142 #define CONFIG_SYS_IDE_MAXDEVICE 1 143 144 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 145 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 146 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 147 #define CONFIG_SYS_ATA_REG_OFFSET 0 148 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 149 #define CONFIG_SYS_ATA_STRIDE 2 150 151 /* If a CF card is not inserted, time out quickly */ 152 #define ATA_RESET_TIME 1 153 154 #endif 155 156 /* 157 * SATA 158 */ 159 #ifdef CONFIG_SATA_SIL3114 160 161 #define CONFIG_SYS_SATA_MAX_DEVICE 4 162 #define CONFIG_LIBATA 163 #define CONFIG_LBA48 164 165 #endif 166 167 #ifdef CONFIG_SYS_USB_HOST 168 /* 169 * Support USB 170 */ 171 #define CONFIG_CMD_USB 172 #define CONFIG_USB_STORAGE 173 #define CONFIG_USB_EHCI 174 #define CONFIG_USB_EHCI_FSL 175 176 /* Current USB implementation supports the only USB controller, 177 * so we have to choose between the MPH or the DR ones */ 178 #if 1 179 #define CONFIG_HAS_FSL_MPH_USB 180 #else 181 #define CONFIG_HAS_FSL_DR_USB 182 #endif 183 184 #endif 185 186 /* 187 * DDR Setup 188 */ 189 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 190 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 191 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 192 #define CONFIG_SYS_83XX_DDR_USES_CS0 193 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 194 #define CONFIG_SYS_MEMTEST_END 0x2000 195 196 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 197 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 198 199 #define CONFIG_VERY_BIG_RAM 200 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 201 202 #ifdef CONFIG_HARD_I2C 203 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 204 #endif 205 206 /* No SPD? Then manually set up DDR parameters */ 207 #ifndef CONFIG_SPD_EEPROM 208 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 209 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \ 210 | CSCONFIG_ROW_BIT_13 \ 211 | CSCONFIG_COL_BIT_10) 212 213 #define CONFIG_SYS_DDR_TIMING_1 0x26242321 214 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 215 #endif 216 217 /* 218 *Flash on the Local Bus 219 */ 220 221 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 222 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 223 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 224 #define CONFIG_SYS_FLASH_EMPTY_INFO 225 /* 127 64KB sectors + 8 8KB sectors per device */ 226 #define CONFIG_SYS_MAX_FLASH_SECT 135 227 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 228 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 229 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 230 231 /* The ITX has two flash chips, but the ITX-GP has only one. To support both 232 boards, we say we have two, but don't display a message if we find only one. */ 233 #define CONFIG_SYS_FLASH_QUIET_TEST 234 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 235 #define CONFIG_SYS_FLASH_BANKS_LIST \ 236 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 237 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 238 #define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ 239 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 240 241 /* Vitesse 7385 */ 242 243 #ifdef CONFIG_VSC7385_ENET 244 245 #define CONFIG_TSEC2 246 247 /* The flash address and size of the VSC7385 firmware image */ 248 #define CONFIG_VSC7385_IMAGE 0xFEFFE000 249 #define CONFIG_VSC7385_IMAGE_SIZE 8192 250 251 #endif 252 253 /* 254 * BRx, ORx, LBLAWBARx, and LBLAWARx 255 */ 256 257 /* Flash */ 258 259 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) 260 #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ 261 | OR_UPM_XAM \ 262 | OR_GPCM_CSNT \ 263 | OR_GPCM_ACS_DIV2 \ 264 | OR_GPCM_XACS \ 265 | OR_GPCM_SCY_15 \ 266 | OR_GPCM_TRLX \ 267 | OR_GPCM_EHTR \ 268 | OR_GPCM_EAD) 269 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 270 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \ 271 | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT)) 272 273 /* Vitesse 7385 */ 274 275 #define CONFIG_SYS_VSC7385_BASE 0xF8000000 276 277 #ifdef CONFIG_VSC7385_ENET 278 279 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V) 280 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 281 | OR_GPCM_CSNT \ 282 | OR_GPCM_XACS \ 283 | OR_GPCM_SCY_15 \ 284 | OR_GPCM_SETA \ 285 | OR_GPCM_TRLX \ 286 | OR_GPCM_EHTR \ 287 | OR_GPCM_EAD) 288 289 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 290 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 291 292 #endif 293 294 /* LED */ 295 296 #define CONFIG_SYS_LED_BASE 0xF9000000 297 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V) 298 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 299 | OR_GPCM_CSNT \ 300 | OR_GPCM_ACS_DIV2 \ 301 | OR_GPCM_XACS \ 302 | OR_GPCM_SCY_9 \ 303 | OR_GPCM_TRLX \ 304 | OR_GPCM_EHTR \ 305 | OR_GPCM_EAD) 306 307 /* Compact Flash */ 308 309 #ifdef CONFIG_COMPACT_FLASH 310 311 #define CONFIG_SYS_CF_BASE 0xF0000000 312 313 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 314 | BR_PS_16 \ 315 | BR_MS_UPMA \ 316 | BR_V) 317 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 318 319 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 320 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 321 322 #endif 323 324 /* 325 * U-Boot memory configuration 326 */ 327 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 328 329 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 330 #define CONFIG_SYS_RAMBOOT 331 #else 332 #undef CONFIG_SYS_RAMBOOT 333 #endif 334 335 #define CONFIG_SYS_INIT_RAM_LOCK 336 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 337 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 338 339 #define CONFIG_SYS_GBL_DATA_OFFSET \ 340 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 341 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 342 343 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 344 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 345 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 346 347 /* 348 * Local Bus LCRR and LBCR regs 349 * LCRR: DLL bypass, Clock divider is 4 350 * External Local Bus rate is 351 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 352 */ 353 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 354 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 355 #define CONFIG_SYS_LBC_LBCR 0x00000000 356 357 /* LB sdram refresh timer, about 6us */ 358 #define CONFIG_SYS_LBC_LSRT 0x32000000 359 /* LB refresh timer prescal, 266MHz/32*/ 360 #define CONFIG_SYS_LBC_MRTPR 0x20000000 361 362 /* 363 * Serial Port 364 */ 365 #define CONFIG_CONS_INDEX 1 366 #define CONFIG_SYS_NS16550 367 #define CONFIG_SYS_NS16550_SERIAL 368 #define CONFIG_SYS_NS16550_REG_SIZE 1 369 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 370 371 #define CONFIG_SYS_BAUDRATE_TABLE \ 372 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 373 374 #define CONFIG_CONSOLE ttyS0 375 #define CONFIG_BAUDRATE 115200 376 377 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 378 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 379 380 /* pass open firmware flat tree */ 381 #define CONFIG_OF_LIBFDT 1 382 #define CONFIG_OF_BOARD_SETUP 1 383 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 384 385 /* 386 * PCI 387 */ 388 #ifdef CONFIG_PCI 389 390 #define CONFIG_MPC83XX_PCI2 391 392 /* 393 * General PCI 394 * Addresses are mapped 1-1. 395 */ 396 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 397 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 398 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 399 #define CONFIG_SYS_PCI1_MMIO_BASE \ 400 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 401 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 402 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 403 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 404 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 405 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 406 407 #ifdef CONFIG_MPC83XX_PCI2 408 #define CONFIG_SYS_PCI2_MEM_BASE \ 409 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 410 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 411 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 412 #define CONFIG_SYS_PCI2_MMIO_BASE \ 413 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 414 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 415 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 416 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 417 #define CONFIG_SYS_PCI2_IO_PHYS \ 418 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 419 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 420 #endif 421 422 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 423 424 #ifndef CONFIG_PCI_PNP 425 #define PCI_ENET0_IOADDR 0x00000000 426 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 427 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 428 #endif 429 430 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 431 432 #endif 433 434 #define CONFIG_PCI_66M 435 #ifdef CONFIG_PCI_66M 436 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 437 #else 438 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 439 #endif 440 441 /* TSEC */ 442 443 #ifdef CONFIG_TSEC_ENET 444 445 #define CONFIG_MII 446 #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 447 448 #define CONFIG_TSEC1 449 450 #ifdef CONFIG_TSEC1 451 #define CONFIG_HAS_ETH0 452 #define CONFIG_TSEC1_NAME "TSEC0" 453 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 454 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 455 #define TSEC1_PHYIDX 0 456 #define TSEC1_FLAGS TSEC_GIGABIT 457 #endif 458 459 #ifdef CONFIG_TSEC2 460 #define CONFIG_HAS_ETH1 461 #define CONFIG_TSEC2_NAME "TSEC1" 462 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 463 464 #define TSEC2_PHY_ADDR 4 465 #define TSEC2_PHYIDX 0 466 #define TSEC2_FLAGS TSEC_GIGABIT 467 #endif 468 469 #define CONFIG_ETHPRIME "Freescale TSEC" 470 471 #endif 472 473 /* 474 * Environment 475 */ 476 #define CONFIG_ENV_OVERWRITE 477 478 #ifndef CONFIG_SYS_RAMBOOT 479 #define CONFIG_ENV_IS_IN_FLASH 480 #define CONFIG_ENV_ADDR \ 481 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 482 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 483 #define CONFIG_ENV_SIZE 0x2000 484 #else 485 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 486 #undef CONFIG_FLASH_CFI_DRIVER 487 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 488 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 489 #define CONFIG_ENV_SIZE 0x2000 490 #endif 491 492 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 493 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 494 495 /* 496 * BOOTP options 497 */ 498 #define CONFIG_BOOTP_BOOTFILESIZE 499 #define CONFIG_BOOTP_BOOTPATH 500 #define CONFIG_BOOTP_GATEWAY 501 #define CONFIG_BOOTP_HOSTNAME 502 503 504 /* 505 * Command line configuration. 506 */ 507 #include <config_cmd_default.h> 508 509 #define CONFIG_CMD_CACHE 510 #define CONFIG_CMD_DATE 511 #define CONFIG_CMD_IRQ 512 #define CONFIG_CMD_NET 513 #define CONFIG_CMD_PING 514 #define CONFIG_CMD_DHCP 515 #define CONFIG_CMD_SDRAM 516 517 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ 518 || defined(CONFIG_USB_STORAGE) 519 #define CONFIG_DOS_PARTITION 520 #define CONFIG_CMD_FAT 521 #define CONFIG_SUPPORT_VFAT 522 #endif 523 524 #ifdef CONFIG_COMPACT_FLASH 525 #define CONFIG_CMD_IDE 526 #endif 527 528 #ifdef CONFIG_SATA_SIL3114 529 #define CONFIG_CMD_SATA 530 #endif 531 532 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) 533 #define CONFIG_CMD_EXT2 534 #endif 535 536 #ifdef CONFIG_PCI 537 #define CONFIG_CMD_PCI 538 #endif 539 540 #ifdef CONFIG_HARD_I2C 541 #define CONFIG_CMD_I2C 542 #endif 543 544 /* Watchdog */ 545 #undef CONFIG_WATCHDOG /* watchdog disabled */ 546 547 /* 548 * Miscellaneous configurable options 549 */ 550 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 551 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 552 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 553 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 554 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 555 556 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 557 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 558 559 #ifdef CONFIG_MPC8349ITX 560 #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 561 #else 562 #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 563 #endif 564 565 #if defined(CONFIG_CMD_KGDB) 566 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 567 #else 568 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 569 #endif 570 571 /* Print Buffer Size */ 572 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 573 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 574 /* Boot Argument Buffer Size */ 575 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 576 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 577 578 /* 579 * For booting Linux, the board info and command line data 580 * have to be in the first 256 MB of memory, since this is 581 * the maximum mapped by the Linux kernel during initialization. 582 */ 583 /* Initial Memory map for Linux*/ 584 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 585 586 #define CONFIG_SYS_HRCW_LOW (\ 587 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 588 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 589 HRCWL_CSB_TO_CLKIN_4X1 |\ 590 HRCWL_VCO_1X2 |\ 591 HRCWL_CORE_TO_CSB_2X1) 592 593 #ifdef CONFIG_SYS_LOWBOOT 594 #define CONFIG_SYS_HRCW_HIGH (\ 595 HRCWH_PCI_HOST |\ 596 HRCWH_32_BIT_PCI |\ 597 HRCWH_PCI1_ARBITER_ENABLE |\ 598 HRCWH_PCI2_ARBITER_ENABLE |\ 599 HRCWH_CORE_ENABLE |\ 600 HRCWH_FROM_0X00000100 |\ 601 HRCWH_BOOTSEQ_DISABLE |\ 602 HRCWH_SW_WATCHDOG_DISABLE |\ 603 HRCWH_ROM_LOC_LOCAL_16BIT |\ 604 HRCWH_TSEC1M_IN_GMII |\ 605 HRCWH_TSEC2M_IN_GMII) 606 #else 607 #define CONFIG_SYS_HRCW_HIGH (\ 608 HRCWH_PCI_HOST |\ 609 HRCWH_32_BIT_PCI |\ 610 HRCWH_PCI1_ARBITER_ENABLE |\ 611 HRCWH_PCI2_ARBITER_ENABLE |\ 612 HRCWH_CORE_ENABLE |\ 613 HRCWH_FROM_0XFFF00100 |\ 614 HRCWH_BOOTSEQ_DISABLE |\ 615 HRCWH_SW_WATCHDOG_DISABLE |\ 616 HRCWH_ROM_LOC_LOCAL_16BIT |\ 617 HRCWH_TSEC1M_IN_GMII |\ 618 HRCWH_TSEC2M_IN_GMII) 619 #endif 620 621 /* 622 * System performance 623 */ 624 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 625 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 626 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 627 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 628 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 629 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 630 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 631 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 632 633 /* 634 * System IO Config 635 */ 636 /* Needed for gigabit to work on TSEC 1 */ 637 #define CONFIG_SYS_SICRH SICRH_TSOBI1 638 /* USB DR as device + USB MPH as host */ 639 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 640 641 #define CONFIG_SYS_HID0_INIT 0x00000000 642 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 643 644 #define CONFIG_SYS_HID2 HID2_HBE 645 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 646 647 /* DDR */ 648 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 649 | BATL_PP_RW \ 650 | BATL_MEMCOHERENCE) 651 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 652 | BATU_BL_256M \ 653 | BATU_VS \ 654 | BATU_VP) 655 656 /* PCI */ 657 #ifdef CONFIG_PCI 658 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 659 | BATL_PP_RW \ 660 | BATL_MEMCOHERENCE) 661 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 662 | BATU_BL_256M \ 663 | BATU_VS \ 664 | BATU_VP) 665 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 666 | BATL_PP_RW \ 667 | BATL_CACHEINHIBIT \ 668 | BATL_GUARDEDSTORAGE) 669 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 670 | BATU_BL_256M \ 671 | BATU_VS \ 672 | BATU_VP) 673 #else 674 #define CONFIG_SYS_IBAT1L 0 675 #define CONFIG_SYS_IBAT1U 0 676 #define CONFIG_SYS_IBAT2L 0 677 #define CONFIG_SYS_IBAT2U 0 678 #endif 679 680 #ifdef CONFIG_MPC83XX_PCI2 681 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 682 | BATL_PP_RW \ 683 | BATL_MEMCOHERENCE) 684 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 685 | BATU_BL_256M \ 686 | BATU_VS \ 687 | BATU_VP) 688 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 689 | BATL_PP_RW \ 690 | BATL_CACHEINHIBIT \ 691 | BATL_GUARDEDSTORAGE) 692 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 693 | BATU_BL_256M \ 694 | BATU_VS \ 695 | BATU_VP) 696 #else 697 #define CONFIG_SYS_IBAT3L 0 698 #define CONFIG_SYS_IBAT3U 0 699 #define CONFIG_SYS_IBAT4L 0 700 #define CONFIG_SYS_IBAT4U 0 701 #endif 702 703 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 704 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 705 | BATL_PP_RW \ 706 | BATL_CACHEINHIBIT \ 707 | BATL_GUARDEDSTORAGE) 708 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 709 | BATU_BL_256M \ 710 | BATU_VS \ 711 | BATU_VP) 712 713 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 714 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 715 | BATL_PP_RW \ 716 | BATL_MEMCOHERENCE \ 717 | BATL_GUARDEDSTORAGE) 718 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 719 | BATU_BL_256M \ 720 | BATU_VS \ 721 | BATU_VP) 722 723 #define CONFIG_SYS_IBAT7L 0 724 #define CONFIG_SYS_IBAT7U 0 725 726 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 727 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 728 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 729 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 730 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 731 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 732 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 733 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 734 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 735 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 736 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 737 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 738 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 739 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 740 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 741 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 742 743 #if defined(CONFIG_CMD_KGDB) 744 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 745 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 746 #endif 747 748 749 /* 750 * Environment Configuration 751 */ 752 #define CONFIG_ENV_OVERWRITE 753 754 #define CONFIG_NETDEV "eth0" 755 756 #ifdef CONFIG_MPC8349ITX 757 #define CONFIG_HOSTNAME "mpc8349emitx" 758 #else 759 #define CONFIG_HOSTNAME "mpc8349emitxgp" 760 #endif 761 762 /* Default path and filenames */ 763 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 764 #define CONFIG_BOOTFILE "uImage" 765 /* U-Boot image on TFTP server */ 766 #define CONFIG_UBOOTPATH "u-boot.bin" 767 768 #ifdef CONFIG_MPC8349ITX 769 #define CONFIG_FDTFILE "mpc8349emitx.dtb" 770 #else 771 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 772 #endif 773 774 #define CONFIG_BOOTDELAY 6 775 776 #define XMK_STR(x) #x 777 #define MK_STR(x) XMK_STR(x) 778 779 #define CONFIG_BOOTARGS \ 780 "root=/dev/nfs rw" \ 781 " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ 782 " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ 783 MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ 784 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ 785 " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) 786 787 #define CONFIG_EXTRA_ENV_SETTINGS \ 788 "console=" MK_STR(CONFIG_CONSOLE) "\0" \ 789 "netdev=" CONFIG_NETDEV "\0" \ 790 "uboot=" CONFIG_UBOOTPATH "\0" \ 791 "tftpflash=tftpboot $loadaddr $uboot; " \ 792 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 793 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 794 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\ 795 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 796 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ 797 "fdtaddr=780000\0" \ 798 "fdtfile=" CONFIG_FDTFILE "\0" 799 800 #define CONFIG_NFSBOOTCOMMAND \ 801 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 802 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 803 " console=$console,$baudrate $othbootargs; " \ 804 "tftp $loadaddr $bootfile;" \ 805 "tftp $fdtaddr $fdtfile;" \ 806 "bootm $loadaddr - $fdtaddr" 807 808 #define CONFIG_RAMBOOTCOMMAND \ 809 "setenv bootargs root=/dev/ram rw" \ 810 " console=$console,$baudrate $othbootargs; " \ 811 "tftp $ramdiskaddr $ramdiskfile;" \ 812 "tftp $loadaddr $bootfile;" \ 813 "tftp $fdtaddr $fdtfile;" \ 814 "bootm $loadaddr $ramdiskaddr $fdtaddr" 815 816 #undef MK_STR 817 #undef XMK_STR 818 819 #endif 820