1 /* 2 * (C) Copyright 2006 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * mpc8349emds board configuration file 26 * 27 */ 28 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 #undef DEBUG 33 34 /* 35 * High Level Configuration Options 36 */ 37 #define CONFIG_E300 1 /* E300 Family */ 38 #define CONFIG_MPC834X 1 /* MPC834X family */ 39 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 40 #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ 41 42 #undef CONFIG_PCI 43 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 44 45 #define PCI_66M 46 #ifdef PCI_66M 47 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 48 #else 49 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 50 #endif 51 52 #ifndef CONFIG_SYS_CLK_FREQ 53 #ifdef PCI_66M 54 #define CONFIG_SYS_CLK_FREQ 66000000 55 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 56 #else 57 #define CONFIG_SYS_CLK_FREQ 33000000 58 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 59 #endif 60 #endif 61 62 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 63 64 #define CFG_IMMRBAR 0xE0000000 65 66 #undef CFG_DRAM_TEST /* memory test, takes time */ 67 #define CFG_MEMTEST_START 0x00000000 /* memtest region */ 68 #define CFG_MEMTEST_END 0x00100000 69 70 /* 71 * DDR Setup 72 */ 73 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 74 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 75 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 76 77 /* 78 * 32-bit data path mode. 79 * 80 * Please note that using this mode for devices with the real density of 64-bit 81 * effectively reduces the amount of available memory due to the effect of 82 * wrapping around while translating address to row/columns, for example in the 83 * 256MB module the upper 128MB get aliased with contents of the lower 84 * 128MB); normally this define should be used for devices with real 32-bit 85 * data path. 86 */ 87 #undef CONFIG_DDR_32BIT 88 89 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 90 #define CFG_SDRAM_BASE CFG_DDR_BASE 91 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 92 #undef CONFIG_DDR_2T_TIMING 93 94 #if defined(CONFIG_SPD_EEPROM) 95 /* 96 * Determine DDR configuration from I2C interface. 97 */ 98 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 99 #else 100 /* 101 * Manually set up DDR parameters 102 */ 103 #define CFG_DDR_SIZE 256 /* MB */ 104 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 105 #define CFG_DDR_TIMING_1 0x36332321 106 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 107 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 108 #define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 109 110 #if defined(CONFIG_DDR_32BIT) 111 /* set burst length to 8 for 32-bit data path */ 112 #define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ 113 #else 114 /* the default burst length is 4 - for 64-bit data path */ 115 #define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ 116 #endif 117 #endif 118 119 /* 120 * SDRAM on the Local Bus 121 */ 122 #define CFG_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 123 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 124 125 /* 126 * FLASH on the Local Bus 127 */ 128 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 129 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 130 #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 131 #define CFG_FLASH_SIZE 8 /* flash size in MB */ 132 /* #define CFG_FLASH_USE_BUFFER_WRITE */ 133 134 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ 135 (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ 136 BR_V) /* valid */ 137 138 #define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ 139 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ 140 #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 141 142 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 143 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 144 145 #undef CFG_FLASH_CHECKSUM 146 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 147 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 148 149 #define CFG_MID_FLASH_JUMP 0x7F000000 150 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 151 152 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 153 #define CFG_RAMBOOT 154 #else 155 #undef CFG_RAMBOOT 156 #endif 157 158 /* 159 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 160 */ 161 #define CFG_BCSR 0xE2400000 162 #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ 163 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ 164 #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ 165 #define CFG_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ 166 167 #define CONFIG_L1_INIT_RAM 168 #define CFG_INIT_RAM_LOCK 1 169 #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 170 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 171 172 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 173 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 174 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 175 176 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 177 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 178 179 /* 180 * Local Bus LCRR and LBCR regs 181 * LCRR: DLL bypass, Clock divider is 4 182 * External Local Bus rate is 183 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 184 */ 185 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 186 #define CFG_LBC_LBCR 0x00000000 187 188 #define CFG_LB_SDRAM /* if board has SRDAM on local bus */ 189 190 #ifdef CFG_LB_SDRAM 191 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ 192 /* 193 * Base Register 2 and Option Register 2 configure SDRAM. 194 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 195 * 196 * For BR2, need: 197 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 198 * port-size = 32-bits = BR2[19:20] = 11 199 * no parity checking = BR2[21:22] = 00 200 * SDRAM for MSEL = BR2[24:26] = 011 201 * Valid = BR[31] = 1 202 * 203 * 0 4 8 12 16 20 24 28 204 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 205 * 206 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 207 * FIXME: the top 17 bits of BR2. 208 */ 209 210 #define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ 211 #define CFG_LBLAWBAR2_PRELIM 0xF0000000 212 #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 213 214 /* 215 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 216 * 217 * For OR2, need: 218 * 64MB mask for AM, OR2[0:7] = 1111 1100 219 * XAM, OR2[17:18] = 11 220 * 9 columns OR2[19-21] = 010 221 * 13 rows OR2[23-25] = 100 222 * EAD set for extra time OR[31] = 1 223 * 224 * 0 4 8 12 16 20 24 28 225 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 226 */ 227 228 #define CFG_OR2_PRELIM 0xFC006901 229 230 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 231 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 232 233 /* 234 * LSDMR masks 235 */ 236 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 237 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 238 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 239 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 240 #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) 241 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 242 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 243 #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) 244 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 245 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 246 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 247 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 248 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 249 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 250 #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) 251 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 252 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 253 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 254 255 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 256 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 257 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 258 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 259 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 260 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 261 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 262 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 263 264 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ 265 | CFG_LBC_LSDMR_BSMA1516 \ 266 | CFG_LBC_LSDMR_RFCR8 \ 267 | CFG_LBC_LSDMR_PRETOACT6 \ 268 | CFG_LBC_LSDMR_ACTTORW3 \ 269 | CFG_LBC_LSDMR_BL8 \ 270 | CFG_LBC_LSDMR_WRC3 \ 271 | CFG_LBC_LSDMR_CL3 \ 272 ) 273 274 /* 275 * SDRAM Controller configuration sequence. 276 */ 277 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 278 | CFG_LBC_LSDMR_OP_PCHALL) 279 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 280 | CFG_LBC_LSDMR_OP_ARFRSH) 281 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 282 | CFG_LBC_LSDMR_OP_ARFRSH) 283 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 284 | CFG_LBC_LSDMR_OP_MRW) 285 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 286 | CFG_LBC_LSDMR_OP_NORMAL) 287 #endif 288 289 /* 290 * Serial Port 291 */ 292 #define CONFIG_CONS_INDEX 1 293 #undef CONFIG_SERIAL_SOFTWARE_FIFO 294 #define CFG_NS16550 295 #define CFG_NS16550_SERIAL 296 #define CFG_NS16550_REG_SIZE 1 297 #define CFG_NS16550_CLK get_bus_freq(0) 298 299 #define CFG_BAUDRATE_TABLE \ 300 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 301 302 #define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) 303 #define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) 304 305 /* Use the HUSH parser */ 306 #define CFG_HUSH_PARSER 307 #ifdef CFG_HUSH_PARSER 308 #define CFG_PROMPT_HUSH_PS2 "> " 309 #endif 310 311 /* I2C */ 312 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 313 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 314 #define CONFIG_I2C_MULTI_BUS 315 #define CONFIG_I2C_CMD_TREE 316 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 317 #define CFG_I2C_SLAVE 0x7F 318 #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 319 #define CFG_I2C_OFFSET 0x3000 320 #define CFG_I2C2_OFFSET 0x3100 321 322 /* TSEC */ 323 #define CFG_TSEC1_OFFSET 0x24000 324 #define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) 325 #define CFG_TSEC2_OFFSET 0x25000 326 #define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) 327 328 /* USB */ 329 #define CFG_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ 330 331 /* 332 * General PCI 333 * Addresses are mapped 1-1. 334 */ 335 #define CFG_PCI1_MEM_BASE 0x80000000 336 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 337 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 338 #define CFG_PCI1_MMIO_BASE 0x90000000 339 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 340 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 341 #define CFG_PCI1_IO_BASE 0x00000000 342 #define CFG_PCI1_IO_PHYS 0xE2000000 343 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 344 345 #define CFG_PCI2_MEM_BASE 0xA0000000 346 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 347 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 348 #define CFG_PCI2_MMIO_BASE 0xB0000000 349 #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE 350 #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 351 #define CFG_PCI2_IO_BASE 0x00000000 352 #define CFG_PCI2_IO_PHYS 0xE2100000 353 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ 354 355 #if defined(CONFIG_PCI) 356 357 #define PCI_ONE_PCI1 358 #if defined(PCI_64BIT) 359 #undef PCI_ALL_PCI1 360 #undef PCI_TWO_PCI1 361 #undef PCI_ONE_PCI1 362 #endif 363 364 #define CONFIG_NET_MULTI 365 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 366 367 #undef CONFIG_EEPRO100 368 #undef CONFIG_TULIP 369 370 #if !defined(CONFIG_PCI_PNP) 371 #define PCI_ENET0_IOADDR 0xFIXME 372 #define PCI_ENET0_MEMADDR 0xFIXME 373 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 374 #endif 375 376 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 377 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 378 379 #endif /* CONFIG_PCI */ 380 381 /* 382 * TSEC configuration 383 */ 384 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 385 386 #if defined(CONFIG_TSEC_ENET) 387 #ifndef CONFIG_NET_MULTI 388 #define CONFIG_NET_MULTI 1 389 #endif 390 391 #define CONFIG_GMII 1 /* MII PHY management */ 392 #define CONFIG_MPC83XX_TSEC1 1 393 #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" 394 #define CONFIG_MPC83XX_TSEC2 1 395 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" 396 #define TSEC1_PHY_ADDR 0 397 #define TSEC2_PHY_ADDR 1 398 #define TSEC1_PHYIDX 0 399 #define TSEC2_PHYIDX 0 400 401 /* Options are: TSEC[0-1] */ 402 #define CONFIG_ETHPRIME "TSEC0" 403 404 #endif /* CONFIG_TSEC_ENET */ 405 406 /* 407 * Configure on-board RTC 408 */ 409 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 410 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 411 412 /* 413 * Environment 414 */ 415 #ifndef CFG_RAMBOOT 416 #define CFG_ENV_IS_IN_FLASH 1 417 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 418 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 419 #define CFG_ENV_SIZE 0x2000 420 421 /* Address and size of Redundant Environment Sector */ 422 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) 423 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) 424 425 #else 426 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 427 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 428 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 429 #define CFG_ENV_SIZE 0x2000 430 #endif 431 432 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 433 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 434 435 #if defined(CFG_RAMBOOT) 436 #if defined(CONFIG_PCI) 437 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 438 | CFG_CMD_PING \ 439 | CFG_CMD_PCI \ 440 | CFG_CMD_I2C \ 441 | CFG_CMD_DATE) \ 442 & \ 443 ~(CFG_CMD_ENV \ 444 | CFG_CMD_LOADS)) 445 #else 446 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 447 | CFG_CMD_PING \ 448 | CFG_CMD_I2C \ 449 | CFG_CMD_DATE) \ 450 & \ 451 ~(CFG_CMD_ENV \ 452 | CFG_CMD_LOADS)) 453 #endif 454 #else 455 #if defined(CONFIG_PCI) 456 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 457 | CFG_CMD_PCI \ 458 | CFG_CMD_PING \ 459 | CFG_CMD_I2C \ 460 | CFG_CMD_DATE \ 461 ) 462 #else 463 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 464 | CFG_CMD_PING \ 465 | CFG_CMD_I2C \ 466 | CFG_CMD_MII \ 467 | CFG_CMD_DATE \ 468 ) 469 #endif 470 #endif 471 472 #include <cmd_confdefs.h> 473 474 #undef CONFIG_WATCHDOG /* watchdog disabled */ 475 476 /* 477 * Miscellaneous configurable options 478 */ 479 #define CFG_LONGHELP /* undef to save memory */ 480 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 481 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 482 483 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 484 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 485 #else 486 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 487 #endif 488 489 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 490 #define CFG_MAXARGS 16 /* max number of command args */ 491 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 492 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 493 494 /* 495 * For booting Linux, the board info and command line data 496 * have to be in the first 8 MB of memory, since this is 497 * the maximum mapped by the Linux kernel during initialization. 498 */ 499 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 500 501 /* Cache Configuration */ 502 #define CFG_DCACHE_SIZE 32768 503 #define CFG_CACHELINE_SIZE 32 504 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 505 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 506 #endif 507 508 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 509 510 #if 1 /*528/264*/ 511 #define CFG_HRCW_LOW (\ 512 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 513 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 514 HRCWL_CSB_TO_CLKIN |\ 515 HRCWL_VCO_1X2 |\ 516 HRCWL_CORE_TO_CSB_2X1) 517 #elif 0 /*396/132*/ 518 #define CFG_HRCW_LOW (\ 519 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 520 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 521 HRCWL_CSB_TO_CLKIN |\ 522 HRCWL_VCO_1X4 |\ 523 HRCWL_CORE_TO_CSB_3X1) 524 #elif 0 /*264/132*/ 525 #define CFG_HRCW_LOW (\ 526 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 527 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 528 HRCWL_CSB_TO_CLKIN |\ 529 HRCWL_VCO_1X4 |\ 530 HRCWL_CORE_TO_CSB_2X1) 531 #elif 0 /*132/132*/ 532 #define CFG_HRCW_LOW (\ 533 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 534 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 535 HRCWL_CSB_TO_CLKIN |\ 536 HRCWL_VCO_1X4 |\ 537 HRCWL_CORE_TO_CSB_1X1) 538 #elif 0 /*264/264 */ 539 #define CFG_HRCW_LOW (\ 540 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 541 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 542 HRCWL_CSB_TO_CLKIN |\ 543 HRCWL_VCO_1X4 |\ 544 HRCWL_CORE_TO_CSB_1X1) 545 #endif 546 547 #if defined(PCI_64BIT) 548 #define CFG_HRCW_HIGH (\ 549 HRCWH_PCI_HOST |\ 550 HRCWH_64_BIT_PCI |\ 551 HRCWH_PCI1_ARBITER_ENABLE |\ 552 HRCWH_PCI2_ARBITER_DISABLE |\ 553 HRCWH_CORE_ENABLE |\ 554 HRCWH_FROM_0X00000100 |\ 555 HRCWH_BOOTSEQ_DISABLE |\ 556 HRCWH_SW_WATCHDOG_DISABLE |\ 557 HRCWH_ROM_LOC_LOCAL_16BIT |\ 558 HRCWH_TSEC1M_IN_GMII |\ 559 HRCWH_TSEC2M_IN_GMII ) 560 #else 561 #define CFG_HRCW_HIGH (\ 562 HRCWH_PCI_HOST |\ 563 HRCWH_32_BIT_PCI |\ 564 HRCWH_PCI1_ARBITER_ENABLE |\ 565 HRCWH_PCI2_ARBITER_ENABLE |\ 566 HRCWH_CORE_ENABLE |\ 567 HRCWH_FROM_0X00000100 |\ 568 HRCWH_BOOTSEQ_DISABLE |\ 569 HRCWH_SW_WATCHDOG_DISABLE |\ 570 HRCWH_ROM_LOC_LOCAL_16BIT |\ 571 HRCWH_TSEC1M_IN_GMII |\ 572 HRCWH_TSEC2M_IN_GMII ) 573 #endif 574 575 /* System IO Config */ 576 #define CFG_SICRH SICRH_TSOBI1 577 #define CFG_SICRL SICRL_LDP_A 578 579 #define CFG_HID0_INIT 0x000000000 580 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 581 582 /* #define CFG_HID0_FINAL (\ 583 HID0_ENABLE_INSTRUCTION_CACHE |\ 584 HID0_ENABLE_M_BIT |\ 585 HID0_ENABLE_ADDRESS_BROADCAST ) */ 586 587 588 #define CFG_HID2 HID2_HBE 589 590 /* DDR @ 0x00000000 */ 591 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 592 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 593 594 /* PCI @ 0x80000000 */ 595 #ifdef CONFIG_PCI 596 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 597 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 598 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 599 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 600 #else 601 #define CFG_IBAT1L (0) 602 #define CFG_IBAT1U (0) 603 #define CFG_IBAT2L (0) 604 #define CFG_IBAT2U (0) 605 #endif 606 607 #ifdef CONFIG_MPC83XX_PCI2 608 #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 609 #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 610 #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 611 #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 612 #else 613 #define CFG_IBAT3L (0) 614 #define CFG_IBAT3U (0) 615 #define CFG_IBAT4L (0) 616 #define CFG_IBAT4U (0) 617 #endif 618 619 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 620 #define CFG_IBAT5L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 621 #define CFG_IBAT5U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) 622 623 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 624 #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 625 #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 626 627 #define CFG_IBAT7L (0) 628 #define CFG_IBAT7U (0) 629 630 #define CFG_DBAT0L CFG_IBAT0L 631 #define CFG_DBAT0U CFG_IBAT0U 632 #define CFG_DBAT1L CFG_IBAT1L 633 #define CFG_DBAT1U CFG_IBAT1U 634 #define CFG_DBAT2L CFG_IBAT2L 635 #define CFG_DBAT2U CFG_IBAT2U 636 #define CFG_DBAT3L CFG_IBAT3L 637 #define CFG_DBAT3U CFG_IBAT3U 638 #define CFG_DBAT4L CFG_IBAT4L 639 #define CFG_DBAT4U CFG_IBAT4U 640 #define CFG_DBAT5L CFG_IBAT5L 641 #define CFG_DBAT5U CFG_IBAT5U 642 #define CFG_DBAT6L CFG_IBAT6L 643 #define CFG_DBAT6U CFG_IBAT6U 644 #define CFG_DBAT7L CFG_IBAT7L 645 #define CFG_DBAT7U CFG_IBAT7U 646 647 /* 648 * Internal Definitions 649 * 650 * Boot Flags 651 */ 652 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 653 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 654 655 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 656 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 657 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 658 #endif 659 660 /* 661 * Environment Configuration 662 */ 663 #define CONFIG_ENV_OVERWRITE 664 665 #if defined(CONFIG_TSEC_ENET) 666 #define CONFIG_ETHADDR 00:04:9f:ef:23:33 667 #define CONFIG_HAS_ETH1 668 #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 669 #endif 670 671 #define CONFIG_IPADDR 192.168.205.5 672 673 #define CONFIG_HOSTNAME mpc8349emds 674 #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx 675 #define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage 676 677 #define CONFIG_SERVERIP 192.168.1.1 678 #define CONFIG_GATEWAYIP 192.168.1.1 679 #define CONFIG_NETMASK 255.255.255.0 680 681 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 682 683 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 684 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 685 686 #define CONFIG_BAUDRATE 115200 687 688 #define CONFIG_PREBOOT "echo;" \ 689 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ 690 "echo" 691 692 #define CONFIG_EXTRA_ENV_SETTINGS \ 693 "netdev=eth0\0" \ 694 "hostname=mpc8349emds\0" \ 695 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 696 "nfsroot=${serverip}:${rootpath}\0" \ 697 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 698 "addip=setenv bootargs ${bootargs} " \ 699 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 700 ":${hostname}:${netdev}:off panic=1\0" \ 701 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 702 "flash_nfs=run nfsargs addip addtty;" \ 703 "bootm ${kernel_addr}\0" \ 704 "flash_self=run ramargs addip addtty;" \ 705 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 706 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 707 "bootm\0" \ 708 "rootpath=/opt/eldk/ppc_6xx\0" \ 709 "bootfile=/tftpboot/mpc8349emds/uImage\0" \ 710 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 711 "update=protect off fe000000 fe03ffff; " \ 712 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ 713 "upd=run load;run update\0" \ 714 "" 715 716 #define CONFIG_BOOTCOMMAND "run flash_self" 717 718 #endif /* __CONFIG_H */ 719