1 /* 2 * (C) Copyright 2006 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * mpc8349emds board configuration file 26 * 27 */ 28 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 #define DEBUG 33 #undef DEBUG 34 35 /* 36 * High Level Configuration Options 37 */ 38 #define CONFIG_E300 1 /* E300 Family */ 39 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 40 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 41 #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ 42 43 /* FIXME: Real PCI support will come in a follow-up update. */ 44 #undef CONFIG_PCI 45 46 #define PCI_66M 47 #ifdef PCI_66M 48 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 49 #else 50 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 51 #endif 52 53 #ifndef CONFIG_SYS_CLK_FREQ 54 #ifdef PCI_66M 55 #define CONFIG_SYS_CLK_FREQ 66000000 56 #else 57 #define CONFIG_SYS_CLK_FREQ 33000000 58 #endif 59 #endif 60 61 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 62 63 #define CFG_IMMRBAR 0xE0000000 64 65 #undef CFG_DRAM_TEST /* memory test, takes time */ 66 #define CFG_MEMTEST_START 0x00000000 /* memtest region */ 67 #define CFG_MEMTEST_END 0x00100000 68 69 /* 70 * DDR Setup 71 */ 72 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 73 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 74 75 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 76 #define CFG_SDRAM_BASE CFG_DDR_BASE 77 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 78 #undef CONFIG_DDR_2T_TIMING 79 80 #if defined(CONFIG_SPD_EEPROM) 81 /* 82 * Determine DDR configuration from I2C interface. 83 */ 84 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 85 #else 86 /* 87 * Manually set up DDR parameters 88 */ 89 #define CFG_DDR_SIZE 128 /* Mb */ 90 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) 91 #define CFG_DDR_TIMING_1 0x37344321 92 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 93 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 94 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 95 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 96 #endif 97 98 /* 99 * SDRAM on the Local Bus 100 */ 101 #define CFG_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 102 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 103 104 /* 105 * FLASH on the Local Bus 106 */ 107 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 108 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 109 #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 110 #define CFG_FLASH_SIZE 8 /* flash size in MB */ 111 /* #define CFG_FLASH_USE_BUFFER_WRITE */ 112 113 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ 114 (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ 115 BR_V) /* valid */ 116 117 #define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ 118 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ 119 #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 120 121 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 122 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 123 124 #undef CFG_FLASH_CHECKSUM 125 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 126 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 127 128 #define CFG_MID_FLASH_JUMP 0x7F000000 129 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 130 131 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 132 #define CFG_RAMBOOT 133 #else 134 #undef CFG_RAMBOOT 135 #endif 136 137 /* 138 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 139 */ 140 #define CFG_BCSR 0xF8000000 141 #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ 142 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ 143 #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ 144 #define CFG_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ 145 146 #define CONFIG_L1_INIT_RAM 147 #define CFG_INIT_RAM_LOCK 1 148 #define CFG_INIT_RAM_ADDR 0xE8000000 /* Initial RAM address */ 149 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 150 151 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 152 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 153 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 154 155 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 156 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 157 158 /* 159 * Local Bus LCRR and LBCR regs 160 * LCRR: DLL bypass, Clock divider is 4 161 * External Local Bus rate is 162 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 163 */ 164 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 165 #define CFG_LBC_LBCR 0x00000000 166 167 #define CFG_LB_SDRAM /* if board has SRDAM on local bus */ 168 169 #ifdef CFG_LB_SDRAM 170 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ 171 /* 172 * Base Register 2 and Option Register 2 configure SDRAM. 173 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 174 * 175 * For BR2, need: 176 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 177 * port-size = 32-bits = BR2[19:20] = 11 178 * no parity checking = BR2[21:22] = 00 179 * SDRAM for MSEL = BR2[24:26] = 011 180 * Valid = BR[31] = 1 181 * 182 * 0 4 8 12 16 20 24 28 183 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 184 * 185 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 186 * FIXME: the top 17 bits of BR2. 187 */ 188 189 #define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ 190 #define CFG_LBLAWBAR2_PRELIM 0xF0000000 191 #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 192 193 /* 194 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 195 * 196 * For OR2, need: 197 * 64MB mask for AM, OR2[0:7] = 1111 1100 198 * XAM, OR2[17:18] = 11 199 * 9 columns OR2[19-21] = 010 200 * 13 rows OR2[23-25] = 100 201 * EAD set for extra time OR[31] = 1 202 * 203 * 0 4 8 12 16 20 24 28 204 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 205 */ 206 207 #define CFG_OR2_PRELIM 0xFC006901 208 209 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 210 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 211 212 /* 213 * LSDMR masks 214 */ 215 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 216 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 217 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 218 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 219 #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) 220 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 221 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 222 #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) 223 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 224 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 225 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 226 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 227 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 228 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 229 #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) 230 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 231 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 232 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 233 234 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 235 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 236 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 237 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 238 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 239 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 240 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 241 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 242 243 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ 244 | CFG_LBC_LSDMR_BSMA1516 \ 245 | CFG_LBC_LSDMR_RFCR8 \ 246 | CFG_LBC_LSDMR_PRETOACT6 \ 247 | CFG_LBC_LSDMR_ACTTORW3 \ 248 | CFG_LBC_LSDMR_BL8 \ 249 | CFG_LBC_LSDMR_WRC3 \ 250 | CFG_LBC_LSDMR_CL3 \ 251 ) 252 253 /* 254 * SDRAM Controller configuration sequence. 255 */ 256 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 257 | CFG_LBC_LSDMR_OP_PCHALL) 258 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 259 | CFG_LBC_LSDMR_OP_ARFRSH) 260 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 261 | CFG_LBC_LSDMR_OP_ARFRSH) 262 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 263 | CFG_LBC_LSDMR_OP_MRW) 264 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 265 | CFG_LBC_LSDMR_OP_NORMAL) 266 #endif 267 268 /* 269 * Serial Port 270 */ 271 #define CONFIG_CONS_INDEX 1 272 #undef CONFIG_SERIAL_SOFTWARE_FIFO 273 #define CFG_NS16550 274 #define CFG_NS16550_SERIAL 275 #define CFG_NS16550_REG_SIZE 1 276 #define CFG_NS16550_CLK get_bus_freq(0) 277 278 #define CFG_BAUDRATE_TABLE \ 279 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 280 281 #define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) 282 #define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) 283 284 /* Use the HUSH parser */ 285 #define CFG_HUSH_PARSER 286 #ifdef CFG_HUSH_PARSER 287 #define CFG_PROMPT_HUSH_PS2 "> " 288 #endif 289 290 /* I2C */ 291 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 292 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 293 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 294 #define CFG_I2C_SLAVE 0x7F 295 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 296 #define CFG_I2C_OFFSET 0x3000 297 #define CFG_I2C2_OFFSET 0x3100 298 299 /* TSEC */ 300 #define CFG_TSEC1_OFFSET 0x24000 301 #define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) 302 #define CFG_TSEC2_OFFSET 0x25000 303 #define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) 304 305 /* IO Configuration */ 306 #define CFG_IO_CONF (\ 307 IO_CONF_UART |\ 308 IO_CONF_TSEC1 |\ 309 IO_CONF_IRQ0 |\ 310 IO_CONF_IRQ1 |\ 311 IO_CONF_IRQ2 |\ 312 IO_CONF_IRQ3 |\ 313 IO_CONF_IRQ4 |\ 314 IO_CONF_IRQ5 |\ 315 IO_CONF_IRQ6 |\ 316 IO_CONF_IRQ7 ) 317 318 /* 319 * General PCI 320 * Addresses are mapped 1-1. 321 */ 322 #define CFG_PCI1_MEM_BASE 0x80000000 323 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 324 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 325 #define CFG_PCI1_IO_BASE 0x00000000 326 #define CFG_PCI1_IO_PHYS 0xe2000000 327 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 328 329 #define CFG_PCI2_MEM_BASE 0xA0000000 330 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 331 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ 332 #define CFG_PCI2_IO_BASE 0x00000000 333 #define CFG_PCI2_IO_PHYS 0xe3000000 334 #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ 335 336 #if defined(CONFIG_PCI) 337 338 #define PCI_ALL_PCI1 339 #if defined(PCI_64BIT) 340 #undef PCI_ALL_PCI1 341 #undef PCI_TWO_PCI1 342 #undef PCI_ONE_PCI1 343 #endif 344 345 #define CONFIG_NET_MULTI 346 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 347 348 #undef CONFIG_EEPRO100 349 #undef CONFIG_TULIP 350 351 #if !defined(CONFIG_PCI_PNP) 352 #define PCI_ENET0_IOADDR 0xFIXME 353 #define PCI_ENET0_MEMADDR 0xFIXME 354 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 355 #endif 356 357 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 358 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 359 360 #endif /* CONFIG_PCI */ 361 362 /* 363 * TSEC configuration 364 */ 365 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 366 367 #if defined(CONFIG_TSEC_ENET) 368 #ifndef CONFIG_NET_MULTI 369 #define CONFIG_NET_MULTI 1 370 #endif 371 372 #define CONFIG_GMII 1 /* MII PHY management */ 373 #define CONFIG_MPC83XX_TSEC1 1 374 #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" 375 #define CONFIG_MPC83XX_TSEC2 1 376 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" 377 #define TSEC1_PHY_ADDR 0 378 #define TSEC2_PHY_ADDR 1 379 #define TSEC1_PHYIDX 0 380 #define TSEC2_PHYIDX 0 381 382 /* Options are: TSEC[0-1] */ 383 #define CONFIG_ETHPRIME "TSEC0" 384 385 #endif /* CONFIG_TSEC_ENET */ 386 387 /* 388 * Configure on-board RTC 389 */ 390 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 391 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 392 393 /* 394 * Environment 395 */ 396 #ifndef CFG_RAMBOOT 397 #define CFG_ENV_IS_IN_FLASH 1 398 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 399 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 400 #define CFG_ENV_SIZE 0x2000 401 402 /* Address and size of Redundant Environment Sector */ 403 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) 404 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) 405 406 #else 407 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 408 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 409 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 410 #define CFG_ENV_SIZE 0x2000 411 #endif 412 413 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 414 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 415 416 #if defined(CFG_RAMBOOT) 417 #if defined(CONFIG_PCI) 418 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 419 | CFG_CMD_PING \ 420 | CFG_CMD_PCI \ 421 | CFG_CMD_I2C \ 422 | CFG_CMD_DATE) \ 423 & \ 424 ~(CFG_CMD_ENV \ 425 | CFG_CMD_LOADS)) 426 #else 427 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 428 | CFG_CMD_PING \ 429 | CFG_CMD_I2C \ 430 | CFG_CMD_DATE) \ 431 & \ 432 ~(CFG_CMD_ENV \ 433 | CFG_CMD_LOADS)) 434 #endif 435 #else 436 #if defined(CONFIG_PCI) 437 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 438 | CFG_CMD_PCI \ 439 | CFG_CMD_PING \ 440 | CFG_CMD_I2C \ 441 | CFG_CMD_DATE \ 442 ) 443 #else 444 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 445 | CFG_CMD_PING \ 446 | CFG_CMD_I2C \ 447 | CFG_CMD_MII \ 448 | CFG_CMD_DATE \ 449 ) 450 #endif 451 #endif 452 453 #include <cmd_confdefs.h> 454 455 #undef CONFIG_WATCHDOG /* watchdog disabled */ 456 457 /* 458 * Miscellaneous configurable options 459 */ 460 #define CFG_LONGHELP /* undef to save memory */ 461 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 462 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 463 464 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 465 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 466 #else 467 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 468 #endif 469 470 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 471 #define CFG_MAXARGS 16 /* max number of command args */ 472 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 473 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 474 475 /* 476 * For booting Linux, the board info and command line data 477 * have to be in the first 8 MB of memory, since this is 478 * the maximum mapped by the Linux kernel during initialization. 479 */ 480 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 481 482 /* Cache Configuration */ 483 #define CFG_DCACHE_SIZE 32768 484 #define CFG_CACHELINE_SIZE 32 485 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 486 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 487 #endif 488 489 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 490 491 #if 1 /*528/264*/ 492 #define CFG_HRCW_LOW (\ 493 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 494 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 495 HRCWL_CSB_TO_CLKIN_4X1 |\ 496 HRCWL_VCO_1X2 |\ 497 HRCWL_CORE_TO_CSB_2X1) 498 #elif 0 /*396/132*/ 499 #define CFG_HRCW_LOW (\ 500 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 501 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 502 HRCWL_CSB_TO_CLKIN_2X1 |\ 503 HRCWL_VCO_1X4 |\ 504 HRCWL_CORE_TO_CSB_3X1) 505 #elif 0 /*264/132*/ 506 #define CFG_HRCW_LOW (\ 507 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 508 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 509 HRCWL_CSB_TO_CLKIN_2X1 |\ 510 HRCWL_VCO_1X4 |\ 511 HRCWL_CORE_TO_CSB_2X1) 512 #elif 0 /*132/132*/ 513 #define CFG_HRCW_LOW (\ 514 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 515 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 516 HRCWL_CSB_TO_CLKIN_2X1 |\ 517 HRCWL_VCO_1X4 |\ 518 HRCWL_CORE_TO_CSB_1X1) 519 #elif 0 /*264/264 */ 520 #define CFG_HRCW_LOW (\ 521 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 522 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 523 HRCWL_CSB_TO_CLKIN_4X1 |\ 524 HRCWL_VCO_1X4 |\ 525 HRCWL_CORE_TO_CSB_1X1) 526 #endif 527 528 #if defined(PCI_64BIT) 529 #define CFG_HRCW_HIGH (\ 530 HRCWH_PCI_HOST |\ 531 HRCWH_64_BIT_PCI |\ 532 HRCWH_PCI1_ARBITER_ENABLE |\ 533 HRCWH_PCI2_ARBITER_DISABLE |\ 534 HRCWH_CORE_ENABLE |\ 535 HRCWH_FROM_0X00000100 |\ 536 HRCWH_BOOTSEQ_DISABLE |\ 537 HRCWH_SW_WATCHDOG_DISABLE |\ 538 HRCWH_ROM_LOC_LOCAL_16BIT |\ 539 HRCWH_TSEC1M_IN_GMII |\ 540 HRCWH_TSEC2M_IN_GMII ) 541 #else 542 #define CFG_HRCW_HIGH (\ 543 HRCWH_PCI_HOST |\ 544 HRCWH_32_BIT_PCI |\ 545 HRCWH_PCI1_ARBITER_ENABLE |\ 546 HRCWH_PCI2_ARBITER_ENABLE |\ 547 HRCWH_CORE_ENABLE |\ 548 HRCWH_FROM_0X00000100 |\ 549 HRCWH_BOOTSEQ_DISABLE |\ 550 HRCWH_SW_WATCHDOG_DISABLE |\ 551 HRCWH_ROM_LOC_LOCAL_16BIT |\ 552 HRCWH_TSEC1M_IN_GMII |\ 553 HRCWH_TSEC2M_IN_GMII ) 554 #endif 555 556 /* System IO Config */ 557 #define CFG_SICRH SICRH_TSOBI1 558 #define CFG_SICRL SICRL_LDP_A 559 560 #define CFG_HID0_INIT 0x000000000 561 #define CFG_HID0_FINAL CFG_HID0_INIT 562 563 /* #define CFG_HID0_FINAL (\ 564 HID0_ENABLE_INSTRUCTION_CACHE |\ 565 HID0_ENABLE_M_BIT |\ 566 HID0_ENABLE_ADDRESS_BROADCAST ) */ 567 568 569 #define CFG_HID2 HID2_HBE 570 571 /* DDR @ 0x00000000 */ 572 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 573 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 574 575 /* PCI @ 0x80000000 */ 576 #ifdef CONFIG_PCI 577 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 578 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 579 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 580 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 581 #else 582 #define CFG_IBAT1L (0) 583 #define CFG_IBAT1U (0) 584 #define CFG_IBAT2L (0) 585 #define CFG_IBAT2U (0) 586 #endif 587 588 /* IMMRBAR @ 0xE0000000 */ 589 #define CFG_IBAT3L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 590 #define CFG_IBAT3U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 591 592 /* stack in DCACHE (no backing mem) @ 0xE8000000 */ 593 #define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 594 #define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 595 596 /* LBC SDRAM @ 0xF0000000 */ 597 #define CFG_IBAT5L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 598 #define CFG_IBAT5U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) 599 600 /* BCSR @ 0xF8000000 */ 601 #define CFG_IBAT6L (CFG_BCSR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 602 #define CFG_IBAT6U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) 603 604 /* FLASH @ 0xFE000000 */ 605 #define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 606 #define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP) 607 608 #define CFG_DBAT0L CFG_IBAT0L 609 #define CFG_DBAT0U CFG_IBAT0U 610 #define CFG_DBAT1L CFG_IBAT1L 611 #define CFG_DBAT1U CFG_IBAT1U 612 #define CFG_DBAT2L CFG_IBAT2L 613 #define CFG_DBAT2U CFG_IBAT2U 614 #define CFG_DBAT3L CFG_IBAT3L 615 #define CFG_DBAT3U CFG_IBAT3U 616 #define CFG_DBAT4L CFG_IBAT4L 617 #define CFG_DBAT4U CFG_IBAT4U 618 #define CFG_DBAT5L CFG_IBAT5L 619 #define CFG_DBAT5U CFG_IBAT5U 620 #define CFG_DBAT6L CFG_IBAT6L 621 #define CFG_DBAT6U CFG_IBAT6U 622 #define CFG_DBAT7L CFG_IBAT7L 623 #define CFG_DBAT7U CFG_IBAT7U 624 625 /* 626 * Internal Definitions 627 * 628 * Boot Flags 629 */ 630 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 631 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 632 633 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 634 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 635 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 636 #endif 637 638 /* 639 * Environment Configuration 640 */ 641 #define CONFIG_ENV_OVERWRITE 642 643 #if defined(CONFIG_TSEC_ENET) 644 #define CONFIG_ETHADDR 00:04:9f:ef:23:33 645 #define CONFIG_HAS_ETH1 646 #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 647 #endif 648 649 #define CONFIG_IPADDR 192.168.205.5 650 651 #define CONFIG_HOSTNAME mpc8349emds 652 #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx 653 #define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage 654 655 #define CONFIG_SERVERIP 192.168.1.1 656 #define CONFIG_GATEWAYIP 192.168.1.1 657 #define CONFIG_NETMASK 255.255.255.0 658 659 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 660 661 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 662 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 663 664 #define CONFIG_BAUDRATE 115200 665 666 #define CONFIG_PREBOOT "echo;" \ 667 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ 668 "echo" 669 670 #define CONFIG_EXTRA_ENV_SETTINGS \ 671 "netdev=eth0\0" \ 672 "hostname=mpc8349emds\0" \ 673 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 674 "nfsroot=${serverip}:${rootpath}\0" \ 675 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 676 "addip=setenv bootargs ${bootargs} " \ 677 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 678 ":${hostname}:${netdev}:off panic=1\0" \ 679 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 680 "flash_nfs=run nfsargs addip addtty;" \ 681 "bootm ${kernel_addr}\0" \ 682 "flash_self=run ramargs addip addtty;" \ 683 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 684 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 685 "bootm\0" \ 686 "rootpath=/opt/eldk/ppc_6xx\0" \ 687 "bootfile=/tftpboot/mpc8349emds/uImage\0" \ 688 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 689 "update=protect off fe000000 fe03ffff; " \ 690 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ 691 "upd=run load;run update\0" \ 692 "" 693 694 #define CONFIG_BOOTCOMMAND "run flash_self" 695 696 #endif /* __CONFIG_H */ 697