1 /* 2 * (C) Copyright 2006 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * mpc8349emds board configuration file 26 * 27 */ 28 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 #define DEBUG 33 #undef DEBUG 34 35 /* 36 * High Level Configuration Options 37 */ 38 #define CONFIG_E300 1 /* E300 Family */ 39 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 40 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 41 #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ 42 43 /* FIXME: Real PCI support will come in a follow-up update. */ 44 #undef CONFIG_PCI 45 46 #define PCI_66M 47 #ifdef PCI_66M 48 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 49 #else 50 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 51 #endif 52 53 #ifndef CONFIG_SYS_CLK_FREQ 54 #ifdef PCI_66M 55 #define CONFIG_SYS_CLK_FREQ 66000000 56 #else 57 #define CONFIG_SYS_CLK_FREQ 33000000 58 #endif 59 #endif 60 61 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 62 63 #define CFG_IMMRBAR 0xE0000000 64 65 #undef CFG_DRAM_TEST /* memory test, takes time */ 66 #define CFG_MEMTEST_START 0x00000000 /* memtest region */ 67 #define CFG_MEMTEST_END 0x00100000 68 69 /* 70 * DDR Setup 71 */ 72 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 73 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 74 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 75 76 /* 77 * 32-bit data path mode. 78 * 79 * Please note that using this mode for devices with the real density of 64-bit 80 * effectively reduces the amount of available memory due to the effect of 81 * wrapping around while translating address to row/columns, for example in the 82 * 256MB module the upper 128MB get aliased with contents of the lower 83 * 128MB); normally this define should be used for devices with real 32-bit 84 * data path. 85 */ 86 #undef CONFIG_DDR_32BIT 87 88 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 89 #define CFG_SDRAM_BASE CFG_DDR_BASE 90 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 91 #undef CONFIG_DDR_2T_TIMING 92 93 #if defined(CONFIG_SPD_EEPROM) 94 /* 95 * Determine DDR configuration from I2C interface. 96 */ 97 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 98 #else 99 /* 100 * Manually set up DDR parameters 101 */ 102 #define CFG_DDR_SIZE 256 /* MB */ 103 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 104 #define CFG_DDR_TIMING_1 0x36332321 105 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 106 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 107 #define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 108 109 #if defined(CONFIG_DDR_32BIT) 110 /* set burst length to 8 for 32-bit data path */ 111 #define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ 112 #else 113 /* the default burst length is 4 - for 64-bit data path */ 114 #define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ 115 #endif 116 #endif 117 118 /* 119 * SDRAM on the Local Bus 120 */ 121 #define CFG_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 122 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 123 124 /* 125 * FLASH on the Local Bus 126 */ 127 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 128 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 129 #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 130 #define CFG_FLASH_SIZE 8 /* flash size in MB */ 131 /* #define CFG_FLASH_USE_BUFFER_WRITE */ 132 133 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ 134 (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ 135 BR_V) /* valid */ 136 137 #define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ 138 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ 139 #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 140 141 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 142 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 143 144 #undef CFG_FLASH_CHECKSUM 145 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 146 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 147 148 #define CFG_MID_FLASH_JUMP 0x7F000000 149 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 150 151 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 152 #define CFG_RAMBOOT 153 #else 154 #undef CFG_RAMBOOT 155 #endif 156 157 /* 158 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 159 */ 160 #define CFG_BCSR 0xF8000000 161 #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ 162 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ 163 #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ 164 #define CFG_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ 165 166 #define CONFIG_L1_INIT_RAM 167 #define CFG_INIT_RAM_LOCK 1 168 #define CFG_INIT_RAM_ADDR 0xE8000000 /* Initial RAM address */ 169 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 170 171 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 172 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 173 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 174 175 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 176 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 177 178 /* 179 * Local Bus LCRR and LBCR regs 180 * LCRR: DLL bypass, Clock divider is 4 181 * External Local Bus rate is 182 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 183 */ 184 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 185 #define CFG_LBC_LBCR 0x00000000 186 187 #define CFG_LB_SDRAM /* if board has SRDAM on local bus */ 188 189 #ifdef CFG_LB_SDRAM 190 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ 191 /* 192 * Base Register 2 and Option Register 2 configure SDRAM. 193 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 194 * 195 * For BR2, need: 196 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 197 * port-size = 32-bits = BR2[19:20] = 11 198 * no parity checking = BR2[21:22] = 00 199 * SDRAM for MSEL = BR2[24:26] = 011 200 * Valid = BR[31] = 1 201 * 202 * 0 4 8 12 16 20 24 28 203 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 204 * 205 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 206 * FIXME: the top 17 bits of BR2. 207 */ 208 209 #define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ 210 #define CFG_LBLAWBAR2_PRELIM 0xF0000000 211 #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 212 213 /* 214 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 215 * 216 * For OR2, need: 217 * 64MB mask for AM, OR2[0:7] = 1111 1100 218 * XAM, OR2[17:18] = 11 219 * 9 columns OR2[19-21] = 010 220 * 13 rows OR2[23-25] = 100 221 * EAD set for extra time OR[31] = 1 222 * 223 * 0 4 8 12 16 20 24 28 224 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 225 */ 226 227 #define CFG_OR2_PRELIM 0xFC006901 228 229 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 230 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 231 232 /* 233 * LSDMR masks 234 */ 235 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 236 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 237 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 238 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 239 #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) 240 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 241 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 242 #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) 243 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 244 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 245 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 246 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 247 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 248 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 249 #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) 250 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 251 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 252 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 253 254 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 255 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 256 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 257 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 258 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 259 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 260 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 261 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 262 263 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ 264 | CFG_LBC_LSDMR_BSMA1516 \ 265 | CFG_LBC_LSDMR_RFCR8 \ 266 | CFG_LBC_LSDMR_PRETOACT6 \ 267 | CFG_LBC_LSDMR_ACTTORW3 \ 268 | CFG_LBC_LSDMR_BL8 \ 269 | CFG_LBC_LSDMR_WRC3 \ 270 | CFG_LBC_LSDMR_CL3 \ 271 ) 272 273 /* 274 * SDRAM Controller configuration sequence. 275 */ 276 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 277 | CFG_LBC_LSDMR_OP_PCHALL) 278 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 279 | CFG_LBC_LSDMR_OP_ARFRSH) 280 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 281 | CFG_LBC_LSDMR_OP_ARFRSH) 282 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 283 | CFG_LBC_LSDMR_OP_MRW) 284 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 285 | CFG_LBC_LSDMR_OP_NORMAL) 286 #endif 287 288 /* 289 * Serial Port 290 */ 291 #define CONFIG_CONS_INDEX 1 292 #undef CONFIG_SERIAL_SOFTWARE_FIFO 293 #define CFG_NS16550 294 #define CFG_NS16550_SERIAL 295 #define CFG_NS16550_REG_SIZE 1 296 #define CFG_NS16550_CLK get_bus_freq(0) 297 298 #define CFG_BAUDRATE_TABLE \ 299 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 300 301 #define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) 302 #define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) 303 304 /* Use the HUSH parser */ 305 #define CFG_HUSH_PARSER 306 #ifdef CFG_HUSH_PARSER 307 #define CFG_PROMPT_HUSH_PS2 "> " 308 #endif 309 310 /* I2C */ 311 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 312 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 313 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 314 #define CFG_I2C_SLAVE 0x7F 315 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 316 #define CFG_I2C_OFFSET 0x3000 317 #define CFG_I2C2_OFFSET 0x3100 318 319 /* TSEC */ 320 #define CFG_TSEC1_OFFSET 0x24000 321 #define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) 322 #define CFG_TSEC2_OFFSET 0x25000 323 #define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) 324 325 /* IO Configuration */ 326 #define CFG_IO_CONF (\ 327 IO_CONF_UART |\ 328 IO_CONF_TSEC1 |\ 329 IO_CONF_IRQ0 |\ 330 IO_CONF_IRQ1 |\ 331 IO_CONF_IRQ2 |\ 332 IO_CONF_IRQ3 |\ 333 IO_CONF_IRQ4 |\ 334 IO_CONF_IRQ5 |\ 335 IO_CONF_IRQ6 |\ 336 IO_CONF_IRQ7 ) 337 338 /* 339 * General PCI 340 * Addresses are mapped 1-1. 341 */ 342 #define CFG_PCI1_MEM_BASE 0x80000000 343 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 344 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 345 #define CFG_PCI1_IO_BASE 0x00000000 346 #define CFG_PCI1_IO_PHYS 0xe2000000 347 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 348 349 #define CFG_PCI2_MEM_BASE 0xA0000000 350 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 351 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ 352 #define CFG_PCI2_IO_BASE 0x00000000 353 #define CFG_PCI2_IO_PHYS 0xe3000000 354 #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ 355 356 #if defined(CONFIG_PCI) 357 358 #define PCI_ALL_PCI1 359 #if defined(PCI_64BIT) 360 #undef PCI_ALL_PCI1 361 #undef PCI_TWO_PCI1 362 #undef PCI_ONE_PCI1 363 #endif 364 365 #define CONFIG_NET_MULTI 366 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 367 368 #undef CONFIG_EEPRO100 369 #undef CONFIG_TULIP 370 371 #if !defined(CONFIG_PCI_PNP) 372 #define PCI_ENET0_IOADDR 0xFIXME 373 #define PCI_ENET0_MEMADDR 0xFIXME 374 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 375 #endif 376 377 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 378 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 379 380 #endif /* CONFIG_PCI */ 381 382 /* 383 * TSEC configuration 384 */ 385 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 386 387 #if defined(CONFIG_TSEC_ENET) 388 #ifndef CONFIG_NET_MULTI 389 #define CONFIG_NET_MULTI 1 390 #endif 391 392 #define CONFIG_GMII 1 /* MII PHY management */ 393 #define CONFIG_MPC83XX_TSEC1 1 394 #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" 395 #define CONFIG_MPC83XX_TSEC2 1 396 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" 397 #define TSEC1_PHY_ADDR 0 398 #define TSEC2_PHY_ADDR 1 399 #define TSEC1_PHYIDX 0 400 #define TSEC2_PHYIDX 0 401 402 /* Options are: TSEC[0-1] */ 403 #define CONFIG_ETHPRIME "TSEC0" 404 405 #endif /* CONFIG_TSEC_ENET */ 406 407 /* 408 * Configure on-board RTC 409 */ 410 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 411 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 412 413 /* 414 * Environment 415 */ 416 #ifndef CFG_RAMBOOT 417 #define CFG_ENV_IS_IN_FLASH 1 418 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 419 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 420 #define CFG_ENV_SIZE 0x2000 421 422 /* Address and size of Redundant Environment Sector */ 423 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) 424 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) 425 426 #else 427 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 428 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 429 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 430 #define CFG_ENV_SIZE 0x2000 431 #endif 432 433 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 434 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 435 436 #if defined(CFG_RAMBOOT) 437 #if defined(CONFIG_PCI) 438 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 439 | CFG_CMD_PING \ 440 | CFG_CMD_PCI \ 441 | CFG_CMD_I2C \ 442 | CFG_CMD_DATE) \ 443 & \ 444 ~(CFG_CMD_ENV \ 445 | CFG_CMD_LOADS)) 446 #else 447 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 448 | CFG_CMD_PING \ 449 | CFG_CMD_I2C \ 450 | CFG_CMD_DATE) \ 451 & \ 452 ~(CFG_CMD_ENV \ 453 | CFG_CMD_LOADS)) 454 #endif 455 #else 456 #if defined(CONFIG_PCI) 457 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 458 | CFG_CMD_PCI \ 459 | CFG_CMD_PING \ 460 | CFG_CMD_I2C \ 461 | CFG_CMD_DATE \ 462 ) 463 #else 464 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 465 | CFG_CMD_PING \ 466 | CFG_CMD_I2C \ 467 | CFG_CMD_MII \ 468 | CFG_CMD_DATE \ 469 ) 470 #endif 471 #endif 472 473 #include <cmd_confdefs.h> 474 475 #undef CONFIG_WATCHDOG /* watchdog disabled */ 476 477 /* 478 * Miscellaneous configurable options 479 */ 480 #define CFG_LONGHELP /* undef to save memory */ 481 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 482 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 483 484 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 485 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 486 #else 487 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 488 #endif 489 490 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 491 #define CFG_MAXARGS 16 /* max number of command args */ 492 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 493 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 494 495 /* 496 * For booting Linux, the board info and command line data 497 * have to be in the first 8 MB of memory, since this is 498 * the maximum mapped by the Linux kernel during initialization. 499 */ 500 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 501 502 /* Cache Configuration */ 503 #define CFG_DCACHE_SIZE 32768 504 #define CFG_CACHELINE_SIZE 32 505 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 506 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 507 #endif 508 509 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 510 511 #if 1 /*528/264*/ 512 #define CFG_HRCW_LOW (\ 513 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 514 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 515 HRCWL_CSB_TO_CLKIN_4X1 |\ 516 HRCWL_VCO_1X2 |\ 517 HRCWL_CORE_TO_CSB_2X1) 518 #elif 0 /*396/132*/ 519 #define CFG_HRCW_LOW (\ 520 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 521 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 522 HRCWL_CSB_TO_CLKIN_2X1 |\ 523 HRCWL_VCO_1X4 |\ 524 HRCWL_CORE_TO_CSB_3X1) 525 #elif 0 /*264/132*/ 526 #define CFG_HRCW_LOW (\ 527 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 528 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 529 HRCWL_CSB_TO_CLKIN_2X1 |\ 530 HRCWL_VCO_1X4 |\ 531 HRCWL_CORE_TO_CSB_2X1) 532 #elif 0 /*132/132*/ 533 #define CFG_HRCW_LOW (\ 534 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 535 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 536 HRCWL_CSB_TO_CLKIN_2X1 |\ 537 HRCWL_VCO_1X4 |\ 538 HRCWL_CORE_TO_CSB_1X1) 539 #elif 0 /*264/264 */ 540 #define CFG_HRCW_LOW (\ 541 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 542 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 543 HRCWL_CSB_TO_CLKIN_4X1 |\ 544 HRCWL_VCO_1X4 |\ 545 HRCWL_CORE_TO_CSB_1X1) 546 #endif 547 548 #if defined(PCI_64BIT) 549 #define CFG_HRCW_HIGH (\ 550 HRCWH_PCI_HOST |\ 551 HRCWH_64_BIT_PCI |\ 552 HRCWH_PCI1_ARBITER_ENABLE |\ 553 HRCWH_PCI2_ARBITER_DISABLE |\ 554 HRCWH_CORE_ENABLE |\ 555 HRCWH_FROM_0X00000100 |\ 556 HRCWH_BOOTSEQ_DISABLE |\ 557 HRCWH_SW_WATCHDOG_DISABLE |\ 558 HRCWH_ROM_LOC_LOCAL_16BIT |\ 559 HRCWH_TSEC1M_IN_GMII |\ 560 HRCWH_TSEC2M_IN_GMII ) 561 #else 562 #define CFG_HRCW_HIGH (\ 563 HRCWH_PCI_HOST |\ 564 HRCWH_32_BIT_PCI |\ 565 HRCWH_PCI1_ARBITER_ENABLE |\ 566 HRCWH_PCI2_ARBITER_ENABLE |\ 567 HRCWH_CORE_ENABLE |\ 568 HRCWH_FROM_0X00000100 |\ 569 HRCWH_BOOTSEQ_DISABLE |\ 570 HRCWH_SW_WATCHDOG_DISABLE |\ 571 HRCWH_ROM_LOC_LOCAL_16BIT |\ 572 HRCWH_TSEC1M_IN_GMII |\ 573 HRCWH_TSEC2M_IN_GMII ) 574 #endif 575 576 /* System IO Config */ 577 #define CFG_SICRH SICRH_TSOBI1 578 #define CFG_SICRL SICRL_LDP_A 579 580 #define CFG_HID0_INIT 0x000000000 581 #define CFG_HID0_FINAL CFG_HID0_INIT 582 583 /* #define CFG_HID0_FINAL (\ 584 HID0_ENABLE_INSTRUCTION_CACHE |\ 585 HID0_ENABLE_M_BIT |\ 586 HID0_ENABLE_ADDRESS_BROADCAST ) */ 587 588 589 #define CFG_HID2 HID2_HBE 590 591 /* DDR @ 0x00000000 */ 592 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 593 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 594 595 /* PCI @ 0x80000000 */ 596 #ifdef CONFIG_PCI 597 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 598 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 599 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 600 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 601 #else 602 #define CFG_IBAT1L (0) 603 #define CFG_IBAT1U (0) 604 #define CFG_IBAT2L (0) 605 #define CFG_IBAT2U (0) 606 #endif 607 608 /* IMMRBAR @ 0xE0000000 */ 609 #define CFG_IBAT3L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 610 #define CFG_IBAT3U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 611 612 /* stack in DCACHE (no backing mem) @ 0xE8000000 */ 613 #define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 614 #define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 615 616 /* LBC SDRAM @ 0xF0000000 */ 617 #define CFG_IBAT5L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 618 #define CFG_IBAT5U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) 619 620 /* BCSR @ 0xF8000000 */ 621 #define CFG_IBAT6L (CFG_BCSR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 622 #define CFG_IBAT6U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) 623 624 /* FLASH @ 0xFE000000 */ 625 #define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 626 #define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP) 627 628 #define CFG_DBAT0L CFG_IBAT0L 629 #define CFG_DBAT0U CFG_IBAT0U 630 #define CFG_DBAT1L CFG_IBAT1L 631 #define CFG_DBAT1U CFG_IBAT1U 632 #define CFG_DBAT2L CFG_IBAT2L 633 #define CFG_DBAT2U CFG_IBAT2U 634 #define CFG_DBAT3L CFG_IBAT3L 635 #define CFG_DBAT3U CFG_IBAT3U 636 #define CFG_DBAT4L CFG_IBAT4L 637 #define CFG_DBAT4U CFG_IBAT4U 638 #define CFG_DBAT5L CFG_IBAT5L 639 #define CFG_DBAT5U CFG_IBAT5U 640 #define CFG_DBAT6L CFG_IBAT6L 641 #define CFG_DBAT6U CFG_IBAT6U 642 #define CFG_DBAT7L CFG_IBAT7L 643 #define CFG_DBAT7U CFG_IBAT7U 644 645 /* 646 * Internal Definitions 647 * 648 * Boot Flags 649 */ 650 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 651 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 652 653 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 654 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 655 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 656 #endif 657 658 /* 659 * Environment Configuration 660 */ 661 #define CONFIG_ENV_OVERWRITE 662 663 #if defined(CONFIG_TSEC_ENET) 664 #define CONFIG_ETHADDR 00:04:9f:ef:23:33 665 #define CONFIG_HAS_ETH1 666 #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 667 #endif 668 669 #define CONFIG_IPADDR 192.168.205.5 670 671 #define CONFIG_HOSTNAME mpc8349emds 672 #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx 673 #define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage 674 675 #define CONFIG_SERVERIP 192.168.1.1 676 #define CONFIG_GATEWAYIP 192.168.1.1 677 #define CONFIG_NETMASK 255.255.255.0 678 679 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 680 681 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 682 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 683 684 #define CONFIG_BAUDRATE 115200 685 686 #define CONFIG_PREBOOT "echo;" \ 687 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ 688 "echo" 689 690 #define CONFIG_EXTRA_ENV_SETTINGS \ 691 "netdev=eth0\0" \ 692 "hostname=mpc8349emds\0" \ 693 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 694 "nfsroot=${serverip}:${rootpath}\0" \ 695 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 696 "addip=setenv bootargs ${bootargs} " \ 697 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 698 ":${hostname}:${netdev}:off panic=1\0" \ 699 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 700 "flash_nfs=run nfsargs addip addtty;" \ 701 "bootm ${kernel_addr}\0" \ 702 "flash_self=run ramargs addip addtty;" \ 703 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 704 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 705 "bootm\0" \ 706 "rootpath=/opt/eldk/ppc_6xx\0" \ 707 "bootfile=/tftpboot/mpc8349emds/uImage\0" \ 708 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 709 "update=protect off fe000000 fe03ffff; " \ 710 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ 711 "upd=run load;run update\0" \ 712 "" 713 714 #define CONFIG_BOOTCOMMAND "run flash_self" 715 716 #endif /* __CONFIG_H */ 717