1 /* 2 * (C) Copyright 2006-2010 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * mpc8349emds board configuration file 26 * 27 */ 28 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* 33 * High Level Configuration Options 34 */ 35 #define CONFIG_E300 1 /* E300 Family */ 36 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 37 #define CONFIG_MPC834x 1 /* MPC834x family */ 38 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 39 #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ 40 41 #define CONFIG_SYS_TEXT_BASE 0xFE000000 42 43 #define CONFIG_PCI_66M 44 #ifdef CONFIG_PCI_66M 45 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 46 #else 47 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 48 #endif 49 50 #ifdef CONFIG_PCISLAVE 51 #define CONFIG_PCI 52 #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ 53 #endif /* CONFIG_PCISLAVE */ 54 55 #ifndef CONFIG_SYS_CLK_FREQ 56 #ifdef CONFIG_PCI_66M 57 #define CONFIG_SYS_CLK_FREQ 66000000 58 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 59 #else 60 #define CONFIG_SYS_CLK_FREQ 33000000 61 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 62 #endif 63 #endif 64 65 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 66 67 #define CONFIG_SYS_IMMR 0xE0000000 68 69 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 70 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 71 #define CONFIG_SYS_MEMTEST_END 0x00100000 72 73 /* 74 * DDR Setup 75 */ 76 #define CONFIG_DDR_ECC /* support DDR ECC function */ 77 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 78 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 79 80 /* 81 * define CONFIG_FSL_DDR2 to use unified DDR driver 82 * undefine it to use old spd_sdram.c 83 */ 84 #define CONFIG_FSL_DDR2 85 #ifdef CONFIG_FSL_DDR2 86 #define CONFIG_SYS_SPD_BUS_NUM 0 87 #define SPD_EEPROM_ADDRESS1 0x52 88 #define SPD_EEPROM_ADDRESS2 0x51 89 #define CONFIG_NUM_DDR_CONTROLLERS 1 90 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 91 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 92 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 93 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 94 #endif 95 96 /* 97 * 32-bit data path mode. 98 * 99 * Please note that using this mode for devices with the real density of 64-bit 100 * effectively reduces the amount of available memory due to the effect of 101 * wrapping around while translating address to row/columns, for example in the 102 * 256MB module the upper 128MB get aliased with contents of the lower 103 * 128MB); normally this define should be used for devices with real 32-bit 104 * data path. 105 */ 106 #undef CONFIG_DDR_32BIT 107 108 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 109 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 110 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 111 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 112 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 113 #undef CONFIG_DDR_2T_TIMING 114 115 /* 116 * DDRCDR - DDR Control Driver Register 117 */ 118 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 119 120 #if defined(CONFIG_SPD_EEPROM) 121 /* 122 * Determine DDR configuration from I2C interface. 123 */ 124 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 125 #else 126 /* 127 * Manually set up DDR parameters 128 */ 129 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 130 #if defined(CONFIG_DDR_II) 131 #define CONFIG_SYS_DDRCDR 0x80080001 132 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f 133 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 134 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 135 #define CONFIG_SYS_DDR_TIMING_1 0x38357322 136 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 137 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 138 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 139 #define CONFIG_SYS_DDR_MODE 0x47d00432 140 #define CONFIG_SYS_DDR_MODE2 0x8000c000 141 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 142 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 143 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 144 #else 145 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \ 146 | CSCONFIG_ROW_BIT_13 \ 147 | CSCONFIG_COL_BIT_10) 148 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 149 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 150 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 151 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 152 153 #if defined(CONFIG_DDR_32BIT) 154 /* set burst length to 8 for 32-bit data path */ 155 /* DLL,normal,seq,4/2.5, 8 burst len */ 156 #define CONFIG_SYS_DDR_MODE 0x00000023 157 #else 158 /* the default burst length is 4 - for 64-bit data path */ 159 /* DLL,normal,seq,4/2.5, 4 burst len */ 160 #define CONFIG_SYS_DDR_MODE 0x00000022 161 #endif 162 #endif 163 #endif 164 165 /* 166 * SDRAM on the Local Bus 167 */ 168 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 169 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 170 171 /* 172 * FLASH on the Local Bus 173 */ 174 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 175 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 176 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 177 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ 178 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 179 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 180 181 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 182 (2 << BR_PS_SHIFT) | /* 16 bit port */ \ 183 BR_V) /* valid */ 184 #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ 185 | OR_UPM_XAM \ 186 | OR_GPCM_CSNT \ 187 | OR_GPCM_ACS_DIV2 \ 188 | OR_GPCM_XACS \ 189 | OR_GPCM_SCY_15 \ 190 | OR_GPCM_TRLX \ 191 | OR_GPCM_EHTR \ 192 | OR_GPCM_EAD) 193 /* window base at flash base */ 194 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 195 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ 196 197 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 198 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 199 200 #undef CONFIG_SYS_FLASH_CHECKSUM 201 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 202 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 203 204 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 205 206 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 207 #define CONFIG_SYS_RAMBOOT 208 #else 209 #undef CONFIG_SYS_RAMBOOT 210 #endif 211 212 /* 213 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 214 */ 215 #define CONFIG_SYS_BCSR 0xE2400000 216 /* Access window base at BCSR base */ 217 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 218 /* Access window size 32K */ 219 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E 220 /* Port-size=8bit, MSEL=GPCM */ 221 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) 222 #define CONFIG_SYS_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ 223 224 #define CONFIG_SYS_INIT_RAM_LOCK 1 225 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 226 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 227 228 #define CONFIG_SYS_GBL_DATA_OFFSET \ 229 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 230 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 231 232 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 233 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 234 235 /* 236 * Local Bus LCRR and LBCR regs 237 * LCRR: DLL bypass, Clock divider is 4 238 * External Local Bus rate is 239 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 240 */ 241 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 242 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 243 #define CONFIG_SYS_LBC_LBCR 0x00000000 244 245 /* 246 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. 247 * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM 248 */ 249 #undef CONFIG_SYS_LB_SDRAM 250 251 #ifdef CONFIG_SYS_LB_SDRAM 252 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ 253 /* 254 * Base Register 2 and Option Register 2 configure SDRAM. 255 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 256 * 257 * For BR2, need: 258 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 259 * port-size = 32-bits = BR2[19:20] = 11 260 * no parity checking = BR2[21:22] = 00 261 * SDRAM for MSEL = BR2[24:26] = 011 262 * Valid = BR[31] = 1 263 * 264 * 0 4 8 12 16 20 24 28 265 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 266 * 267 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 268 * FIXME: the top 17 bits of BR2. 269 */ 270 271 /* Port-size=32bit, MSEL=SDRAM */ 272 #define CONFIG_SYS_BR2_PRELIM 0xF0001861 273 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000 274 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 275 276 /* 277 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 278 * 279 * For OR2, need: 280 * 64MB mask for AM, OR2[0:7] = 1111 1100 281 * XAM, OR2[17:18] = 11 282 * 9 columns OR2[19-21] = 010 283 * 13 rows OR2[23-25] = 100 284 * EAD set for extra time OR[31] = 1 285 * 286 * 0 4 8 12 16 20 24 28 287 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 288 */ 289 290 #define CONFIG_SYS_OR2_PRELIM 0xFC006901 291 292 /* LB sdram refresh timer, about 6us */ 293 #define CONFIG_SYS_LBC_LSRT 0x32000000 294 /* LB refresh timer prescal, 266MHz/32 */ 295 #define CONFIG_SYS_LBC_MRTPR 0x20000000 296 297 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ 298 | LSDMR_BSMA1516 \ 299 | LSDMR_RFCR8 \ 300 | LSDMR_PRETOACT6 \ 301 | LSDMR_ACTTORW3 \ 302 | LSDMR_BL8 \ 303 | LSDMR_WRC3 \ 304 | LSDMR_CL3) 305 306 /* 307 * SDRAM Controller configuration sequence. 308 */ 309 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 310 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 311 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 312 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 313 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 314 #endif 315 316 /* 317 * Serial Port 318 */ 319 #define CONFIG_CONS_INDEX 1 320 #define CONFIG_SYS_NS16550 321 #define CONFIG_SYS_NS16550_SERIAL 322 #define CONFIG_SYS_NS16550_REG_SIZE 1 323 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 324 325 #define CONFIG_SYS_BAUDRATE_TABLE \ 326 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 327 328 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 329 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 330 331 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 332 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 333 /* Use the HUSH parser */ 334 #define CONFIG_SYS_HUSH_PARSER 335 #ifdef CONFIG_SYS_HUSH_PARSER 336 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 337 #endif 338 339 /* pass open firmware flat tree */ 340 #define CONFIG_OF_LIBFDT 1 341 #define CONFIG_OF_BOARD_SETUP 1 342 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 343 344 /* I2C */ 345 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 346 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 347 #define CONFIG_FSL_I2C 348 #define CONFIG_I2C_MULTI_BUS 349 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 350 #define CONFIG_SYS_I2C_SLAVE 0x7F 351 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 352 #define CONFIG_SYS_I2C_OFFSET 0x3000 353 #define CONFIG_SYS_I2C2_OFFSET 0x3100 354 355 /* SPI */ 356 #define CONFIG_MPC8XXX_SPI 357 #undef CONFIG_SOFT_SPI /* SPI bit-banged */ 358 359 /* GPIOs. Used as SPI chip selects */ 360 #define CONFIG_SYS_GPIO1_PRELIM 361 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ 362 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ 363 364 /* TSEC */ 365 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 366 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 367 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 368 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 369 370 /* USB */ 371 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ 372 373 /* 374 * General PCI 375 * Addresses are mapped 1-1. 376 */ 377 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 378 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 379 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 380 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 381 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 382 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 383 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 384 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 385 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 386 387 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 388 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 389 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 390 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 391 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 392 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 393 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 394 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 395 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 396 397 #if defined(CONFIG_PCI) 398 399 #define PCI_ONE_PCI1 400 #if defined(PCI_64BIT) 401 #undef PCI_ALL_PCI1 402 #undef PCI_TWO_PCI1 403 #undef PCI_ONE_PCI1 404 #endif 405 406 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 407 #define CONFIG_83XX_PCI_STREAMING 408 409 #undef CONFIG_EEPRO100 410 #undef CONFIG_TULIP 411 412 #if !defined(CONFIG_PCI_PNP) 413 #define PCI_ENET0_IOADDR 0xFIXME 414 #define PCI_ENET0_MEMADDR 0xFIXME 415 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 416 #endif 417 418 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 419 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 420 421 #endif /* CONFIG_PCI */ 422 423 /* 424 * TSEC configuration 425 */ 426 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 427 428 #if defined(CONFIG_TSEC_ENET) 429 430 #define CONFIG_GMII 1 /* MII PHY management */ 431 #define CONFIG_TSEC1 1 432 #define CONFIG_TSEC1_NAME "TSEC0" 433 #define CONFIG_TSEC2 1 434 #define CONFIG_TSEC2_NAME "TSEC1" 435 #define TSEC1_PHY_ADDR 0 436 #define TSEC2_PHY_ADDR 1 437 #define TSEC1_PHYIDX 0 438 #define TSEC2_PHYIDX 0 439 #define TSEC1_FLAGS TSEC_GIGABIT 440 #define TSEC2_FLAGS TSEC_GIGABIT 441 442 /* Options are: TSEC[0-1] */ 443 #define CONFIG_ETHPRIME "TSEC0" 444 445 #endif /* CONFIG_TSEC_ENET */ 446 447 /* 448 * Configure on-board RTC 449 */ 450 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 451 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 452 453 /* 454 * Environment 455 */ 456 #ifndef CONFIG_SYS_RAMBOOT 457 #define CONFIG_ENV_IS_IN_FLASH 1 458 #define CONFIG_ENV_ADDR \ 459 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 460 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 461 #define CONFIG_ENV_SIZE 0x2000 462 463 /* Address and size of Redundant Environment Sector */ 464 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 465 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 466 467 #else 468 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 469 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 470 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 471 #define CONFIG_ENV_SIZE 0x2000 472 #endif 473 474 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 475 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 476 477 478 /* 479 * BOOTP options 480 */ 481 #define CONFIG_BOOTP_BOOTFILESIZE 482 #define CONFIG_BOOTP_BOOTPATH 483 #define CONFIG_BOOTP_GATEWAY 484 #define CONFIG_BOOTP_HOSTNAME 485 486 487 /* 488 * Command line configuration. 489 */ 490 #include <config_cmd_default.h> 491 492 #define CONFIG_CMD_PING 493 #define CONFIG_CMD_I2C 494 #define CONFIG_CMD_DATE 495 #define CONFIG_CMD_MII 496 497 #if defined(CONFIG_PCI) 498 #define CONFIG_CMD_PCI 499 #endif 500 501 #if defined(CONFIG_SYS_RAMBOOT) 502 #undef CONFIG_CMD_SAVEENV 503 #undef CONFIG_CMD_LOADS 504 #endif 505 506 507 #undef CONFIG_WATCHDOG /* watchdog disabled */ 508 509 /* 510 * Miscellaneous configurable options 511 */ 512 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 513 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 514 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 515 516 #if defined(CONFIG_CMD_KGDB) 517 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 518 #else 519 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 520 #endif 521 522 /* Print Buffer Size */ 523 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 524 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 525 /* Boot Argument Buffer Size */ 526 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 527 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 528 529 /* 530 * For booting Linux, the board info and command line data 531 * have to be in the first 256 MB of memory, since this is 532 * the maximum mapped by the Linux kernel during initialization. 533 */ 534 /* Initial Memory map for Linux*/ 535 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 536 537 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 538 539 #if 1 /*528/264*/ 540 #define CONFIG_SYS_HRCW_LOW (\ 541 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 542 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 543 HRCWL_CSB_TO_CLKIN |\ 544 HRCWL_VCO_1X2 |\ 545 HRCWL_CORE_TO_CSB_2X1) 546 #elif 0 /*396/132*/ 547 #define CONFIG_SYS_HRCW_LOW (\ 548 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 549 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 550 HRCWL_CSB_TO_CLKIN |\ 551 HRCWL_VCO_1X4 |\ 552 HRCWL_CORE_TO_CSB_3X1) 553 #elif 0 /*264/132*/ 554 #define CONFIG_SYS_HRCW_LOW (\ 555 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 556 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 557 HRCWL_CSB_TO_CLKIN |\ 558 HRCWL_VCO_1X4 |\ 559 HRCWL_CORE_TO_CSB_2X1) 560 #elif 0 /*132/132*/ 561 #define CONFIG_SYS_HRCW_LOW (\ 562 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 563 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 564 HRCWL_CSB_TO_CLKIN |\ 565 HRCWL_VCO_1X4 |\ 566 HRCWL_CORE_TO_CSB_1X1) 567 #elif 0 /*264/264 */ 568 #define CONFIG_SYS_HRCW_LOW (\ 569 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 570 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 571 HRCWL_CSB_TO_CLKIN |\ 572 HRCWL_VCO_1X4 |\ 573 HRCWL_CORE_TO_CSB_1X1) 574 #endif 575 576 #ifdef CONFIG_PCISLAVE 577 #define CONFIG_SYS_HRCW_HIGH (\ 578 HRCWH_PCI_AGENT |\ 579 HRCWH_64_BIT_PCI |\ 580 HRCWH_PCI1_ARBITER_DISABLE |\ 581 HRCWH_PCI2_ARBITER_DISABLE |\ 582 HRCWH_CORE_ENABLE |\ 583 HRCWH_FROM_0X00000100 |\ 584 HRCWH_BOOTSEQ_DISABLE |\ 585 HRCWH_SW_WATCHDOG_DISABLE |\ 586 HRCWH_ROM_LOC_LOCAL_16BIT |\ 587 HRCWH_TSEC1M_IN_GMII |\ 588 HRCWH_TSEC2M_IN_GMII) 589 #else 590 #if defined(PCI_64BIT) 591 #define CONFIG_SYS_HRCW_HIGH (\ 592 HRCWH_PCI_HOST |\ 593 HRCWH_64_BIT_PCI |\ 594 HRCWH_PCI1_ARBITER_ENABLE |\ 595 HRCWH_PCI2_ARBITER_DISABLE |\ 596 HRCWH_CORE_ENABLE |\ 597 HRCWH_FROM_0X00000100 |\ 598 HRCWH_BOOTSEQ_DISABLE |\ 599 HRCWH_SW_WATCHDOG_DISABLE |\ 600 HRCWH_ROM_LOC_LOCAL_16BIT |\ 601 HRCWH_TSEC1M_IN_GMII |\ 602 HRCWH_TSEC2M_IN_GMII) 603 #else 604 #define CONFIG_SYS_HRCW_HIGH (\ 605 HRCWH_PCI_HOST |\ 606 HRCWH_32_BIT_PCI |\ 607 HRCWH_PCI1_ARBITER_ENABLE |\ 608 HRCWH_PCI2_ARBITER_ENABLE |\ 609 HRCWH_CORE_ENABLE |\ 610 HRCWH_FROM_0X00000100 |\ 611 HRCWH_BOOTSEQ_DISABLE |\ 612 HRCWH_SW_WATCHDOG_DISABLE |\ 613 HRCWH_ROM_LOC_LOCAL_16BIT |\ 614 HRCWH_TSEC1M_IN_GMII |\ 615 HRCWH_TSEC2M_IN_GMII) 616 #endif /* PCI_64BIT */ 617 #endif /* CONFIG_PCISLAVE */ 618 619 /* 620 * System performance 621 */ 622 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 623 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 624 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 625 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 626 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 627 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 628 629 /* System IO Config */ 630 #define CONFIG_SYS_SICRH 0 631 #define CONFIG_SYS_SICRL SICRL_LDP_A 632 633 #define CONFIG_SYS_HID0_INIT 0x000000000 634 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 635 | HID0_ENABLE_INSTRUCTION_CACHE) 636 637 /* #define CONFIG_SYS_HID0_FINAL (\ 638 HID0_ENABLE_INSTRUCTION_CACHE |\ 639 HID0_ENABLE_M_BIT |\ 640 HID0_ENABLE_ADDRESS_BROADCAST) */ 641 642 643 #define CONFIG_SYS_HID2 HID2_HBE 644 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 645 646 /* DDR @ 0x00000000 */ 647 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 648 | BATL_PP_RW \ 649 | BATL_MEMCOHERENCE) 650 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 651 | BATU_BL_256M \ 652 | BATU_VS \ 653 | BATU_VP) 654 655 /* PCI @ 0x80000000 */ 656 #ifdef CONFIG_PCI 657 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 658 | BATL_PP_RW \ 659 | BATL_MEMCOHERENCE) 660 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 661 | BATU_BL_256M \ 662 | BATU_VS \ 663 | BATU_VP) 664 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 665 | BATL_PP_RW \ 666 | BATL_CACHEINHIBIT \ 667 | BATL_GUARDEDSTORAGE) 668 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 669 | BATU_BL_256M \ 670 | BATU_VS \ 671 | BATU_VP) 672 #else 673 #define CONFIG_SYS_IBAT1L (0) 674 #define CONFIG_SYS_IBAT1U (0) 675 #define CONFIG_SYS_IBAT2L (0) 676 #define CONFIG_SYS_IBAT2U (0) 677 #endif 678 679 #ifdef CONFIG_MPC83XX_PCI2 680 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 681 | BATL_PP_RW \ 682 | BATL_MEMCOHERENCE) 683 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 684 | BATU_BL_256M \ 685 | BATU_VS \ 686 | BATU_VP) 687 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 688 | BATL_PP_RW \ 689 | BATL_CACHEINHIBIT \ 690 | BATL_GUARDEDSTORAGE) 691 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 692 | BATU_BL_256M \ 693 | BATU_VS \ 694 | BATU_VP) 695 #else 696 #define CONFIG_SYS_IBAT3L (0) 697 #define CONFIG_SYS_IBAT3U (0) 698 #define CONFIG_SYS_IBAT4L (0) 699 #define CONFIG_SYS_IBAT4U (0) 700 #endif 701 702 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 703 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 704 | BATL_PP_RW \ 705 | BATL_CACHEINHIBIT \ 706 | BATL_GUARDEDSTORAGE) 707 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 708 | BATU_BL_256M \ 709 | BATU_VS \ 710 | BATU_VP) 711 712 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 713 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 714 | BATL_PP_RW \ 715 | BATL_MEMCOHERENCE \ 716 | BATL_GUARDEDSTORAGE) 717 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 718 | BATU_BL_256M \ 719 | BATU_VS \ 720 | BATU_VP) 721 722 #define CONFIG_SYS_IBAT7L (0) 723 #define CONFIG_SYS_IBAT7U (0) 724 725 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 726 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 727 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 728 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 729 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 730 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 731 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 732 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 733 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 734 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 735 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 736 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 737 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 738 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 739 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 740 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 741 742 #if defined(CONFIG_CMD_KGDB) 743 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 744 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 745 #endif 746 747 /* 748 * Environment Configuration 749 */ 750 #define CONFIG_ENV_OVERWRITE 751 752 #if defined(CONFIG_TSEC_ENET) 753 #define CONFIG_HAS_ETH1 754 #define CONFIG_HAS_ETH0 755 #endif 756 757 #define CONFIG_HOSTNAME mpc8349emds 758 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 759 #define CONFIG_BOOTFILE "uImage" 760 761 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 762 763 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 764 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 765 766 #define CONFIG_BAUDRATE 115200 767 768 #define CONFIG_PREBOOT "echo;" \ 769 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 770 "echo" 771 772 #define CONFIG_EXTRA_ENV_SETTINGS \ 773 "netdev=eth0\0" \ 774 "hostname=mpc8349emds\0" \ 775 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 776 "nfsroot=${serverip}:${rootpath}\0" \ 777 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 778 "addip=setenv bootargs ${bootargs} " \ 779 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 780 ":${hostname}:${netdev}:off panic=1\0" \ 781 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 782 "flash_nfs=run nfsargs addip addtty;" \ 783 "bootm ${kernel_addr}\0" \ 784 "flash_self=run ramargs addip addtty;" \ 785 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 786 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 787 "bootm\0" \ 788 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 789 "update=protect off fe000000 fe03ffff; " \ 790 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ 791 "upd=run load update\0" \ 792 "fdtaddr=780000\0" \ 793 "fdtfile=mpc834x_mds.dtb\0" \ 794 "" 795 796 #define CONFIG_NFSBOOTCOMMAND \ 797 "setenv bootargs root=/dev/nfs rw " \ 798 "nfsroot=$serverip:$rootpath " \ 799 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 800 "$netdev:off " \ 801 "console=$consoledev,$baudrate $othbootargs;" \ 802 "tftp $loadaddr $bootfile;" \ 803 "tftp $fdtaddr $fdtfile;" \ 804 "bootm $loadaddr - $fdtaddr" 805 806 #define CONFIG_RAMBOOTCOMMAND \ 807 "setenv bootargs root=/dev/ram rw " \ 808 "console=$consoledev,$baudrate $othbootargs;" \ 809 "tftp $ramdiskaddr $ramdiskfile;" \ 810 "tftp $loadaddr $bootfile;" \ 811 "tftp $fdtaddr $fdtfile;" \ 812 "bootm $loadaddr $ramdiskaddr $fdtaddr" 813 814 #define CONFIG_BOOTCOMMAND "run flash_self" 815 816 #endif /* __CONFIG_H */ 817