1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 #undef DEBUG 24 25 /* 26 * High Level Configuration Options 27 */ 28 #define CONFIG_E300 1 /* E300 family */ 29 #define CONFIG_QE 1 /* Has QE */ 30 #define CONFIG_MPC83XX 1 /* MPC83xx family */ 31 #define CONFIG_MPC832X 1 /* MPC832x CPU specific */ 32 #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ 33 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ 34 #undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ 35 36 /* 37 * System Clock Setup 38 */ 39 #ifdef CONFIG_PCISLAVE 40 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 41 #else 42 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 43 #endif 44 45 #ifndef CONFIG_SYS_CLK_FREQ 46 #define CONFIG_SYS_CLK_FREQ 66000000 47 #endif 48 49 /* 50 * Hardware Reset Configuration Word 51 */ 52 #define CFG_HRCW_LOW (\ 53 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 54 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 55 HRCWL_VCO_1X2 |\ 56 HRCWL_CSB_TO_CLKIN_2X1 |\ 57 HRCWL_CORE_TO_CSB_2X1 |\ 58 HRCWL_CE_PLL_VCO_DIV_2 |\ 59 HRCWL_CE_PLL_DIV_1X1 |\ 60 HRCWL_CE_TO_PLL_1X3) 61 62 #ifdef CONFIG_PCISLAVE 63 #define CFG_HRCW_HIGH (\ 64 HRCWH_PCI_AGENT |\ 65 HRCWH_PCI1_ARBITER_DISABLE |\ 66 HRCWH_CORE_ENABLE |\ 67 HRCWH_FROM_0XFFF00100 |\ 68 HRCWH_BOOTSEQ_DISABLE |\ 69 HRCWH_SW_WATCHDOG_DISABLE |\ 70 HRCWH_ROM_LOC_LOCAL_16BIT |\ 71 HRCWH_BIG_ENDIAN |\ 72 HRCWH_LALE_NORMAL) 73 #else 74 #define CFG_HRCW_HIGH (\ 75 HRCWH_PCI_HOST |\ 76 HRCWH_PCI1_ARBITER_ENABLE |\ 77 HRCWH_CORE_ENABLE |\ 78 HRCWH_FROM_0X00000100 |\ 79 HRCWH_BOOTSEQ_DISABLE |\ 80 HRCWH_SW_WATCHDOG_DISABLE |\ 81 HRCWH_ROM_LOC_LOCAL_16BIT |\ 82 HRCWH_BIG_ENDIAN |\ 83 HRCWH_LALE_NORMAL) 84 #endif 85 86 /* 87 * System IO Config 88 */ 89 #define CFG_SICRL 0x00000000 90 91 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 92 #define CONFIG_BOARD_EARLY_INIT_R 93 94 /* 95 * IMMR new address 96 */ 97 #define CFG_IMMR 0xE0000000 98 99 /* 100 * DDR Setup 101 */ 102 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ 103 #define CFG_SDRAM_BASE CFG_DDR_BASE 104 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 105 #define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ 106 107 #undef CONFIG_SPD_EEPROM 108 #if defined(CONFIG_SPD_EEPROM) 109 /* Determine DDR configuration from I2C interface 110 */ 111 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 112 #else 113 /* Manually set up DDR parameters 114 */ 115 #define CFG_DDR_SIZE 128 /* MB */ 116 #define CFG_DDR_CS0_CONFIG 0x80840102 117 #define CFG_DDR_TIMING_0 0x00220802 118 #define CFG_DDR_TIMING_1 0x3935d322 119 #define CFG_DDR_TIMING_2 0x0f9048ca 120 #define CFG_DDR_TIMING_3 0x00000000 121 #define CFG_DDR_CLK_CNTL 0x02000000 122 #define CFG_DDR_MODE 0x44400232 123 #define CFG_DDR_MODE2 0x8000c000 124 #define CFG_DDR_INTERVAL 0x03200064 125 #define CFG_DDR_CS0_BNDS 0x00000007 126 #define CFG_DDR_SDRAM_CFG 0x43080000 127 #define CFG_DDR_SDRAM_CFG2 0x00401000 128 #endif 129 130 /* 131 * Memory test 132 */ 133 #undef CFG_DRAM_TEST /* memory test, takes time */ 134 #define CFG_MEMTEST_START 0x00000000 /* memtest region */ 135 #define CFG_MEMTEST_END 0x00100000 136 137 /* 138 * The reserved memory 139 */ 140 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 141 142 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 143 #define CFG_RAMBOOT 144 #else 145 #undef CFG_RAMBOOT 146 #endif 147 148 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 149 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 150 151 /* 152 * Initial RAM Base Address Setup 153 */ 154 #define CFG_INIT_RAM_LOCK 1 155 #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 156 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ 157 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 158 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 159 160 /* 161 * Local Bus Configuration & Clock Setup 162 */ 163 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) 164 #define CFG_LBC_LBCR 0x00000000 165 166 /* 167 * FLASH on the Local Bus 168 */ 169 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 170 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 171 #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ 172 #define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ 173 174 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 175 #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ 176 177 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ 178 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 179 BR_V) /* valid */ 180 #define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ 181 182 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 183 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 184 185 #undef CFG_FLASH_CHECKSUM 186 187 /* 188 * BCSR on the Local Bus 189 */ 190 #define CFG_BCSR 0xF8000000 191 #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ 192 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ 193 194 #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ 195 #define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ 196 197 /* 198 * SDRAM on the Local Bus 199 */ 200 #undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */ 201 202 #ifdef CFG_LB_SDRAM 203 #define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ 204 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 205 206 #define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE 207 #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ 208 209 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ 210 /* 211 * Base Register 2 and Option Register 2 configure SDRAM. 212 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 213 * 214 * For BR2, need: 215 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 216 * port size = 32-bits = BR2[19:20] = 11 217 * no parity checking = BR2[21:22] = 00 218 * SDRAM for MSEL = BR2[24:26] = 011 219 * Valid = BR[31] = 1 220 * 221 * 0 4 8 12 16 20 24 28 222 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 223 * 224 * CFG_LBC_SDRAM_BASE should be masked and OR'ed into 225 * the top 17 bits of BR2. 226 */ 227 228 #define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ 229 230 /* 231 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 232 * 233 * For OR2, need: 234 * 64MB mask for AM, OR2[0:7] = 1111 1100 235 * XAM, OR2[17:18] = 11 236 * 9 columns OR2[19-21] = 010 237 * 13 rows OR2[23-25] = 100 238 * EAD set for extra time OR[31] = 1 239 * 240 * 0 4 8 12 16 20 24 28 241 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 242 */ 243 244 #define CFG_OR2_PRELIM 0xfc006901 245 246 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 247 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 248 249 /* 250 * LSDMR masks 251 */ 252 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 253 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 254 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 255 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 256 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 257 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 258 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 259 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 260 261 #define CFG_LBC_LSDMR_COMMON 0x0063b723 262 263 /* 264 * SDRAM Controller configuration sequence. 265 */ 266 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 267 | CFG_LBC_LSDMR_OP_PCHALL) 268 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 269 | CFG_LBC_LSDMR_OP_ARFRSH) 270 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 271 | CFG_LBC_LSDMR_OP_ARFRSH) 272 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 273 | CFG_LBC_LSDMR_OP_MRW) 274 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 275 | CFG_LBC_LSDMR_OP_NORMAL) 276 277 #endif 278 279 /* 280 * Windows to access PIB via local bus 281 */ 282 #define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ 283 #define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ 284 285 /* 286 * CS2 on Local Bus, to PIB 287 */ 288 #define CFG_BR2_PRELIM 0xf8008801 /* CS2 base address at 0xf8008000 */ 289 #define CFG_OR2_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ 290 291 /* 292 * CS3 on Local Bus, to PIB 293 */ 294 #define CFG_BR3_PRELIM 0xf8010801 /* CS3 base address at 0xf8010000 */ 295 #define CFG_OR3_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ 296 297 /* 298 * Serial Port 299 */ 300 #define CONFIG_CONS_INDEX 1 301 #undef CONFIG_SERIAL_SOFTWARE_FIFO 302 #define CFG_NS16550 303 #define CFG_NS16550_SERIAL 304 #define CFG_NS16550_REG_SIZE 1 305 #define CFG_NS16550_CLK get_bus_freq(0) 306 307 #define CFG_BAUDRATE_TABLE \ 308 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 309 310 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 311 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 312 313 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 314 /* Use the HUSH parser */ 315 #define CFG_HUSH_PARSER 316 #ifdef CFG_HUSH_PARSER 317 #define CFG_PROMPT_HUSH_PS2 "> " 318 #endif 319 320 /* pass open firmware flat tree */ 321 #define CONFIG_OF_LIBFDT 1 322 #define CONFIG_OF_BOARD_SETUP 1 323 324 /* maximum size of the flat tree (8K) */ 325 #define OF_FLAT_TREE_MAX_SIZE 8192 326 327 #define OF_CPU "PowerPC,8323@0" 328 #define OF_SOC "soc8323@e0000000" 329 #define OF_QE "qe@e0100000" 330 #define OF_TBCLK (bd->bi_busfreq / 4) 331 #define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500" 332 333 /* I2C */ 334 #define CONFIG_HARD_I2C /* I2C with hardware support */ 335 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 336 #define CONFIG_FSL_I2C 337 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 338 #define CFG_I2C_SLAVE 0x7F 339 #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 340 #define CFG_I2C_OFFSET 0x3000 341 342 /* 343 * Config on-board RTC 344 */ 345 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 346 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 347 348 /* 349 * General PCI 350 * Addresses are mapped 1-1. 351 */ 352 #define CFG_PCI_MEM_BASE 0x80000000 353 #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE 354 #define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ 355 #define CFG_PCI_MMIO_BASE 0x90000000 356 #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE 357 #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ 358 #define CFG_PCI_IO_BASE 0xE0300000 359 #define CFG_PCI_IO_PHYS 0xE0300000 360 #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ 361 362 #define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE 363 #define CFG_PCI_SLV_MEM_BUS 0x00000000 364 #define CFG_PCI_SLV_MEM_SIZE 0x80000000 365 366 367 #ifdef CONFIG_PCI 368 369 #define CONFIG_NET_MULTI 370 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 371 372 #undef CONFIG_EEPRO100 373 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 374 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 375 376 #endif /* CONFIG_PCI */ 377 378 379 #ifndef CONFIG_NET_MULTI 380 #define CONFIG_NET_MULTI 1 381 #endif 382 383 /* 384 * QE UEC ethernet configuration 385 */ 386 #define CONFIG_UEC_ETH 387 #define CONFIG_ETHPRIME "Freescale GETH" 388 389 #define CONFIG_UEC_ETH1 /* ETH3 */ 390 391 #ifdef CONFIG_UEC_ETH1 392 #define CFG_UEC1_UCC_NUM 2 /* UCC3 */ 393 #define CFG_UEC1_RX_CLK QE_CLK9 394 #define CFG_UEC1_TX_CLK QE_CLK10 395 #define CFG_UEC1_ETH_TYPE FAST_ETH 396 #define CFG_UEC1_PHY_ADDR 3 397 #define CFG_UEC1_INTERFACE_MODE ENET_100_MII 398 #endif 399 400 #define CONFIG_UEC_ETH2 /* ETH4 */ 401 402 #ifdef CONFIG_UEC_ETH2 403 #define CFG_UEC2_UCC_NUM 3 /* UCC4 */ 404 #define CFG_UEC2_RX_CLK QE_CLK7 405 #define CFG_UEC2_TX_CLK QE_CLK8 406 #define CFG_UEC2_ETH_TYPE FAST_ETH 407 #define CFG_UEC2_PHY_ADDR 4 408 #define CFG_UEC2_INTERFACE_MODE ENET_100_MII 409 #endif 410 411 /* 412 * Environment 413 */ 414 #ifndef CFG_RAMBOOT 415 #define CFG_ENV_IS_IN_FLASH 1 416 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 417 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 418 #define CFG_ENV_SIZE 0x2000 419 #else 420 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 421 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 422 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 423 #define CFG_ENV_SIZE 0x2000 424 #endif 425 426 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 427 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 428 429 /* 430 * BOOTP options 431 */ 432 #define CONFIG_BOOTP_BOOTFILESIZE 433 #define CONFIG_BOOTP_BOOTPATH 434 #define CONFIG_BOOTP_GATEWAY 435 #define CONFIG_BOOTP_HOSTNAME 436 437 438 /* 439 * Command line configuration. 440 */ 441 #include <config_cmd_default.h> 442 443 #define CONFIG_CMD_PING 444 #define CONFIG_CMD_I2C 445 #define CONFIG_CMD_ASKENV 446 447 #if defined(CONFIG_PCI) 448 #define CONFIG_CMD_PCI 449 #endif 450 451 #if defined(CFG_RAMBOOT) 452 #undef CONFIG_CMD_ENV 453 #undef CONFIG_CMD_LOADS 454 #endif 455 456 457 #undef CONFIG_WATCHDOG /* watchdog disabled */ 458 459 /* 460 * Miscellaneous configurable options 461 */ 462 #define CFG_LONGHELP /* undef to save memory */ 463 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 464 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 465 466 #if defined(CONFIG_CMD_KGDB) 467 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 468 #else 469 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 470 #endif 471 472 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 473 #define CFG_MAXARGS 16 /* max number of command args */ 474 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 475 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 476 477 /* 478 * For booting Linux, the board info and command line data 479 * have to be in the first 8 MB of memory, since this is 480 * the maximum mapped by the Linux kernel during initialization. 481 */ 482 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 483 484 /* 485 * Core HID Setup 486 */ 487 #define CFG_HID0_INIT 0x000000000 488 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 489 #define CFG_HID2 HID2_HBE 490 491 /* 492 * Cache Config 493 */ 494 #define CFG_DCACHE_SIZE 16384 495 #define CFG_CACHELINE_SIZE 32 496 #if defined(CONFIG_CMD_KGDB) 497 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ 498 #endif 499 500 /* 501 * MMU Setup 502 */ 503 504 /* DDR: cache cacheable */ 505 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 506 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 507 #define CFG_DBAT0L CFG_IBAT0L 508 #define CFG_DBAT0U CFG_IBAT0U 509 510 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 511 #define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ 512 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 513 #define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) 514 #define CFG_DBAT1L CFG_IBAT1L 515 #define CFG_DBAT1U CFG_IBAT1U 516 517 /* BCSR: cache-inhibit and guarded */ 518 #define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \ 519 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 520 #define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) 521 #define CFG_DBAT2L CFG_IBAT2L 522 #define CFG_DBAT2U CFG_IBAT2U 523 524 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 525 #define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 526 #define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 527 #define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ 528 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 529 #define CFG_DBAT3U CFG_IBAT3U 530 531 #define CFG_IBAT4L (0) 532 #define CFG_IBAT4U (0) 533 #define CFG_DBAT4L CFG_IBAT4L 534 #define CFG_DBAT4U CFG_IBAT4U 535 536 /* Stack in dcache: cacheable, no memory coherence */ 537 #define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) 538 #define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 539 #define CFG_DBAT5L CFG_IBAT5L 540 #define CFG_DBAT5U CFG_IBAT5U 541 542 #ifdef CONFIG_PCI 543 /* PCI MEM space: cacheable */ 544 #define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 545 #define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 546 #define CFG_DBAT6L CFG_IBAT6L 547 #define CFG_DBAT6U CFG_IBAT6U 548 /* PCI MMIO space: cache-inhibit and guarded */ 549 #define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ 550 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 551 #define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 552 #define CFG_DBAT7L CFG_IBAT7L 553 #define CFG_DBAT7U CFG_IBAT7U 554 #else 555 #define CFG_IBAT6L (0) 556 #define CFG_IBAT6U (0) 557 #define CFG_IBAT7L (0) 558 #define CFG_IBAT7U (0) 559 #define CFG_DBAT6L CFG_IBAT6L 560 #define CFG_DBAT6U CFG_IBAT6U 561 #define CFG_DBAT7L CFG_IBAT7L 562 #define CFG_DBAT7U CFG_IBAT7U 563 #endif 564 565 /* 566 * Internal Definitions 567 * 568 * Boot Flags 569 */ 570 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 571 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 572 573 #if defined(CONFIG_CMD_KGDB) 574 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 575 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 576 #endif 577 578 /* 579 * Environment Configuration 580 */ 581 582 #define CONFIG_ENV_OVERWRITE 583 584 #if defined(CONFIG_UEC_ETH) 585 #define CONFIG_ETHADDR 00:04:9f:ef:03:01 586 #define CONFIG_HAS_ETH1 587 #define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 588 #endif 589 590 #define CONFIG_BAUDRATE 115200 591 592 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 593 594 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 595 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 596 597 #define CONFIG_EXTRA_ENV_SETTINGS \ 598 "netdev=eth0\0" \ 599 "consoledev=ttyS0\0" \ 600 "ramdiskaddr=1000000\0" \ 601 "ramdiskfile=ramfs.83xx\0" \ 602 "fdtaddr=400000\0" \ 603 "fdtfile=mpc832xemds.dtb\0" \ 604 "" 605 606 #define CONFIG_NFSBOOTCOMMAND \ 607 "setenv bootargs root=/dev/nfs rw " \ 608 "nfsroot=$serverip:$rootpath " \ 609 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 610 "console=$consoledev,$baudrate $othbootargs;" \ 611 "tftp $loadaddr $bootfile;" \ 612 "tftp $fdtaddr $fdtfile;" \ 613 "bootm $loadaddr - $fdtaddr" 614 615 #define CONFIG_RAMBOOTCOMMAND \ 616 "setenv bootargs root=/dev/ram rw " \ 617 "console=$consoledev,$baudrate $othbootargs;" \ 618 "tftp $ramdiskaddr $ramdiskfile;" \ 619 "tftp $loadaddr $bootfile;" \ 620 "tftp $fdtaddr $fdtfile;" \ 621 "bootm $loadaddr $ramdiskaddr $fdtaddr" 622 623 624 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 625 626 #endif /* __CONFIG_H */ 627