1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* 24 * High Level Configuration Options 25 */ 26 #define CONFIG_E300 1 /* E300 family */ 27 #define CONFIG_QE 1 /* Has QE */ 28 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 29 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ 30 #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ 31 32 #define CONFIG_SYS_TEXT_BASE 0xFE000000 33 34 /* 35 * System Clock Setup 36 */ 37 #ifdef CONFIG_PCISLAVE 38 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 39 #else 40 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 41 #endif 42 43 #ifndef CONFIG_SYS_CLK_FREQ 44 #define CONFIG_SYS_CLK_FREQ 66000000 45 #endif 46 47 /* 48 * Hardware Reset Configuration Word 49 */ 50 #define CONFIG_SYS_HRCW_LOW (\ 51 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 52 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 53 HRCWL_VCO_1X2 |\ 54 HRCWL_CSB_TO_CLKIN_2X1 |\ 55 HRCWL_CORE_TO_CSB_2X1 |\ 56 HRCWL_CE_PLL_VCO_DIV_2 |\ 57 HRCWL_CE_PLL_DIV_1X1 |\ 58 HRCWL_CE_TO_PLL_1X3) 59 60 #ifdef CONFIG_PCISLAVE 61 #define CONFIG_SYS_HRCW_HIGH (\ 62 HRCWH_PCI_AGENT |\ 63 HRCWH_PCI1_ARBITER_DISABLE |\ 64 HRCWH_CORE_ENABLE |\ 65 HRCWH_FROM_0XFFF00100 |\ 66 HRCWH_BOOTSEQ_DISABLE |\ 67 HRCWH_SW_WATCHDOG_DISABLE |\ 68 HRCWH_ROM_LOC_LOCAL_16BIT |\ 69 HRCWH_BIG_ENDIAN |\ 70 HRCWH_LALE_NORMAL) 71 #else 72 #define CONFIG_SYS_HRCW_HIGH (\ 73 HRCWH_PCI_HOST |\ 74 HRCWH_PCI1_ARBITER_ENABLE |\ 75 HRCWH_CORE_ENABLE |\ 76 HRCWH_FROM_0X00000100 |\ 77 HRCWH_BOOTSEQ_DISABLE |\ 78 HRCWH_SW_WATCHDOG_DISABLE |\ 79 HRCWH_ROM_LOC_LOCAL_16BIT |\ 80 HRCWH_BIG_ENDIAN |\ 81 HRCWH_LALE_NORMAL) 82 #endif 83 84 /* 85 * System IO Config 86 */ 87 #define CONFIG_SYS_SICRL 0x00000000 88 89 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 90 #define CONFIG_BOARD_EARLY_INIT_R 91 92 /* 93 * IMMR new address 94 */ 95 #define CONFIG_SYS_IMMR 0xE0000000 96 97 /* 98 * DDR Setup 99 */ 100 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 101 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 102 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 103 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ 104 105 #undef CONFIG_SPD_EEPROM 106 #if defined(CONFIG_SPD_EEPROM) 107 /* Determine DDR configuration from I2C interface 108 */ 109 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 110 #else 111 /* Manually set up DDR parameters 112 */ 113 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 114 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80840102 115 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 116 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 117 #define CONFIG_SYS_DDR_TIMING_2 0x0f9048ca 118 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 119 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 120 #define CONFIG_SYS_DDR_MODE 0x44400232 121 #define CONFIG_SYS_DDR_MODE2 0x8000c000 122 #define CONFIG_SYS_DDR_INTERVAL 0x03200064 123 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 124 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000 125 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 126 #endif 127 128 /* 129 * Memory test 130 */ 131 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 132 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 133 #define CONFIG_SYS_MEMTEST_END 0x00100000 134 135 /* 136 * The reserved memory 137 */ 138 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 139 140 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 141 #define CONFIG_SYS_RAMBOOT 142 #else 143 #undef CONFIG_SYS_RAMBOOT 144 #endif 145 146 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 147 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 148 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 149 150 /* 151 * Initial RAM Base Address Setup 152 */ 153 #define CONFIG_SYS_INIT_RAM_LOCK 1 154 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */ 155 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 156 #define CONFIG_SYS_GBL_DATA_OFFSET \ 157 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 158 159 /* 160 * Local Bus Configuration & Clock Setup 161 */ 162 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 163 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 164 #define CONFIG_SYS_LBC_LBCR 0x00000000 165 166 /* 167 * FLASH on the Local Bus 168 */ 169 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 170 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 171 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 172 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ 173 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 174 175 /* Window base at flash base */ 176 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 177 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ 178 179 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 180 | (2 << BR_PS_SHIFT) /* 16 bit port */ \ 181 | BR_V) /* valid */ 182 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ 183 184 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 185 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 186 187 #undef CONFIG_SYS_FLASH_CHECKSUM 188 189 /* 190 * BCSR on the Local Bus 191 */ 192 #define CONFIG_SYS_BCSR 0xF8000000 193 /* Access window base at BCSR base */ 194 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 195 /* Access window size 32K */ 196 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E 197 198 /* Port size=8bit, MSEL=GPCM */ 199 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) 200 #define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ 201 202 /* 203 * SDRAM on the Local Bus 204 */ 205 #undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */ 206 207 #ifdef CONFIG_SYS_LB_SDRAM 208 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ 209 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 210 211 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 212 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ 213 214 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ 215 /* 216 * Base Register 2 and Option Register 2 configure SDRAM. 217 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 218 * 219 * For BR2, need: 220 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 221 * port size = 32-bits = BR2[19:20] = 11 222 * no parity checking = BR2[21:22] = 00 223 * SDRAM for MSEL = BR2[24:26] = 011 224 * Valid = BR[31] = 1 225 * 226 * 0 4 8 12 16 20 24 28 227 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 228 * 229 * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 230 * the top 17 bits of BR2. 231 */ 232 233 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ 234 235 /* 236 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 237 * 238 * For OR2, need: 239 * 64MB mask for AM, OR2[0:7] = 1111 1100 240 * XAM, OR2[17:18] = 11 241 * 9 columns OR2[19-21] = 010 242 * 13 rows OR2[23-25] = 100 243 * EAD set for extra time OR[31] = 1 244 * 245 * 0 4 8 12 16 20 24 28 246 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 247 */ 248 249 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 250 251 /* LB sdram refresh timer, about 6us */ 252 #define CONFIG_SYS_LBC_LSRT 0x32000000 253 /* LB refresh timer prescal, 266MHz/32 */ 254 #define CONFIG_SYS_LBC_MRTPR 0x20000000 255 256 #define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 257 258 #endif 259 260 /* 261 * Windows to access PIB via local bus 262 */ 263 /* windows base 0xf8008000 */ 264 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 265 /* windows size 64KB */ 266 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f 267 268 /* 269 * CS2 on Local Bus, to PIB 270 */ 271 /* CS2 base address at 0xf8008000 */ 272 #define CONFIG_SYS_BR2_PRELIM 0xf8008801 273 /* size 32KB, port size 8bit, GPCM */ 274 #define CONFIG_SYS_OR2_PRELIM 0xffffe9f7 275 276 /* 277 * CS3 on Local Bus, to PIB 278 */ 279 /* CS3 base address at 0xf8010000 */ 280 #define CONFIG_SYS_BR3_PRELIM 0xf8010801 281 /* size 32KB, port size 8bit, GPCM */ 282 #define CONFIG_SYS_OR3_PRELIM 0xffffe9f7 283 284 /* 285 * Serial Port 286 */ 287 #define CONFIG_CONS_INDEX 1 288 #define CONFIG_SYS_NS16550 289 #define CONFIG_SYS_NS16550_SERIAL 290 #define CONFIG_SYS_NS16550_REG_SIZE 1 291 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 292 293 #define CONFIG_SYS_BAUDRATE_TABLE \ 294 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 295 296 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 297 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 298 299 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 300 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 301 /* Use the HUSH parser */ 302 #define CONFIG_SYS_HUSH_PARSER 303 #ifdef CONFIG_SYS_HUSH_PARSER 304 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 305 #endif 306 307 /* pass open firmware flat tree */ 308 #define CONFIG_OF_LIBFDT 1 309 #define CONFIG_OF_BOARD_SETUP 1 310 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 311 312 /* I2C */ 313 #define CONFIG_HARD_I2C /* I2C with hardware support */ 314 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 315 #define CONFIG_FSL_I2C 316 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 317 #define CONFIG_SYS_I2C_SLAVE 0x7F 318 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 319 #define CONFIG_SYS_I2C_OFFSET 0x3000 320 321 /* 322 * Config on-board RTC 323 */ 324 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 325 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 326 327 /* 328 * General PCI 329 * Addresses are mapped 1-1. 330 */ 331 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 332 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 333 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 334 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 335 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 336 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 337 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 338 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 339 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 340 341 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 342 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 343 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 344 345 346 #ifdef CONFIG_PCI 347 348 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 349 #define CONFIG_83XX_PCI_STREAMING 350 351 #undef CONFIG_EEPRO100 352 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 353 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 354 355 #endif /* CONFIG_PCI */ 356 357 /* 358 * QE UEC ethernet configuration 359 */ 360 #define CONFIG_UEC_ETH 361 #define CONFIG_ETHPRIME "UEC0" 362 363 #define CONFIG_UEC_ETH1 /* ETH3 */ 364 365 #ifdef CONFIG_UEC_ETH1 366 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ 367 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 368 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 369 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 370 #define CONFIG_SYS_UEC1_PHY_ADDR 3 371 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 372 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 373 #endif 374 375 #define CONFIG_UEC_ETH2 /* ETH4 */ 376 377 #ifdef CONFIG_UEC_ETH2 378 #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */ 379 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7 380 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8 381 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 382 #define CONFIG_SYS_UEC2_PHY_ADDR 4 383 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 384 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 385 #endif 386 387 /* 388 * Environment 389 */ 390 #ifndef CONFIG_SYS_RAMBOOT 391 #define CONFIG_ENV_IS_IN_FLASH 1 392 #define CONFIG_ENV_ADDR \ 393 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 394 #define CONFIG_ENV_SECT_SIZE 0x20000 395 #define CONFIG_ENV_SIZE 0x2000 396 #else 397 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 398 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 399 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 400 #define CONFIG_ENV_SIZE 0x2000 401 #endif 402 403 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 404 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 405 406 /* 407 * BOOTP options 408 */ 409 #define CONFIG_BOOTP_BOOTFILESIZE 410 #define CONFIG_BOOTP_BOOTPATH 411 #define CONFIG_BOOTP_GATEWAY 412 #define CONFIG_BOOTP_HOSTNAME 413 414 415 /* 416 * Command line configuration. 417 */ 418 #include <config_cmd_default.h> 419 420 #define CONFIG_CMD_PING 421 #define CONFIG_CMD_I2C 422 #define CONFIG_CMD_ASKENV 423 424 #if defined(CONFIG_PCI) 425 #define CONFIG_CMD_PCI 426 #endif 427 428 #if defined(CONFIG_SYS_RAMBOOT) 429 #undef CONFIG_CMD_SAVEENV 430 #undef CONFIG_CMD_LOADS 431 #endif 432 433 434 #undef CONFIG_WATCHDOG /* watchdog disabled */ 435 436 /* 437 * Miscellaneous configurable options 438 */ 439 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 440 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 441 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 442 443 #if defined(CONFIG_CMD_KGDB) 444 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 445 #else 446 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 447 #endif 448 449 /* Print Buffer Size */ 450 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 451 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 452 /* Boot Argument Buffer Size */ 453 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 454 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 455 456 /* 457 * For booting Linux, the board info and command line data 458 * have to be in the first 256 MB of memory, since this is 459 * the maximum mapped by the Linux kernel during initialization. 460 */ 461 /* Initial Memory map for Linux */ 462 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 463 464 /* 465 * Core HID Setup 466 */ 467 #define CONFIG_SYS_HID0_INIT 0x000000000 468 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 469 HID0_ENABLE_INSTRUCTION_CACHE) 470 #define CONFIG_SYS_HID2 HID2_HBE 471 472 /* 473 * MMU Setup 474 */ 475 476 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 477 478 /* DDR: cache cacheable */ 479 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 480 | BATL_PP_10 \ 481 | BATL_MEMCOHERENCE) 482 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 483 | BATU_BL_256M \ 484 | BATU_VS \ 485 | BATU_VP) 486 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 487 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 488 489 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 490 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ 491 | BATL_PP_10 \ 492 | BATL_CACHEINHIBIT \ 493 | BATL_GUARDEDSTORAGE) 494 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ 495 | BATU_BL_4M \ 496 | BATU_VS \ 497 | BATU_VP) 498 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 499 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 500 501 /* BCSR: cache-inhibit and guarded */ 502 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ 503 | BATL_PP_10 \ 504 | BATL_CACHEINHIBIT \ 505 | BATL_GUARDEDSTORAGE) 506 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ 507 | BATU_BL_128K \ 508 | BATU_VS \ 509 | BATU_VP) 510 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 511 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 512 513 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 514 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ 515 | BATL_PP_10 \ 516 | BATL_MEMCOHERENCE) 517 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ 518 | BATU_BL_32M \ 519 | BATU_VS \ 520 | BATU_VP) 521 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ 522 | BATL_PP_10 \ 523 | BATL_CACHEINHIBIT \ 524 | BATL_GUARDEDSTORAGE) 525 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 526 527 #define CONFIG_SYS_IBAT4L (0) 528 #define CONFIG_SYS_IBAT4U (0) 529 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 530 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 531 532 /* Stack in dcache: cacheable, no memory coherence */ 533 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) 534 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 535 | BATU_BL_128K \ 536 | BATU_VS \ 537 | BATU_VP) 538 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 539 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 540 541 #ifdef CONFIG_PCI 542 /* PCI MEM space: cacheable */ 543 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ 544 | BATL_PP_10 \ 545 | BATL_MEMCOHERENCE) 546 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ 547 | BATU_BL_256M \ 548 | BATU_VS \ 549 | BATU_VP) 550 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 551 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 552 /* PCI MMIO space: cache-inhibit and guarded */ 553 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ 554 | BATL_PP_10 \ 555 | BATL_CACHEINHIBIT \ 556 | BATL_GUARDEDSTORAGE) 557 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ 558 | BATU_BL_256M \ 559 | BATU_VS \ 560 | BATU_VP) 561 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 562 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 563 #else 564 #define CONFIG_SYS_IBAT6L (0) 565 #define CONFIG_SYS_IBAT6U (0) 566 #define CONFIG_SYS_IBAT7L (0) 567 #define CONFIG_SYS_IBAT7U (0) 568 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 569 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 570 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 571 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 572 #endif 573 574 #if defined(CONFIG_CMD_KGDB) 575 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 576 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 577 #endif 578 579 /* 580 * Environment Configuration 581 */ #define CONFIG_ENV_OVERWRITE 582 583 #if defined(CONFIG_UEC_ETH) 584 #define CONFIG_HAS_ETH0 585 #define CONFIG_HAS_ETH1 586 #endif 587 588 #define CONFIG_BAUDRATE 115200 589 590 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 591 592 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 593 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 594 595 #define CONFIG_EXTRA_ENV_SETTINGS \ 596 "netdev=eth0\0" \ 597 "consoledev=ttyS0\0" \ 598 "ramdiskaddr=1000000\0" \ 599 "ramdiskfile=ramfs.83xx\0" \ 600 "fdtaddr=780000\0" \ 601 "fdtfile=mpc832x_mds.dtb\0" \ 602 "" 603 604 #define CONFIG_NFSBOOTCOMMAND \ 605 "setenv bootargs root=/dev/nfs rw " \ 606 "nfsroot=$serverip:$rootpath " \ 607 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 608 "$netdev:off " \ 609 "console=$consoledev,$baudrate $othbootargs;" \ 610 "tftp $loadaddr $bootfile;" \ 611 "tftp $fdtaddr $fdtfile;" \ 612 "bootm $loadaddr - $fdtaddr" 613 614 #define CONFIG_RAMBOOTCOMMAND \ 615 "setenv bootargs root=/dev/ram rw " \ 616 "console=$consoledev,$baudrate $othbootargs;" \ 617 "tftp $ramdiskaddr $ramdiskfile;" \ 618 "tftp $loadaddr $bootfile;" \ 619 "tftp $fdtaddr $fdtfile;" \ 620 "bootm $loadaddr $ramdiskaddr $fdtaddr" 621 622 623 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 624 625 #endif /* __CONFIG_H */ 626