1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published 6 * by the Free Software Foundation. 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_QE 1 /* Has QE */ 17 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 18 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ 19 20 #define CONFIG_SYS_TEXT_BASE 0xFE000000 21 22 #define CONFIG_PCI 1 23 24 /* 25 * System Clock Setup 26 */ 27 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 28 29 #ifndef CONFIG_SYS_CLK_FREQ 30 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 31 #endif 32 33 /* 34 * Hardware Reset Configuration Word 35 */ 36 #define CONFIG_SYS_HRCW_LOW (\ 37 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 38 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 39 HRCWL_VCO_1X2 |\ 40 HRCWL_CSB_TO_CLKIN_2X1 |\ 41 HRCWL_CORE_TO_CSB_2_5X1 |\ 42 HRCWL_CE_PLL_VCO_DIV_2 |\ 43 HRCWL_CE_PLL_DIV_1X1 |\ 44 HRCWL_CE_TO_PLL_1X3) 45 46 #define CONFIG_SYS_HRCW_HIGH (\ 47 HRCWH_PCI_HOST |\ 48 HRCWH_PCI1_ARBITER_ENABLE |\ 49 HRCWH_CORE_ENABLE |\ 50 HRCWH_FROM_0X00000100 |\ 51 HRCWH_BOOTSEQ_DISABLE |\ 52 HRCWH_SW_WATCHDOG_DISABLE |\ 53 HRCWH_ROM_LOC_LOCAL_16BIT |\ 54 HRCWH_BIG_ENDIAN |\ 55 HRCWH_LALE_NORMAL) 56 57 /* 58 * System IO Config 59 */ 60 #define CONFIG_SYS_SICRL 0x00000000 61 62 /* 63 * IMMR new address 64 */ 65 #define CONFIG_SYS_IMMR 0xE0000000 66 67 /* 68 * System performance 69 */ 70 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 71 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 72 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ 73 #define CONFIG_SYS_SPCR_OPT 1 74 75 /* 76 * DDR Setup 77 */ 78 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 79 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 80 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 81 82 #undef CONFIG_SPD_EEPROM 83 #if defined(CONFIG_SPD_EEPROM) 84 /* Determine DDR configuration from I2C interface 85 */ 86 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 87 #else 88 /* Manually set up DDR parameters 89 */ 90 #define CONFIG_SYS_DDR_SIZE 64 /* MB */ 91 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 92 | CSCONFIG_ROW_BIT_13 \ 93 | CSCONFIG_COL_BIT_9) 94 /* 0x80010101 */ 95 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 96 | (0 << TIMING_CFG0_WRT_SHIFT) \ 97 | (0 << TIMING_CFG0_RRT_SHIFT) \ 98 | (0 << TIMING_CFG0_WWT_SHIFT) \ 99 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 100 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 101 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 102 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 103 /* 0x00220802 */ 104 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 105 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 106 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 107 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 108 | (3 << TIMING_CFG1_REFREC_SHIFT) \ 109 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 110 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 111 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 112 /* 0x26253222 */ 113 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 114 | (31 << TIMING_CFG2_CPO_SHIFT) \ 115 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 116 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 117 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 118 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 119 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) 120 /* 0x1f9048c7 */ 121 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 122 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 123 /* 0x02000000 */ 124 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 125 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 126 /* 0x44480232 */ 127 #define CONFIG_SYS_DDR_MODE2 0x8000c000 128 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ 129 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 130 /* 0x03200064 */ 131 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003 132 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 133 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 134 | SDRAM_CFG_32_BE) 135 /* 0x43080000 */ 136 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 137 #endif 138 139 /* 140 * Memory test 141 */ 142 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 143 #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */ 144 #define CONFIG_SYS_MEMTEST_END 0x03f00000 145 146 /* 147 * The reserved memory 148 */ 149 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 150 151 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 152 #define CONFIG_SYS_RAMBOOT 153 #else 154 #undef CONFIG_SYS_RAMBOOT 155 #endif 156 157 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 158 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 159 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 160 161 /* 162 * Initial RAM Base Address Setup 163 */ 164 #define CONFIG_SYS_INIT_RAM_LOCK 1 165 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 166 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 167 #define CONFIG_SYS_GBL_DATA_OFFSET \ 168 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 169 170 /* 171 * Local Bus Configuration & Clock Setup 172 */ 173 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 174 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 175 #define CONFIG_SYS_LBC_LBCR 0x00000000 176 177 /* 178 * FLASH on the Local Bus 179 */ 180 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 181 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 182 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 183 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ 184 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 185 186 /* Window base at flash base */ 187 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 188 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ 189 190 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 191 | (2 << BR_PS_SHIFT) /* 16 bit port */ \ 192 | BR_V) /* valid */ 193 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ 194 195 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 196 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 197 198 #undef CONFIG_SYS_FLASH_CHECKSUM 199 200 /* 201 * SDRAM on the Local Bus 202 */ 203 #undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */ 204 205 #ifdef CONFIG_SYS_LB_SDRAM 206 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base addr */ 207 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 208 209 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 210 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ 211 212 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ 213 /* 214 * Base Register 2 and Option Register 2 configure SDRAM. 215 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 216 * 217 * For BR2, need: 218 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 219 * port size = 32-bits = BR2[19:20] = 11 220 * no parity checking = BR2[21:22] = 00 221 * SDRAM for MSEL = BR2[24:26] = 011 222 * Valid = BR[31] = 1 223 * 224 * 0 4 8 12 16 20 24 28 225 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 226 * 227 * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 228 * the top 17 bits of BR2. 229 */ 230 231 /*Port size=32bit, MSEL=SDRAM */ 232 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 233 234 /* 235 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 236 * 237 * For OR2, need: 238 * 64MB mask for AM, OR2[0:7] = 1111 1100 239 * XAM, OR2[17:18] = 11 240 * 9 columns OR2[19-21] = 010 241 * 13 rows OR2[23-25] = 100 242 * EAD set for extra time OR[31] = 1 243 * 244 * 0 4 8 12 16 20 24 28 245 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 246 */ 247 248 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 249 250 /* LB sdram refresh timer, about 6us */ 251 #define CONFIG_SYS_LBC_LSRT 0x32000000 252 /* LB refresh timer prescal, 266MHz/32 */ 253 #define CONFIG_SYS_LBC_MRTPR 0x20000000 254 255 #define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 256 257 #endif 258 259 /* 260 * Windows to access PIB via local bus 261 */ 262 /* windows base 0xf8008000 */ 263 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 264 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ 265 266 /* 267 * Serial Port 268 */ 269 #define CONFIG_CONS_INDEX 1 270 #define CONFIG_SYS_NS16550 271 #define CONFIG_SYS_NS16550_SERIAL 272 #define CONFIG_SYS_NS16550_REG_SIZE 1 273 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 274 275 #define CONFIG_SYS_BAUDRATE_TABLE \ 276 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 277 278 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 279 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 280 281 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 282 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 283 /* Use the HUSH parser */ 284 #define CONFIG_SYS_HUSH_PARSER 285 #ifdef CONFIG_SYS_HUSH_PARSER 286 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 287 #endif 288 289 /* pass open firmware flat tree */ 290 #define CONFIG_OF_LIBFDT 1 291 #define CONFIG_OF_BOARD_SETUP 1 292 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 293 294 /* I2C */ 295 #define CONFIG_HARD_I2C /* I2C with hardware support */ 296 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 297 #define CONFIG_FSL_I2C 298 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 299 #define CONFIG_SYS_I2C_SLAVE 0x7F 300 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 301 #define CONFIG_SYS_I2C_OFFSET 0x3000 302 303 /* 304 * Config on-board EEPROM 305 */ 306 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 307 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 308 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 309 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 310 311 /* 312 * General PCI 313 * Addresses are mapped 1-1. 314 */ 315 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 316 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 317 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 318 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 319 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 320 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 321 #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000 322 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 323 #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */ 324 325 #ifdef CONFIG_PCI 326 #define CONFIG_PCI_SKIP_HOST_BRIDGE 327 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 328 329 #undef CONFIG_EEPRO100 330 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 331 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 332 333 #endif /* CONFIG_PCI */ 334 335 /* 336 * QE UEC ethernet configuration 337 */ 338 #define CONFIG_UEC_ETH 339 #define CONFIG_ETHPRIME "UEC0" 340 341 #define CONFIG_UEC_ETH1 /* ETH3 */ 342 343 #ifdef CONFIG_UEC_ETH1 344 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ 345 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 346 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 347 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 348 #define CONFIG_SYS_UEC1_PHY_ADDR 4 349 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 350 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 351 #endif 352 353 #define CONFIG_UEC_ETH2 /* ETH4 */ 354 355 #ifdef CONFIG_UEC_ETH2 356 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 357 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16 358 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 359 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 360 #define CONFIG_SYS_UEC2_PHY_ADDR 0 361 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 362 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 363 #endif 364 365 /* 366 * Environment 367 */ 368 #ifndef CONFIG_SYS_RAMBOOT 369 #define CONFIG_ENV_IS_IN_FLASH 1 370 #define CONFIG_ENV_ADDR \ 371 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 372 #define CONFIG_ENV_SECT_SIZE 0x20000 373 #define CONFIG_ENV_SIZE 0x2000 374 #else 375 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 376 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 377 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 378 #define CONFIG_ENV_SIZE 0x2000 379 #endif 380 381 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 382 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 383 384 /* 385 * BOOTP options 386 */ 387 #define CONFIG_BOOTP_BOOTFILESIZE 388 #define CONFIG_BOOTP_BOOTPATH 389 #define CONFIG_BOOTP_GATEWAY 390 #define CONFIG_BOOTP_HOSTNAME 391 392 /* 393 * Command line configuration. 394 */ 395 #include <config_cmd_default.h> 396 397 #define CONFIG_CMD_PING 398 #define CONFIG_CMD_I2C 399 #define CONFIG_CMD_EEPROM 400 #define CONFIG_CMD_ASKENV 401 402 #if defined(CONFIG_PCI) 403 #define CONFIG_CMD_PCI 404 #endif 405 #if defined(CONFIG_SYS_RAMBOOT) 406 #undef CONFIG_CMD_SAVEENV 407 #undef CONFIG_CMD_LOADS 408 #endif 409 410 #undef CONFIG_WATCHDOG /* watchdog disabled */ 411 412 /* 413 * Miscellaneous configurable options 414 */ 415 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 416 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 417 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 418 419 #if (CONFIG_CMD_KGDB) 420 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 421 #else 422 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 423 #endif 424 425 /* Print Buffer Size */ 426 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 427 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 428 /* Boot Argument Buffer Size */ 429 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 430 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 431 432 /* 433 * For booting Linux, the board info and command line data 434 * have to be in the first 256 MB of memory, since this is 435 * the maximum mapped by the Linux kernel during initialization. 436 */ 437 /* Initial Memory map for Linux */ 438 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 439 440 /* 441 * Core HID Setup 442 */ 443 #define CONFIG_SYS_HID0_INIT 0x000000000 444 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 445 HID0_ENABLE_INSTRUCTION_CACHE) 446 #define CONFIG_SYS_HID2 HID2_HBE 447 448 /* 449 * MMU Setup 450 */ 451 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 452 453 /* DDR: cache cacheable */ 454 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 455 | BATL_PP_RW \ 456 | BATL_MEMCOHERENCE) 457 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 458 | BATU_BL_256M \ 459 | BATU_VS \ 460 | BATU_VP) 461 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 462 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 463 464 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 465 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ 466 | BATL_PP_RW \ 467 | BATL_CACHEINHIBIT \ 468 | BATL_GUARDEDSTORAGE) 469 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ 470 | BATU_BL_4M \ 471 | BATU_VS \ 472 | BATU_VP) 473 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 474 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 475 476 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 477 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ 478 | BATL_PP_RW \ 479 | BATL_MEMCOHERENCE) 480 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ 481 | BATU_BL_32M \ 482 | BATU_VS \ 483 | BATU_VP) 484 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ 485 | BATL_PP_RW \ 486 | BATL_CACHEINHIBIT \ 487 | BATL_GUARDEDSTORAGE) 488 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 489 490 #define CONFIG_SYS_IBAT3L (0) 491 #define CONFIG_SYS_IBAT3U (0) 492 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 493 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 494 495 /* Stack in dcache: cacheable, no memory coherence */ 496 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 497 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ 498 | BATU_BL_128K \ 499 | BATU_VS \ 500 | BATU_VP) 501 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 502 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 503 504 #ifdef CONFIG_PCI 505 /* PCI MEM space: cacheable */ 506 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \ 507 | BATL_PP_RW \ 508 | BATL_MEMCOHERENCE) 509 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \ 510 | BATU_BL_256M \ 511 | BATU_VS \ 512 | BATU_VP) 513 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 514 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 515 /* PCI MMIO space: cache-inhibit and guarded */ 516 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \ 517 | BATL_PP_RW \ 518 | BATL_CACHEINHIBIT \ 519 | BATL_GUARDEDSTORAGE) 520 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \ 521 | BATU_BL_256M \ 522 | BATU_VS \ 523 | BATU_VP) 524 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 525 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 526 #else 527 #define CONFIG_SYS_IBAT5L (0) 528 #define CONFIG_SYS_IBAT5U (0) 529 #define CONFIG_SYS_IBAT6L (0) 530 #define CONFIG_SYS_IBAT6U (0) 531 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 532 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 533 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 534 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 535 #endif 536 537 /* Nothing in BAT7 */ 538 #define CONFIG_SYS_IBAT7L (0) 539 #define CONFIG_SYS_IBAT7U (0) 540 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 541 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 542 543 #if (CONFIG_CMD_KGDB) 544 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 545 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 546 #endif 547 548 /* 549 * Environment Configuration 550 */ 551 #define CONFIG_ENV_OVERWRITE 552 553 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ 554 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ 555 556 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM 557 * (see CONFIG_SYS_I2C_EEPROM) */ 558 /* MAC address offset in I2C EEPROM */ 559 #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 560 561 #define CONFIG_NETDEV "eth1" 562 563 #define CONFIG_HOSTNAME mpc8323erdb 564 #define CONFIG_ROOTPATH "/nfsroot" 565 #define CONFIG_BOOTFILE "uImage" 566 /* U-Boot image on TFTP server */ 567 #define CONFIG_UBOOTPATH "u-boot.bin" 568 #define CONFIG_FDTFILE "mpc832x_rdb.dtb" 569 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" 570 571 /* default location for tftp and bootm */ 572 #define CONFIG_LOADADDR 800000 573 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 574 #define CONFIG_BAUDRATE 115200 575 576 #define XMK_STR(x) #x 577 #define MK_STR(x) XMK_STR(x) 578 579 #define CONFIG_EXTRA_ENV_SETTINGS \ 580 "netdev=" CONFIG_NETDEV "\0" \ 581 "uboot=" CONFIG_UBOOTPATH "\0" \ 582 "tftpflash=tftp $loadaddr $uboot;" \ 583 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 584 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 585 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\ 586 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 587 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ 588 "fdtaddr=780000\0" \ 589 "fdtfile=" CONFIG_FDTFILE "\0" \ 590 "ramdiskaddr=1000000\0" \ 591 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ 592 "console=ttyS0\0" \ 593 "setbootargs=setenv bootargs " \ 594 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\ 595 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 596 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 597 "$netdev:off "\ 598 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 599 600 #define CONFIG_NFSBOOTCOMMAND \ 601 "setenv rootdev /dev/nfs;" \ 602 "run setbootargs;" \ 603 "run setipargs;" \ 604 "tftp $loadaddr $bootfile;" \ 605 "tftp $fdtaddr $fdtfile;" \ 606 "bootm $loadaddr - $fdtaddr" 607 608 #define CONFIG_RAMBOOTCOMMAND \ 609 "setenv rootdev /dev/ram;" \ 610 "run setbootargs;" \ 611 "tftp $ramdiskaddr $ramdiskfile;" \ 612 "tftp $loadaddr $bootfile;" \ 613 "tftp $fdtaddr $fdtfile;" \ 614 "bootm $loadaddr $ramdiskaddr $fdtaddr" 615 616 #undef MK_STR 617 #undef XMK_STR 618 619 #endif /* __CONFIG_H */ 620