1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 /* 23 * mpc8313epb board configuration file 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* 30 * High Level Configuration Options 31 */ 32 #define CONFIG_E300 1 33 #define CONFIG_MPC83xx 1 34 #define CONFIG_MPC831x 1 35 #define CONFIG_MPC8313 1 36 #define CONFIG_MPC8313ERDB 1 37 38 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 39 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 40 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 41 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 42 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 43 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 44 45 #ifdef CONFIG_NAND_U_BOOT 46 #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 47 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 48 #ifdef CONFIG_NAND_SPL 49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 50 #endif /* CONFIG_NAND_SPL */ 51 #endif /* CONFIG_NAND_U_BOOT */ 52 53 #ifndef CONFIG_SYS_TEXT_BASE 54 #define CONFIG_SYS_TEXT_BASE 0xFE000000 55 #endif 56 57 #ifndef CONFIG_SYS_MONITOR_BASE 58 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 59 #endif 60 61 #define CONFIG_PCI 62 #define CONFIG_FSL_ELBC 1 63 64 #define CONFIG_MISC_INIT_R 65 66 /* 67 * On-board devices 68 * 69 * TSEC1 is VSC switch 70 * TSEC2 is SoC TSEC 71 */ 72 #define CONFIG_VSC7385_ENET 73 #define CONFIG_TSEC2 74 75 #ifdef CONFIG_SYS_66MHZ 76 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 77 #elif defined(CONFIG_SYS_33MHZ) 78 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 79 #else 80 #error Unknown oscillator frequency. 81 #endif 82 83 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 84 85 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 86 87 #define CONFIG_SYS_IMMR 0xE0000000 88 89 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 90 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 91 #endif 92 93 #define CONFIG_SYS_MEMTEST_START 0x00001000 94 #define CONFIG_SYS_MEMTEST_END 0x07f00000 95 96 /* Early revs of this board will lock up hard when attempting 97 * to access the PMC registers, unless a JTAG debugger is 98 * connected, or some resistor modifications are made. 99 */ 100 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 101 102 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 103 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 104 105 /* 106 * Device configurations 107 */ 108 109 /* Vitesse 7385 */ 110 111 #ifdef CONFIG_VSC7385_ENET 112 113 #define CONFIG_TSEC1 114 115 /* The flash address and size of the VSC7385 firmware image */ 116 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 117 #define CONFIG_VSC7385_IMAGE_SIZE 8192 118 119 #endif 120 121 /* 122 * DDR Setup 123 */ 124 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 125 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 126 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 127 128 /* 129 * Manually set up DDR parameters, as this board does not 130 * seem to have the SPD connected to I2C. 131 */ 132 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 133 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \ 134 | CSCONFIG_ODT_RD_NEVER \ 135 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 136 | CSCONFIG_ROW_BIT_13 \ 137 | CSCONFIG_COL_BIT_10) 138 /* 0x80010102 */ 139 140 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 141 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 142 | (0 << TIMING_CFG0_WRT_SHIFT) \ 143 | (0 << TIMING_CFG0_RRT_SHIFT) \ 144 | (0 << TIMING_CFG0_WWT_SHIFT) \ 145 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 146 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 147 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 148 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 149 /* 0x00220802 */ 150 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 151 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 152 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 153 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 154 | (10 << TIMING_CFG1_REFREC_SHIFT) \ 155 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 156 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 157 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 158 /* 0x3835a322 */ 159 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 160 | (5 << TIMING_CFG2_CPO_SHIFT) \ 161 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 162 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 163 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 164 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 165 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 166 /* 0x129048c6 */ /* P9-45,may need tuning */ 167 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 168 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 169 /* 0x05100500 */ 170 #if defined(CONFIG_DDR_2T_TIMING) 171 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 172 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 173 | SDRAM_CFG_DBW_32 \ 174 | SDRAM_CFG_2T_EN) 175 /* 0x43088000 */ 176 #else 177 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 178 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 179 | SDRAM_CFG_DBW_32) 180 /* 0x43080000 */ 181 #endif 182 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 183 /* set burst length to 8 for 32-bit data path */ 184 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 185 | (0x0632 << SDRAM_MODE_SD_SHIFT)) 186 /* 0x44480632 */ 187 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 188 189 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 190 /*0x02000000*/ 191 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 192 | DDRCDR_PZ_NOMZ \ 193 | DDRCDR_NZ_NOMZ \ 194 | DDRCDR_M_ODR) 195 196 /* 197 * FLASH on the Local Bus 198 */ 199 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 200 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 201 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 202 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 203 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 204 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 205 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 206 207 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 208 | (2 << BR_PS_SHIFT) /* 16 bit port */ \ 209 | BR_V) /* valid */ 210 #define CONFIG_SYS_NOR_OR_PRELIM (0xFF800000 /* 8 MByte */ \ 211 | OR_GPCM_XACS \ 212 | OR_GPCM_SCY_9 \ 213 | OR_GPCM_EHTR \ 214 | OR_GPCM_EAD) 215 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 216 /* window base at flash base */ 217 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 218 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 219 220 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 221 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 222 223 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 224 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 225 226 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 227 !defined(CONFIG_NAND_SPL) 228 #define CONFIG_SYS_RAMBOOT 229 #endif 230 231 #define CONFIG_SYS_INIT_RAM_LOCK 1 232 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 233 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 234 235 #define CONFIG_SYS_GBL_DATA_OFFSET \ 236 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 237 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 238 239 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 240 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 241 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 242 243 /* 244 * Local Bus LCRR and LBCR regs 245 */ 246 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 247 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 248 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 249 | (0xFF << LBCR_BMT_SHIFT) \ 250 | 0xF) /* 0x0004ff0f */ 251 252 /* LB refresh timer prescal, 266MHz/32 */ 253 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 254 255 /* drivers/mtd/nand/nand.c */ 256 #ifdef CONFIG_NAND_SPL 257 #define CONFIG_SYS_NAND_BASE 0xFFF00000 258 #else 259 #define CONFIG_SYS_NAND_BASE 0xE2800000 260 #endif 261 262 #define CONFIG_MTD_DEVICE 263 #define CONFIG_MTD_PARTITION 264 #define CONFIG_CMD_MTDPARTS 265 #define MTDIDS_DEFAULT "nand0=e2800000.flash" 266 #define MTDPARTS_DEFAULT \ 267 "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 268 269 #define CONFIG_SYS_MAX_NAND_DEVICE 1 270 #define CONFIG_MTD_NAND_VERIFY_WRITE 271 #define CONFIG_CMD_NAND 1 272 #define CONFIG_NAND_FSL_ELBC 1 273 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 274 275 276 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 277 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 278 | BR_PS_8 /* 8 bit port */ \ 279 | BR_MS_FCM /* MSEL = FCM */ \ 280 | BR_V) /* valid */ 281 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \ 282 | OR_FCM_CSCT \ 283 | OR_FCM_CST \ 284 | OR_FCM_CHT \ 285 | OR_FCM_SCY_1 \ 286 | OR_FCM_TRLX \ 287 | OR_FCM_EHTR) 288 /* 0xFFFF8396 */ 289 290 #ifdef CONFIG_NAND_U_BOOT 291 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 292 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 293 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 294 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 295 #else 296 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 297 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 298 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 299 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 300 #endif 301 302 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 303 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 304 305 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 306 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 307 308 /* local bus read write buffer mapping */ 309 #define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 310 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 311 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000 312 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 313 314 /* Vitesse 7385 */ 315 316 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 317 318 #ifdef CONFIG_VSC7385_ENET 319 320 /* VSC7385 Base address */ 321 #define CONFIG_SYS_BR2_PRELIM 0xf0000801 322 /* VSC7385, 128K bytes*/ 323 #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff 324 /* Access window base at VSC7385 base */ 325 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 326 /* Access window size 128K */ 327 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 328 329 #endif 330 331 /* pass open firmware flat tree */ 332 #define CONFIG_OF_LIBFDT 1 333 #define CONFIG_OF_BOARD_SETUP 1 334 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 335 336 /* 337 * Serial Port 338 */ 339 #define CONFIG_CONS_INDEX 1 340 #define CONFIG_SYS_NS16550 341 #define CONFIG_SYS_NS16550_SERIAL 342 #define CONFIG_SYS_NS16550_REG_SIZE 1 343 344 #define CONFIG_SYS_BAUDRATE_TABLE \ 345 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 346 347 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 348 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 349 350 /* Use the HUSH parser */ 351 #define CONFIG_SYS_HUSH_PARSER 352 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 353 354 /* I2C */ 355 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 356 #define CONFIG_FSL_I2C 357 #define CONFIG_I2C_MULTI_BUS 358 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 359 #define CONFIG_SYS_I2C_SLAVE 0x7F 360 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 361 #define CONFIG_SYS_I2C_OFFSET 0x3000 362 #define CONFIG_SYS_I2C2_OFFSET 0x3100 363 364 /* 365 * General PCI 366 * Addresses are mapped 1-1. 367 */ 368 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 369 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 370 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 371 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 372 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 373 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 374 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 375 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 376 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 377 378 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 379 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 380 381 /* 382 * TSEC 383 */ 384 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 385 386 #define CONFIG_GMII /* MII PHY management */ 387 388 #ifdef CONFIG_TSEC1 389 #define CONFIG_HAS_ETH0 390 #define CONFIG_TSEC1_NAME "TSEC0" 391 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 392 #define TSEC1_PHY_ADDR 0x1c 393 #define TSEC1_FLAGS TSEC_GIGABIT 394 #define TSEC1_PHYIDX 0 395 #endif 396 397 #ifdef CONFIG_TSEC2 398 #define CONFIG_HAS_ETH1 399 #define CONFIG_TSEC2_NAME "TSEC1" 400 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 401 #define TSEC2_PHY_ADDR 4 402 #define TSEC2_FLAGS TSEC_GIGABIT 403 #define TSEC2_PHYIDX 0 404 #endif 405 406 407 /* Options are: TSEC[0-1] */ 408 #define CONFIG_ETHPRIME "TSEC1" 409 410 /* 411 * Configure on-board RTC 412 */ 413 #define CONFIG_RTC_DS1337 414 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 415 416 /* 417 * Environment 418 */ 419 #if defined(CONFIG_NAND_U_BOOT) 420 #define CONFIG_ENV_IS_IN_NAND 1 421 #define CONFIG_ENV_OFFSET (512 * 1024) 422 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 423 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 424 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 425 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 426 #define CONFIG_ENV_OFFSET_REDUND \ 427 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 428 #elif !defined(CONFIG_SYS_RAMBOOT) 429 #define CONFIG_ENV_IS_IN_FLASH 1 430 #define CONFIG_ENV_ADDR \ 431 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 432 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 433 #define CONFIG_ENV_SIZE 0x2000 434 435 /* Address and size of Redundant Environment Sector */ 436 #else 437 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 438 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 439 #define CONFIG_ENV_SIZE 0x2000 440 #endif 441 442 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 443 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 444 445 /* 446 * BOOTP options 447 */ 448 #define CONFIG_BOOTP_BOOTFILESIZE 449 #define CONFIG_BOOTP_BOOTPATH 450 #define CONFIG_BOOTP_GATEWAY 451 #define CONFIG_BOOTP_HOSTNAME 452 453 454 /* 455 * Command line configuration. 456 */ 457 #include <config_cmd_default.h> 458 459 #define CONFIG_CMD_PING 460 #define CONFIG_CMD_DHCP 461 #define CONFIG_CMD_I2C 462 #define CONFIG_CMD_MII 463 #define CONFIG_CMD_DATE 464 #define CONFIG_CMD_PCI 465 466 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) 467 #undef CONFIG_CMD_SAVEENV 468 #undef CONFIG_CMD_LOADS 469 #endif 470 471 #define CONFIG_CMDLINE_EDITING 1 472 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 473 474 /* 475 * Miscellaneous configurable options 476 */ 477 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 478 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 479 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 480 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 481 482 /* Print Buffer Size */ 483 #define CONFIG_SYS_PBSIZE \ 484 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 485 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 486 /* Boot Argument Buffer Size */ 487 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 488 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 489 490 /* 491 * For booting Linux, the board info and command line data 492 * have to be in the first 256 MB of memory, since this is 493 * the maximum mapped by the Linux kernel during initialization. 494 */ 495 /* Initial Memory map for Linux*/ 496 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 497 498 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 499 500 #ifdef CONFIG_SYS_66MHZ 501 502 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 503 /* 0x62040000 */ 504 #define CONFIG_SYS_HRCW_LOW (\ 505 0x20000000 /* reserved, must be set */ |\ 506 HRCWL_DDRCM |\ 507 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 508 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 509 HRCWL_CSB_TO_CLKIN_2X1 |\ 510 HRCWL_CORE_TO_CSB_2X1) 511 512 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 513 514 #elif defined(CONFIG_SYS_33MHZ) 515 516 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 517 /* 0x65040000 */ 518 #define CONFIG_SYS_HRCW_LOW (\ 519 0x20000000 /* reserved, must be set */ |\ 520 HRCWL_DDRCM |\ 521 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 522 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 523 HRCWL_CSB_TO_CLKIN_5X1 |\ 524 HRCWL_CORE_TO_CSB_2X1) 525 526 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 527 528 #endif 529 530 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 531 HRCWH_PCI_HOST |\ 532 HRCWH_PCI1_ARBITER_ENABLE |\ 533 HRCWH_CORE_ENABLE |\ 534 HRCWH_BOOTSEQ_DISABLE |\ 535 HRCWH_SW_WATCHDOG_DISABLE |\ 536 HRCWH_TSEC1M_IN_RGMII |\ 537 HRCWH_TSEC2M_IN_RGMII |\ 538 HRCWH_BIG_ENDIAN) 539 540 #ifdef CONFIG_NAND_SPL 541 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 542 HRCWH_FROM_0XFFF00100 |\ 543 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 544 HRCWH_RL_EXT_NAND) 545 #else 546 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 547 HRCWH_FROM_0X00000100 |\ 548 HRCWH_ROM_LOC_LOCAL_16BIT |\ 549 HRCWH_RL_EXT_LEGACY) 550 #endif 551 552 /* System IO Config */ 553 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 554 #define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */ 555 556 #define CONFIG_SYS_HID0_INIT 0x000000000 557 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 558 HID0_ENABLE_INSTRUCTION_CACHE | \ 559 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 560 561 #define CONFIG_SYS_HID2 HID2_HBE 562 563 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 564 565 /* DDR @ 0x00000000 */ 566 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 567 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 568 | BATU_BL_256M \ 569 | BATU_VS \ 570 | BATU_VP) 571 572 /* PCI @ 0x80000000 */ 573 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 574 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 575 | BATU_BL_256M \ 576 | BATU_VS \ 577 | BATU_VP) 578 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 579 | BATL_PP_RW \ 580 | BATL_CACHEINHIBIT \ 581 | BATL_GUARDEDSTORAGE) 582 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 583 | BATU_BL_256M \ 584 | BATU_VS \ 585 | BATU_VP) 586 587 /* PCI2 not supported on 8313 */ 588 #define CONFIG_SYS_IBAT3L (0) 589 #define CONFIG_SYS_IBAT3U (0) 590 #define CONFIG_SYS_IBAT4L (0) 591 #define CONFIG_SYS_IBAT4U (0) 592 593 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 594 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 595 | BATL_PP_RW \ 596 | BATL_CACHEINHIBIT \ 597 | BATL_GUARDEDSTORAGE) 598 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 599 | BATU_BL_256M \ 600 | BATU_VS \ 601 | BATU_VP) 602 603 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 604 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 605 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 606 607 #define CONFIG_SYS_IBAT7L (0) 608 #define CONFIG_SYS_IBAT7U (0) 609 610 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 611 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 612 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 613 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 614 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 615 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 616 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 617 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 618 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 619 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 620 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 621 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 622 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 623 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 624 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 625 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 626 627 /* 628 * Environment Configuration 629 */ 630 #define CONFIG_ENV_OVERWRITE 631 632 #define CONFIG_NETDEV "eth1" 633 634 #define CONFIG_HOSTNAME mpc8313erdb 635 #define CONFIG_ROOTPATH "/nfs/root/path" 636 #define CONFIG_BOOTFILE "uImage" 637 /* U-Boot image on TFTP server */ 638 #define CONFIG_UBOOTPATH "u-boot.bin" 639 #define CONFIG_FDTFILE "mpc8313erdb.dtb" 640 641 /* default location for tftp and bootm */ 642 #define CONFIG_LOADADDR 800000 643 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 644 #define CONFIG_BAUDRATE 115200 645 646 #define XMK_STR(x) #x 647 #define MK_STR(x) XMK_STR(x) 648 649 #define CONFIG_EXTRA_ENV_SETTINGS \ 650 "netdev=" CONFIG_NETDEV "\0" \ 651 "ethprime=TSEC1\0" \ 652 "uboot=" CONFIG_UBOOTPATH "\0" \ 653 "tftpflash=tftpboot $loadaddr $uboot; " \ 654 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 655 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 656 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\ 657 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 658 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ 659 "fdtaddr=780000\0" \ 660 "fdtfile=" CONFIG_FDTFILE "\0" \ 661 "console=ttyS0\0" \ 662 "setbootargs=setenv bootargs " \ 663 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 664 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 665 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 666 "$netdev:off " \ 667 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 668 669 #define CONFIG_NFSBOOTCOMMAND \ 670 "setenv rootdev /dev/nfs;" \ 671 "run setbootargs;" \ 672 "run setipargs;" \ 673 "tftp $loadaddr $bootfile;" \ 674 "tftp $fdtaddr $fdtfile;" \ 675 "bootm $loadaddr - $fdtaddr" 676 677 #define CONFIG_RAMBOOTCOMMAND \ 678 "setenv rootdev /dev/ram;" \ 679 "run setbootargs;" \ 680 "tftp $ramdiskaddr $ramdiskfile;" \ 681 "tftp $loadaddr $bootfile;" \ 682 "tftp $fdtaddr $fdtfile;" \ 683 "bootm $loadaddr $ramdiskaddr $fdtaddr" 684 685 #undef MK_STR 686 #undef XMK_STR 687 688 #endif /* __CONFIG_H */ 689