1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 /* 23 * mpc8313epb board configuration file 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* 30 * High Level Configuration Options 31 */ 32 #define CONFIG_E300 1 33 #define CONFIG_MPC83xx 1 34 #define CONFIG_MPC831x 1 35 #define CONFIG_MPC8313 1 36 #define CONFIG_MPC8313ERDB 1 37 38 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 39 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 40 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 41 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 42 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 43 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 44 45 #ifdef CONFIG_NAND_U_BOOT 46 #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 47 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 48 #ifdef CONFIG_NAND_SPL 49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 50 #endif /* CONFIG_NAND_SPL */ 51 #endif /* CONFIG_NAND_U_BOOT */ 52 53 #ifndef CONFIG_SYS_TEXT_BASE 54 #define CONFIG_SYS_TEXT_BASE 0xFE000000 55 #endif 56 57 #ifndef CONFIG_SYS_MONITOR_BASE 58 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 59 #endif 60 61 #define CONFIG_PCI 62 #define CONFIG_FSL_ELBC 1 63 64 #define CONFIG_MISC_INIT_R 65 66 /* 67 * On-board devices 68 * 69 * TSEC1 is VSC switch 70 * TSEC2 is SoC TSEC 71 */ 72 #define CONFIG_VSC7385_ENET 73 #define CONFIG_TSEC2 74 75 #ifdef CONFIG_SYS_66MHZ 76 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 77 #elif defined(CONFIG_SYS_33MHZ) 78 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 79 #else 80 #error Unknown oscillator frequency. 81 #endif 82 83 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 84 85 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 86 87 #define CONFIG_SYS_IMMR 0xE0000000 88 89 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 90 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 91 #endif 92 93 #define CONFIG_SYS_MEMTEST_START 0x00001000 94 #define CONFIG_SYS_MEMTEST_END 0x07f00000 95 96 /* Early revs of this board will lock up hard when attempting 97 * to access the PMC registers, unless a JTAG debugger is 98 * connected, or some resistor modifications are made. 99 */ 100 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 101 102 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 103 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 104 105 /* 106 * Device configurations 107 */ 108 109 /* Vitesse 7385 */ 110 111 #ifdef CONFIG_VSC7385_ENET 112 113 #define CONFIG_TSEC1 114 115 /* The flash address and size of the VSC7385 firmware image */ 116 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 117 #define CONFIG_VSC7385_IMAGE_SIZE 8192 118 119 #endif 120 121 /* 122 * DDR Setup 123 */ 124 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 125 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 126 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 127 128 /* 129 * Manually set up DDR parameters, as this board does not 130 * seem to have the SPD connected to I2C. 131 */ 132 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 133 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \ 134 | 0x00010000 /* TODO */ \ 135 | CSCONFIG_ROW_BIT_13 \ 136 | CSCONFIG_COL_BIT_10) 137 /* 0x80010102 */ 138 139 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 140 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 141 | (0 << TIMING_CFG0_WRT_SHIFT) \ 142 | (0 << TIMING_CFG0_RRT_SHIFT) \ 143 | (0 << TIMING_CFG0_WWT_SHIFT) \ 144 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 145 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 146 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 147 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 148 /* 0x00220802 */ 149 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 150 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 151 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 152 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 153 | (10 << TIMING_CFG1_REFREC_SHIFT) \ 154 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 155 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 156 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 157 /* 0x3835a322 */ 158 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 159 | (5 << TIMING_CFG2_CPO_SHIFT) \ 160 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 161 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 162 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 163 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 164 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 165 /* 0x129048c6 */ /* P9-45,may need tuning */ 166 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 167 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 168 /* 0x05100500 */ 169 #if defined(CONFIG_DDR_2T_TIMING) 170 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 171 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 172 | SDRAM_CFG_2T_EN \ 173 | SDRAM_CFG_DBW_32) 174 #else 175 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 176 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 177 | SDRAM_CFG_32_BE) 178 /* 0x43080000 */ 179 #endif 180 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 181 /* set burst length to 8 for 32-bit data path */ 182 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 183 | (0x0632 << SDRAM_MODE_SD_SHIFT)) 184 /* 0x44480632 */ 185 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 186 187 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 188 /*0x02000000*/ 189 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 190 | DDRCDR_PZ_NOMZ \ 191 | DDRCDR_NZ_NOMZ \ 192 | DDRCDR_M_ODR) 193 194 /* 195 * FLASH on the Local Bus 196 */ 197 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 198 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 199 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 200 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 201 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 202 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 203 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 204 205 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 206 | (2 << BR_PS_SHIFT) /* 16 bit port */ \ 207 | BR_V) /* valid */ 208 #define CONFIG_SYS_NOR_OR_PRELIM (0xFF800000 /* 8 MByte */ \ 209 | OR_GPCM_XACS \ 210 | OR_GPCM_SCY_9 \ 211 | OR_GPCM_EHTR \ 212 | OR_GPCM_EAD) 213 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 214 /* window base at flash base */ 215 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 216 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 217 218 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 219 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 220 221 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 222 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 223 224 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 225 !defined(CONFIG_NAND_SPL) 226 #define CONFIG_SYS_RAMBOOT 227 #endif 228 229 #define CONFIG_SYS_INIT_RAM_LOCK 1 230 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 231 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 232 233 #define CONFIG_SYS_GBL_DATA_OFFSET \ 234 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 235 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 236 237 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 238 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 239 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 240 241 /* 242 * Local Bus LCRR and LBCR regs 243 */ 244 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 245 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 246 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 247 | (0xFF << LBCR_BMT_SHIFT) \ 248 | 0xF) /* 0x0004ff0f */ 249 250 /* LB refresh timer prescal, 266MHz/32 */ 251 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 252 253 /* drivers/mtd/nand/nand.c */ 254 #ifdef CONFIG_NAND_SPL 255 #define CONFIG_SYS_NAND_BASE 0xFFF00000 256 #else 257 #define CONFIG_SYS_NAND_BASE 0xE2800000 258 #endif 259 260 #define CONFIG_MTD_DEVICE 261 #define CONFIG_MTD_PARTITION 262 #define CONFIG_CMD_MTDPARTS 263 #define MTDIDS_DEFAULT "nand0=e2800000.flash" 264 #define MTDPARTS_DEFAULT \ 265 "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 266 267 #define CONFIG_SYS_MAX_NAND_DEVICE 1 268 #define CONFIG_MTD_NAND_VERIFY_WRITE 269 #define CONFIG_CMD_NAND 1 270 #define CONFIG_NAND_FSL_ELBC 1 271 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 272 273 274 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 275 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 276 | BR_PS_8 /* 8 bit port */ \ 277 | BR_MS_FCM /* MSEL = FCM */ \ 278 | BR_V) /* valid */ 279 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \ 280 | OR_FCM_CSCT \ 281 | OR_FCM_CST \ 282 | OR_FCM_CHT \ 283 | OR_FCM_SCY_1 \ 284 | OR_FCM_TRLX \ 285 | OR_FCM_EHTR) 286 /* 0xFFFF8396 */ 287 288 #ifdef CONFIG_NAND_U_BOOT 289 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 290 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 291 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 292 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 293 #else 294 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 295 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 296 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 297 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 298 #endif 299 300 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 301 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 302 303 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 304 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 305 306 /* local bus read write buffer mapping */ 307 #define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 308 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 309 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000 310 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 311 312 /* Vitesse 7385 */ 313 314 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 315 316 #ifdef CONFIG_VSC7385_ENET 317 318 /* VSC7385 Base address */ 319 #define CONFIG_SYS_BR2_PRELIM 0xf0000801 320 /* VSC7385, 128K bytes*/ 321 #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff 322 /* Access window base at VSC7385 base */ 323 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 324 /* Access window size 128K */ 325 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 326 327 #endif 328 329 /* pass open firmware flat tree */ 330 #define CONFIG_OF_LIBFDT 1 331 #define CONFIG_OF_BOARD_SETUP 1 332 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 333 334 /* 335 * Serial Port 336 */ 337 #define CONFIG_CONS_INDEX 1 338 #define CONFIG_SYS_NS16550 339 #define CONFIG_SYS_NS16550_SERIAL 340 #define CONFIG_SYS_NS16550_REG_SIZE 1 341 342 #define CONFIG_SYS_BAUDRATE_TABLE \ 343 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 344 345 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 346 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 347 348 /* Use the HUSH parser */ 349 #define CONFIG_SYS_HUSH_PARSER 350 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 351 352 /* I2C */ 353 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 354 #define CONFIG_FSL_I2C 355 #define CONFIG_I2C_MULTI_BUS 356 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 357 #define CONFIG_SYS_I2C_SLAVE 0x7F 358 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 359 #define CONFIG_SYS_I2C_OFFSET 0x3000 360 #define CONFIG_SYS_I2C2_OFFSET 0x3100 361 362 /* 363 * General PCI 364 * Addresses are mapped 1-1. 365 */ 366 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 367 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 368 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 369 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 370 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 371 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 372 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 373 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 374 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 375 376 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 377 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 378 379 /* 380 * TSEC 381 */ 382 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 383 384 #define CONFIG_GMII /* MII PHY management */ 385 386 #ifdef CONFIG_TSEC1 387 #define CONFIG_HAS_ETH0 388 #define CONFIG_TSEC1_NAME "TSEC0" 389 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 390 #define TSEC1_PHY_ADDR 0x1c 391 #define TSEC1_FLAGS TSEC_GIGABIT 392 #define TSEC1_PHYIDX 0 393 #endif 394 395 #ifdef CONFIG_TSEC2 396 #define CONFIG_HAS_ETH1 397 #define CONFIG_TSEC2_NAME "TSEC1" 398 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 399 #define TSEC2_PHY_ADDR 4 400 #define TSEC2_FLAGS TSEC_GIGABIT 401 #define TSEC2_PHYIDX 0 402 #endif 403 404 405 /* Options are: TSEC[0-1] */ 406 #define CONFIG_ETHPRIME "TSEC1" 407 408 /* 409 * Configure on-board RTC 410 */ 411 #define CONFIG_RTC_DS1337 412 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 413 414 /* 415 * Environment 416 */ 417 #if defined(CONFIG_NAND_U_BOOT) 418 #define CONFIG_ENV_IS_IN_NAND 1 419 #define CONFIG_ENV_OFFSET (512 * 1024) 420 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 421 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 422 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 423 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 424 #define CONFIG_ENV_OFFSET_REDUND \ 425 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 426 #elif !defined(CONFIG_SYS_RAMBOOT) 427 #define CONFIG_ENV_IS_IN_FLASH 1 428 #define CONFIG_ENV_ADDR \ 429 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 430 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 431 #define CONFIG_ENV_SIZE 0x2000 432 433 /* Address and size of Redundant Environment Sector */ 434 #else 435 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 436 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 437 #define CONFIG_ENV_SIZE 0x2000 438 #endif 439 440 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 441 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 442 443 /* 444 * BOOTP options 445 */ 446 #define CONFIG_BOOTP_BOOTFILESIZE 447 #define CONFIG_BOOTP_BOOTPATH 448 #define CONFIG_BOOTP_GATEWAY 449 #define CONFIG_BOOTP_HOSTNAME 450 451 452 /* 453 * Command line configuration. 454 */ 455 #include <config_cmd_default.h> 456 457 #define CONFIG_CMD_PING 458 #define CONFIG_CMD_DHCP 459 #define CONFIG_CMD_I2C 460 #define CONFIG_CMD_MII 461 #define CONFIG_CMD_DATE 462 #define CONFIG_CMD_PCI 463 464 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) 465 #undef CONFIG_CMD_SAVEENV 466 #undef CONFIG_CMD_LOADS 467 #endif 468 469 #define CONFIG_CMDLINE_EDITING 1 470 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 471 472 /* 473 * Miscellaneous configurable options 474 */ 475 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 476 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 477 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 478 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 479 480 /* Print Buffer Size */ 481 #define CONFIG_SYS_PBSIZE \ 482 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 483 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 484 /* Boot Argument Buffer Size */ 485 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 486 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 487 488 /* 489 * For booting Linux, the board info and command line data 490 * have to be in the first 256 MB of memory, since this is 491 * the maximum mapped by the Linux kernel during initialization. 492 */ 493 /* Initial Memory map for Linux*/ 494 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 495 496 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 497 498 #ifdef CONFIG_SYS_66MHZ 499 500 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 501 /* 0x62040000 */ 502 #define CONFIG_SYS_HRCW_LOW (\ 503 0x20000000 /* reserved, must be set */ |\ 504 HRCWL_DDRCM |\ 505 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 506 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 507 HRCWL_CSB_TO_CLKIN_2X1 |\ 508 HRCWL_CORE_TO_CSB_2X1) 509 510 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 511 512 #elif defined(CONFIG_SYS_33MHZ) 513 514 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 515 /* 0x65040000 */ 516 #define CONFIG_SYS_HRCW_LOW (\ 517 0x20000000 /* reserved, must be set */ |\ 518 HRCWL_DDRCM |\ 519 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 520 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 521 HRCWL_CSB_TO_CLKIN_5X1 |\ 522 HRCWL_CORE_TO_CSB_2X1) 523 524 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 525 526 #endif 527 528 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 529 HRCWH_PCI_HOST |\ 530 HRCWH_PCI1_ARBITER_ENABLE |\ 531 HRCWH_CORE_ENABLE |\ 532 HRCWH_BOOTSEQ_DISABLE |\ 533 HRCWH_SW_WATCHDOG_DISABLE |\ 534 HRCWH_TSEC1M_IN_RGMII |\ 535 HRCWH_TSEC2M_IN_RGMII |\ 536 HRCWH_BIG_ENDIAN) 537 538 #ifdef CONFIG_NAND_SPL 539 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 540 HRCWH_FROM_0XFFF00100 |\ 541 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 542 HRCWH_RL_EXT_NAND) 543 #else 544 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 545 HRCWH_FROM_0X00000100 |\ 546 HRCWH_ROM_LOC_LOCAL_16BIT |\ 547 HRCWH_RL_EXT_LEGACY) 548 #endif 549 550 /* System IO Config */ 551 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 552 #define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */ 553 554 #define CONFIG_SYS_HID0_INIT 0x000000000 555 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 556 HID0_ENABLE_INSTRUCTION_CACHE | \ 557 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 558 559 #define CONFIG_SYS_HID2 HID2_HBE 560 561 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 562 563 /* DDR @ 0x00000000 */ 564 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) 565 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 566 | BATU_BL_256M \ 567 | BATU_VS \ 568 | BATU_VP) 569 570 /* PCI @ 0x80000000 */ 571 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) 572 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 573 | BATU_BL_256M \ 574 | BATU_VS \ 575 | BATU_VP) 576 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 577 | BATL_PP_10 \ 578 | BATL_CACHEINHIBIT \ 579 | BATL_GUARDEDSTORAGE) 580 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 581 | BATU_BL_256M \ 582 | BATU_VS \ 583 | BATU_VP) 584 585 /* PCI2 not supported on 8313 */ 586 #define CONFIG_SYS_IBAT3L (0) 587 #define CONFIG_SYS_IBAT3U (0) 588 #define CONFIG_SYS_IBAT4L (0) 589 #define CONFIG_SYS_IBAT4U (0) 590 591 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 592 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 593 | BATL_PP_10 \ 594 | BATL_CACHEINHIBIT \ 595 | BATL_GUARDEDSTORAGE) 596 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 597 | BATU_BL_256M \ 598 | BATU_VS \ 599 | BATU_VP) 600 601 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 602 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) 603 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 604 605 #define CONFIG_SYS_IBAT7L (0) 606 #define CONFIG_SYS_IBAT7U (0) 607 608 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 609 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 610 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 611 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 612 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 613 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 614 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 615 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 616 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 617 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 618 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 619 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 620 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 621 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 622 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 623 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 624 625 /* 626 * Environment Configuration 627 */ 628 #define CONFIG_ENV_OVERWRITE 629 630 #define CONFIG_NETDEV "eth1" 631 632 #define CONFIG_HOSTNAME mpc8313erdb 633 #define CONFIG_ROOTPATH "/nfs/root/path" 634 #define CONFIG_BOOTFILE "uImage" 635 /* U-Boot image on TFTP server */ 636 #define CONFIG_UBOOTPATH "u-boot.bin" 637 #define CONFIG_FDTFILE "mpc8313erdb.dtb" 638 639 /* default location for tftp and bootm */ 640 #define CONFIG_LOADADDR 800000 641 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 642 #define CONFIG_BAUDRATE 115200 643 644 #define XMK_STR(x) #x 645 #define MK_STR(x) XMK_STR(x) 646 647 #define CONFIG_EXTRA_ENV_SETTINGS \ 648 "netdev=" CONFIG_NETDEV "\0" \ 649 "ethprime=TSEC1\0" \ 650 "uboot=" CONFIG_UBOOTPATH "\0" \ 651 "tftpflash=tftpboot $loadaddr $uboot; " \ 652 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 653 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 654 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\ 655 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 656 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ 657 "fdtaddr=780000\0" \ 658 "fdtfile=" CONFIG_FDTFILE "\0" \ 659 "console=ttyS0\0" \ 660 "setbootargs=setenv bootargs " \ 661 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 662 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 663 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 664 "$netdev:off " \ 665 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 666 667 #define CONFIG_NFSBOOTCOMMAND \ 668 "setenv rootdev /dev/nfs;" \ 669 "run setbootargs;" \ 670 "run setipargs;" \ 671 "tftp $loadaddr $bootfile;" \ 672 "tftp $fdtaddr $fdtfile;" \ 673 "bootm $loadaddr - $fdtaddr" 674 675 #define CONFIG_RAMBOOTCOMMAND \ 676 "setenv rootdev /dev/ram;" \ 677 "run setbootargs;" \ 678 "tftp $ramdiskaddr $ramdiskfile;" \ 679 "tftp $loadaddr $bootfile;" \ 680 "tftp $fdtaddr $fdtfile;" \ 681 "bootm $loadaddr $ramdiskaddr $fdtaddr" 682 683 #undef MK_STR 684 #undef XMK_STR 685 686 #endif /* __CONFIG_H */ 687