1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 * 22 * History 23 * 20061201: Wilson Lo (Wilson.Lo@freescale.com) 24 * Initialized 25 * 20061210: Tanya Jiang (tanya.jiang@freescale.com) 26 * Code Cleanup 27 * 20070410: Scott Wood <scottwood@freescale.com> 28 * More cleanup 29 */ 30 /* 31 * mpc8313epb board configuration file 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* 38 * High Level Configuration Options 39 */ 40 #define CONFIG_E300 1 41 #define CONFIG_MPC83XX 1 42 #define CONFIG_MPC831X 1 43 #define CONFIG_MPC8313 1 44 #define CONFIG_MPC8313ERDB 1 45 46 #define CONFIG_PCI 47 #define CONFIG_83XX_GENERIC_PCI 48 49 #ifdef CFG_66MHZ 50 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 51 #elif defined(CFG_33MHZ) 52 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 53 #else 54 #error Unknown oscillator frequency. 55 #endif 56 57 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 58 59 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 60 61 #define CFG_IMMR 0xE0000000 62 63 #define CFG_MEMTEST_START 0x00001000 64 #define CFG_MEMTEST_END 0x07f00000 65 66 /* Early revs of this board will lock up hard when attempting 67 * to access the PMC registers, unless a JTAG debugger is 68 * connected, or some resistor modifications are made. 69 */ 70 #define CFG_8313ERDB_BROKEN_PMC 1 71 72 #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 73 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 74 75 /* 76 * DDR Setup 77 */ 78 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 79 #define CFG_SDRAM_BASE CFG_DDR_BASE 80 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 81 82 /* 83 * Manually set up DDR parameters, as this board does not 84 * seem to have the SPD connected to I2C. 85 */ 86 #define CFG_DDR_SIZE 128 /* MB */ 87 #define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \ 88 | 0x00040000 /* TODO */ \ 89 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) 90 /* 0x80840102 */ 91 92 #define CFG_DDR_TIMING_3 0x00000000 93 #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 94 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 95 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 96 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 97 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 98 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 99 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 100 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 101 /* 0x00220802 */ 102 #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 103 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 104 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 105 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 106 | (13 << TIMING_CFG1_REFREC_SHIFT ) \ 107 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ 108 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 109 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 110 /* 0x3935d322 */ 111 #define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 112 | (31 << TIMING_CFG2_CPO_SHIFT ) \ 113 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 114 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 115 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 116 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 117 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 118 /* 0x0f9048ca */ /* P9-45,may need tuning */ 119 #define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 120 | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 121 /* 0x03200064 */ 122 #if defined(CONFIG_DDR_2T_TIMING) 123 #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ 124 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ 125 | SDRAM_CFG_2T_EN \ 126 | SDRAM_CFG_DBW_32 ) 127 #else 128 #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ 129 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ 130 | SDRAM_CFG_32_BE ) 131 /* 0x43080000 */ 132 #endif 133 #define CFG_SDRAM_CFG2 0x00401000; 134 /* set burst length to 8 for 32-bit data path */ 135 #define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ 136 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) 137 /* 0x44400232 */ 138 #define CFG_DDR_MODE_2 0x8000C000; 139 140 #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 141 /*0x02000000*/ 142 #define CFG_DDRCDR_VALUE ( DDRCDR_EN \ 143 | DDRCDR_PZ_NOMZ \ 144 | DDRCDR_NZ_NOMZ \ 145 | DDRCDR_M_ODR ) 146 147 /* 148 * FLASH on the Local Bus 149 */ 150 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 151 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 152 #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 153 #define CFG_FLASH_SIZE 8 /* flash size in MB */ 154 #define CFG_FLASH_EMPTY_INFO /* display empty sectors */ 155 #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 156 157 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ 158 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 159 BR_V) /* valid */ 160 #define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ 161 | OR_GPCM_XACS \ 162 | OR_GPCM_SCY_9 \ 163 | OR_GPCM_EHTR \ 164 | OR_GPCM_EAD ) 165 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 166 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ 167 #define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 168 169 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 170 #define CFG_MAX_FLASH_SECT 135 /* sectors per device */ 171 172 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 173 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 174 175 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 176 177 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 178 #define CFG_RAMBOOT 179 #endif 180 181 #define CFG_INIT_RAM_LOCK 1 182 #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 183 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 184 185 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 186 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 187 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 188 189 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 190 #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 191 192 /* 193 * Local Bus LCRR and LBCR regs 194 */ 195 #define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ 196 #define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ 197 | (0xFF << LBCR_BMT_SHIFT) \ 198 | 0xF ) /* 0x0004ff0f */ 199 200 #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ 201 202 /* drivers/nand/nand.c */ 203 #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ 204 #define CFG_MAX_NAND_DEVICE 1 205 #define NAND_MAX_CHIPS 1 206 #define CONFIG_MTD_NAND_VERIFY_WRITE 207 208 #define CFG_BR1_PRELIM ( CFG_NAND_BASE \ 209 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 210 | BR_PS_8 /* Port Size = 8 bit */ \ 211 | BR_MS_FCM /* MSEL = FCM */ \ 212 | BR_V ) /* valid */ 213 #define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ 214 | OR_FCM_CSCT \ 215 | OR_FCM_CST \ 216 | OR_FCM_CHT \ 217 | OR_FCM_SCY_1 \ 218 | OR_FCM_TRLX \ 219 | OR_FCM_EHTR ) 220 /* 0xFFFF8396 */ 221 #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE 222 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 223 224 #define CFG_VSC7385_BASE 0xF0000000 225 226 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 227 #define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ 228 #define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ 229 #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */ 230 #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ 231 232 /* local bus read write buffer mapping */ 233 #define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 234 #define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 235 #define CFG_LBLAWBAR3_PRELIM 0xFA000000 236 #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 237 238 /* pass open firmware flat tree */ 239 #define CONFIG_OF_FLAT_TREE 1 240 #define CONFIG_OF_BOARD_SETUP 1 241 242 /* maximum size of the flat tree (8K) */ 243 #define OF_FLAT_TREE_MAX_SIZE 8192 244 245 #define OF_CPU "PowerPC,8313@0" 246 #define OF_SOC "soc8313@e0000000" 247 #define OF_TBCLK (bd->bi_busfreq / 4) 248 #define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500" 249 250 /* 251 * Serial Port 252 */ 253 #define CONFIG_CONS_INDEX 1 254 #define CFG_NS16550 255 #define CFG_NS16550_SERIAL 256 #define CFG_NS16550_REG_SIZE 1 257 #define CFG_NS16550_CLK get_bus_freq(0) 258 259 #define CFG_BAUDRATE_TABLE \ 260 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 261 262 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 263 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 264 265 /* Use the HUSH parser */ 266 #define CFG_HUSH_PARSER 267 #define CFG_PROMPT_HUSH_PS2 "> " 268 269 /* I2C */ 270 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 271 #define CONFIG_FSL_I2C 272 #define CONFIG_I2C_MULTI_BUS 273 #define CONFIG_I2C_CMD_TREE 274 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 275 #define CFG_I2C_SLAVE 0x7F 276 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 277 #define CFG_I2C_OFFSET 0x3000 278 #define CFG_I2C2_OFFSET 0x3100 279 280 /* TSEC */ 281 #define CFG_TSEC1_OFFSET 0x24000 282 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) 283 #define CFG_TSEC2_OFFSET 0x25000 284 #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) 285 #define CONFIG_NET_MULTI 286 287 /* 288 * General PCI 289 * Addresses are mapped 1-1. 290 */ 291 #define CFG_PCI1_MEM_BASE 0x80000000 292 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 293 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 294 #define CFG_PCI1_MMIO_BASE 0x90000000 295 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 296 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 297 #define CFG_PCI1_IO_BASE 0x00000000 298 #define CFG_PCI1_IO_PHYS 0xE2000000 299 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 300 301 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 302 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 303 304 /* 305 * TSEC configuration 306 */ 307 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 308 309 #ifndef CONFIG_NET_MULTI 310 #define CONFIG_NET_MULTI 1 311 #endif 312 313 #define CONFIG_GMII 1 /* MII PHY management */ 314 #define CONFIG_MPC83XX_TSEC1 1 315 316 #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" 317 #define CONFIG_MPC83XX_TSEC2 1 318 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" 319 #define TSEC1_PHY_ADDR 0x1c 320 #define TSEC2_PHY_ADDR 4 321 #define TSEC1_PHYIDX 0 322 #define TSEC2_PHYIDX 0 323 324 /* Options are: TSEC[0-1] */ 325 #define CONFIG_ETHPRIME "TSEC1" 326 327 /* 328 * Configure on-board RTC 329 */ 330 #define CONFIG_RTC_DS1337 331 #define CFG_I2C_RTC_ADDR 0x68 332 333 /* 334 * Environment 335 */ 336 #ifndef CFG_RAMBOOT 337 #define CFG_ENV_IS_IN_FLASH 1 338 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 339 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 340 #define CFG_ENV_SIZE 0x2000 341 342 /* Address and size of Redundant Environment Sector */ 343 #else 344 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 345 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 346 #define CFG_ENV_SIZE 0x2000 347 #endif 348 349 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 350 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 351 352 #define CFG_BASE_COMMANDS ( CONFIG_CMD_DFL \ 353 | CFG_CMD_PING \ 354 | CFG_CMD_DHCP \ 355 | CFG_CMD_I2C \ 356 | CFG_CMD_MII \ 357 | CFG_CMD_DATE \ 358 | CFG_CMD_PCI) 359 360 #define CONFIG_CMDLINE_EDITING 1 361 362 #define CFG_RAMBOOT_COMMANDS (CFG_BASE_COMMANDS & \ 363 ~(CFG_CMD_ENV | CFG_CMD_LOADS)) 364 365 #if defined(CFG_RAMBOOT) 366 #define CONFIG_COMMANDS CFG_RAMBOOT_COMMANDS 367 #else 368 #define CONFIG_COMMANDS CFG_BASE_COMMANDS 369 #endif 370 371 #include <cmd_confdefs.h> 372 373 /* 374 * Miscellaneous configurable options 375 */ 376 #define CFG_LONGHELP /* undef to save memory */ 377 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 378 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 379 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 380 381 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 382 #define CFG_MAXARGS 16 /* max number of command args */ 383 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 384 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 385 386 /* 387 * For booting Linux, the board info and command line data 388 * have to be in the first 8 MB of memory, since this is 389 * the maximum mapped by the Linux kernel during initialization. 390 */ 391 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 392 393 /* Cache Configuration */ 394 #define CFG_DCACHE_SIZE 16384 395 #define CFG_CACHELINE_SIZE 32 396 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 397 398 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 399 400 #ifdef CFG_66MHZ 401 402 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 403 /* 0x62040000 */ 404 #define CFG_HRCW_LOW (\ 405 0x20000000 /* reserved, must be set */ |\ 406 HRCWL_DDRCM |\ 407 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 408 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 409 HRCWL_CSB_TO_CLKIN_2X1 |\ 410 HRCWL_CORE_TO_CSB_2X1) 411 412 #elif defined(CFG_33MHZ) 413 414 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 415 /* 0x65040000 */ 416 #define CFG_HRCW_LOW (\ 417 0x20000000 /* reserved, must be set */ |\ 418 HRCWL_DDRCM |\ 419 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 420 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 421 HRCWL_CSB_TO_CLKIN_5X1 |\ 422 HRCWL_CORE_TO_CSB_2X1) 423 424 #endif 425 426 /* 0xa0606c00 */ 427 #define CFG_HRCW_HIGH (\ 428 HRCWH_PCI_HOST |\ 429 HRCWH_PCI1_ARBITER_ENABLE |\ 430 HRCWH_CORE_ENABLE |\ 431 HRCWH_FROM_0X00000100 |\ 432 HRCWH_BOOTSEQ_DISABLE |\ 433 HRCWH_SW_WATCHDOG_DISABLE |\ 434 HRCWH_ROM_LOC_LOCAL_16BIT |\ 435 HRCWH_RL_EXT_LEGACY |\ 436 HRCWH_TSEC1M_IN_RGMII |\ 437 HRCWH_TSEC2M_IN_RGMII |\ 438 HRCWH_BIG_ENDIAN |\ 439 HRCWH_LALE_NORMAL) 440 441 /* System IO Config */ 442 #define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 443 #define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ 444 445 #define CFG_HID0_INIT 0x000000000 446 #define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 447 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 448 449 #define CFG_HID2 HID2_HBE 450 451 /* DDR @ 0x00000000 */ 452 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) 453 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 454 455 /* PCI @ 0x80000000 */ 456 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10) 457 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 458 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 459 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 460 461 /* PCI2 not supported on 8313 */ 462 #define CFG_IBAT3L (0) 463 #define CFG_IBAT3U (0) 464 #define CFG_IBAT4L (0) 465 #define CFG_IBAT4U (0) 466 467 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 468 #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 469 #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 470 471 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 472 #define CFG_IBAT6L (0xF0000000 | BATL_PP_10) 473 #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 474 475 #define CFG_IBAT7L (0) 476 #define CFG_IBAT7U (0) 477 478 #define CFG_DBAT0L CFG_IBAT0L 479 #define CFG_DBAT0U CFG_IBAT0U 480 #define CFG_DBAT1L CFG_IBAT1L 481 #define CFG_DBAT1U CFG_IBAT1U 482 #define CFG_DBAT2L CFG_IBAT2L 483 #define CFG_DBAT2U CFG_IBAT2U 484 #define CFG_DBAT3L CFG_IBAT3L 485 #define CFG_DBAT3U CFG_IBAT3U 486 #define CFG_DBAT4L CFG_IBAT4L 487 #define CFG_DBAT4U CFG_IBAT4U 488 #define CFG_DBAT5L CFG_IBAT5L 489 #define CFG_DBAT5U CFG_IBAT5U 490 #define CFG_DBAT6L CFG_IBAT6L 491 #define CFG_DBAT6U CFG_IBAT6U 492 #define CFG_DBAT7L CFG_IBAT7L 493 #define CFG_DBAT7U CFG_IBAT7U 494 495 /* 496 * Internal Definitions 497 * 498 * Boot Flags 499 */ 500 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 501 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 502 503 /* 504 * Environment Configuration 505 */ 506 #define CONFIG_ENV_OVERWRITE 507 508 #define CONFIG_ETHADDR 00:E0:0C:00:95:01 509 #define CONFIG_HAS_ETH1 510 #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 511 512 #define CONFIG_IPADDR 10.0.0.2 513 #define CONFIG_SERVERIP 10.0.0.1 514 #define CONFIG_GATEWAYIP 10.0.0.1 515 #define CONFIG_NETMASK 255.0.0.0 516 #define CONFIG_NETDEV eth1 517 518 #define CONFIG_HOSTNAME mpc8313erdb 519 #define CONFIG_ROOTPATH /nfs/root/path 520 #define CONFIG_BOOTFILE uImage 521 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 522 #define CONFIG_FDTFILE mpc8313erdb.dtb 523 524 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 525 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 526 #define CONFIG_BAUDRATE 115200 527 528 #define XMK_STR(x) #x 529 #define MK_STR(x) XMK_STR(x) 530 531 #define CONFIG_EXTRA_ENV_SETTINGS \ 532 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 533 "ethprime=TSEC1\0" \ 534 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 535 "tftpflash=tftpboot $loadaddr $uboot; " \ 536 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 537 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 538 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 539 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 540 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 541 "fdtaddr=400000\0" \ 542 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 543 "console=ttyS0\0" \ 544 "setbootargs=setenv bootargs " \ 545 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 546 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 547 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 548 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 549 550 #define CONFIG_NFSBOOTCOMMAND \ 551 "setenv rootdev /dev/nfs;" \ 552 "run setbootargs;" \ 553 "run setipargs;" \ 554 "tftp $loadaddr $bootfile;" \ 555 "tftp $fdtaddr $fdtfile;" \ 556 "bootm $loadaddr - $fdtaddr" 557 558 #define CONFIG_RAMBOOTCOMMAND \ 559 "setenv rootdev /dev/ram;" \ 560 "run setbootargs;" \ 561 "tftp $ramdiskaddr $ramdiskfile;" \ 562 "tftp $loadaddr $bootfile;" \ 563 "tftp $fdtaddr $fdtfile;" \ 564 "bootm $loadaddr $ramdiskaddr $fdtaddr" 565 566 #undef MK_STR 567 #undef XMK_STR 568 569 #endif /* __CONFIG_H */ 570