1 /* 2 * Configuation settings for the Freescale MCF5475 board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5475EVB_H 15 #define _M5475EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 #define CONFIG_MCFUART 25 #define CONFIG_SYS_UART_PORT (0) 26 #define CONFIG_BAUDRATE 115200 27 28 #undef CONFIG_HW_WATCHDOG 29 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 30 31 /* Command line configuration */ 32 #define CONFIG_CMD_CACHE 33 #undef CONFIG_CMD_DATE 34 #define CONFIG_CMD_MII 35 #define CONFIG_CMD_PCI 36 #define CONFIG_CMD_REGINFO 37 38 #define CONFIG_SLTTMR 39 40 #define CONFIG_FSLDMAFEC 41 #ifdef CONFIG_FSLDMAFEC 42 # define CONFIG_MII 1 43 # define CONFIG_MII_INIT 1 44 # define CONFIG_HAS_ETH1 45 46 # define CONFIG_SYS_DMA_USE_INTSRAM 1 47 # define CONFIG_SYS_DISCOVER_PHY 48 # define CONFIG_SYS_RX_ETH_BUFFER 32 49 # define CONFIG_SYS_TX_ETH_BUFFER 48 50 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 51 52 # define CONFIG_SYS_FEC0_PINMUX 0 53 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 54 # define CONFIG_SYS_FEC1_PINMUX 0 55 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 56 57 # define MCFFEC_TOUT_LOOP 50000 58 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 59 # ifndef CONFIG_SYS_DISCOVER_PHY 60 # define FECDUPLEX FULL 61 # define FECSPEED _100BASET 62 # else 63 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 64 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 65 # endif 66 # endif /* CONFIG_SYS_DISCOVER_PHY */ 67 68 # define CONFIG_IPADDR 192.162.1.2 69 # define CONFIG_NETMASK 255.255.255.0 70 # define CONFIG_SERVERIP 192.162.1.1 71 # define CONFIG_GATEWAYIP 192.162.1.1 72 73 #endif 74 75 #ifdef CONFIG_CMD_USB 76 # define CONFIG_USB_OHCI_NEW 77 # define CONFIG_USB_STORAGE 78 79 # ifndef CONFIG_CMD_PCI 80 # define CONFIG_CMD_PCI 81 # endif 82 # define CONFIG_PCI_OHCI 83 # define CONFIG_DOS_PARTITION 84 85 # undef CONFIG_SYS_USB_OHCI_BOARD_INIT 86 # undef CONFIG_SYS_USB_OHCI_CPU_INIT 87 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 88 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 89 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 90 #endif 91 92 /* I2C */ 93 #define CONFIG_SYS_I2C 94 #define CONFIG_SYS_I2C_FSL 95 #define CONFIG_SYS_FSL_I2C_SPEED 80000 96 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 97 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 98 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 99 100 /* PCI */ 101 #ifdef CONFIG_CMD_PCI 102 #define CONFIG_PCI 1 103 #define CONFIG_PCI_PNP 1 104 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 105 106 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 107 108 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 109 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 110 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 111 112 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 113 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 114 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 115 116 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 117 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 118 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 119 #endif 120 121 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 122 #define CONFIG_UDP_CHECKSUM 123 124 #ifdef CONFIG_MCFFEC 125 # define CONFIG_IPADDR 192.162.1.2 126 # define CONFIG_NETMASK 255.255.255.0 127 # define CONFIG_SERVERIP 192.162.1.1 128 # define CONFIG_GATEWAYIP 192.162.1.1 129 #endif /* FEC_ENET */ 130 131 #define CONFIG_HOSTNAME M547xEVB 132 #define CONFIG_EXTRA_ENV_SETTINGS \ 133 "netdev=eth0\0" \ 134 "loadaddr=10000\0" \ 135 "u-boot=u-boot.bin\0" \ 136 "load=tftp ${loadaddr) ${u-boot}\0" \ 137 "upd=run load; run prog\0" \ 138 "prog=prot off bank 1;" \ 139 "era ff800000 ff83ffff;" \ 140 "cp.b ${loadaddr} ff800000 ${filesize};"\ 141 "save\0" \ 142 "" 143 144 #define CONFIG_PRAM 512 /* 512 KB */ 145 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 146 147 #ifdef CONFIG_CMD_KGDB 148 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 149 #else 150 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 151 #endif 152 153 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 154 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 155 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 156 #define CONFIG_SYS_LOAD_ADDR 0x00010000 157 158 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 159 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 160 161 #define CONFIG_SYS_MBAR 0xF0000000 162 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 163 #define CONFIG_SYS_INTSRAMSZ 0x8000 164 165 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 166 167 /* 168 * Low Level Configuration Settings 169 * (address mappings, register initial values, etc.) 170 * You should know what you are doing if you make changes here. 171 */ 172 /*----------------------------------------------------------------------- 173 * Definitions for initial stack pointer and data area (in DPRAM) 174 */ 175 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 176 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 177 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 178 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 179 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 180 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 181 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 182 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 183 184 /*----------------------------------------------------------------------- 185 * Start addresses for the final memory configuration 186 * (Set up by the startup code) 187 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 188 */ 189 #define CONFIG_SYS_SDRAM_BASE 0x00000000 190 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 191 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 192 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 193 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 194 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 195 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 196 #ifdef CONFIG_SYS_DRAMSZ1 197 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 198 #else 199 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 200 #endif 201 202 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 203 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 204 205 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 206 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 207 208 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 209 210 /* Reserve 256 kB for malloc() */ 211 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 212 /* 213 * For booting Linux, the board info and command line data 214 * have to be in the first 8 MB of memory, since this is 215 * the maximum mapped by the Linux kernel during initialization ?? 216 */ 217 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 218 219 /*----------------------------------------------------------------------- 220 * FLASH organization 221 */ 222 #define CONFIG_SYS_FLASH_CFI 223 #ifdef CONFIG_SYS_FLASH_CFI 224 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 225 # define CONFIG_FLASH_CFI_DRIVER 1 226 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 227 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 228 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 229 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 230 #ifdef CONFIG_SYS_NOR1SZ 231 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 232 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 233 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 234 #else 235 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 236 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 237 #endif 238 #endif 239 240 /* Configuration for environment 241 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 242 * First time runing may have env crc error warning if there is 243 * no correct environment on the flash. 244 */ 245 #define CONFIG_ENV_OFFSET 0x40000 246 #define CONFIG_ENV_SECT_SIZE 0x10000 247 #define CONFIG_ENV_IS_IN_FLASH 1 248 249 /*----------------------------------------------------------------------- 250 * Cache Configuration 251 */ 252 #define CONFIG_SYS_CACHELINE_SIZE 16 253 254 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 255 CONFIG_SYS_INIT_RAM_SIZE - 8) 256 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 257 CONFIG_SYS_INIT_RAM_SIZE - 4) 258 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 259 CF_CACR_IDCM) 260 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 261 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 262 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 263 CF_ACR_EN | CF_ACR_SM_ALL) 264 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 265 CF_CACR_IEC | CF_CACR_ICINVA) 266 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 267 CF_CACR_DEC | CF_CACR_DDCM_P | \ 268 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 269 270 /*----------------------------------------------------------------------- 271 * Chipselect bank definitions 272 */ 273 /* 274 * CS0 - NOR Flash 1, 2, 4, or 8MB 275 * CS1 - NOR Flash 276 * CS2 - Available 277 * CS3 - Available 278 * CS4 - Available 279 * CS5 - Available 280 */ 281 #define CONFIG_SYS_CS0_BASE 0xFF800000 282 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 283 #define CONFIG_SYS_CS0_CTRL 0x00101980 284 285 #ifdef CONFIG_SYS_NOR1SZ 286 #define CONFIG_SYS_CS1_BASE 0xE0000000 287 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 288 #define CONFIG_SYS_CS1_CTRL 0x00101D80 289 #endif 290 291 #endif /* _M5475EVB_H */ 292