1 /* 2 * Configuation settings for the Freescale MCF5475 board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5475EVB_H 15 #define _M5475EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 #define CONFIG_MCFUART 25 #define CONFIG_SYS_UART_PORT (0) 26 #define CONFIG_BAUDRATE 115200 27 28 #undef CONFIG_HW_WATCHDOG 29 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 30 31 /* Command line configuration */ 32 #include <config_cmd_default.h> 33 34 #define CONFIG_CMD_CACHE 35 #undef CONFIG_CMD_DATE 36 #define CONFIG_CMD_ELF 37 #define CONFIG_CMD_FLASH 38 #define CONFIG_CMD_I2C 39 #define CONFIG_CMD_MEMORY 40 #define CONFIG_CMD_MISC 41 #define CONFIG_CMD_MII 42 #define CONFIG_CMD_NET 43 #define CONFIG_CMD_PCI 44 #define CONFIG_CMD_PING 45 #define CONFIG_CMD_REGINFO 46 #define CONFIG_CMD_USB 47 48 #define CONFIG_SLTTMR 49 50 #define CONFIG_FSLDMAFEC 51 #ifdef CONFIG_FSLDMAFEC 52 # define CONFIG_MII 1 53 # define CONFIG_MII_INIT 1 54 # define CONFIG_HAS_ETH1 55 56 # define CONFIG_SYS_DMA_USE_INTSRAM 1 57 # define CONFIG_SYS_DISCOVER_PHY 58 # define CONFIG_SYS_RX_ETH_BUFFER 32 59 # define CONFIG_SYS_TX_ETH_BUFFER 48 60 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 61 62 # define CONFIG_SYS_FEC0_PINMUX 0 63 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 64 # define CONFIG_SYS_FEC1_PINMUX 0 65 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 66 67 # define MCFFEC_TOUT_LOOP 50000 68 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 69 # ifndef CONFIG_SYS_DISCOVER_PHY 70 # define FECDUPLEX FULL 71 # define FECSPEED _100BASET 72 # else 73 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 74 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 75 # endif 76 # endif /* CONFIG_SYS_DISCOVER_PHY */ 77 78 # define CONFIG_IPADDR 192.162.1.2 79 # define CONFIG_NETMASK 255.255.255.0 80 # define CONFIG_SERVERIP 192.162.1.1 81 # define CONFIG_GATEWAYIP 192.162.1.1 82 83 #endif 84 85 #ifdef CONFIG_CMD_USB 86 # define CONFIG_USB_OHCI_NEW 87 # define CONFIG_USB_STORAGE 88 89 # ifndef CONFIG_CMD_PCI 90 # define CONFIG_CMD_PCI 91 # endif 92 # define CONFIG_PCI_OHCI 93 # define CONFIG_DOS_PARTITION 94 95 # undef CONFIG_SYS_USB_OHCI_BOARD_INIT 96 # undef CONFIG_SYS_USB_OHCI_CPU_INIT 97 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 98 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 99 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 100 #endif 101 102 /* I2C */ 103 #define CONFIG_SYS_I2C 104 #define CONFIG_SYS_I2C_FSL 105 #define CONFIG_SYS_FSL_I2C_SPEED 80000 106 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 107 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 108 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 109 110 /* PCI */ 111 #ifdef CONFIG_CMD_PCI 112 #define CONFIG_PCI 1 113 #define CONFIG_PCI_PNP 1 114 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 115 116 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 117 118 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 119 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 120 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 121 122 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 123 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 124 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 125 126 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 127 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 128 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 129 #endif 130 131 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 132 #define CONFIG_UDP_CHECKSUM 133 134 #ifdef CONFIG_MCFFEC 135 # define CONFIG_IPADDR 192.162.1.2 136 # define CONFIG_NETMASK 255.255.255.0 137 # define CONFIG_SERVERIP 192.162.1.1 138 # define CONFIG_GATEWAYIP 192.162.1.1 139 #endif /* FEC_ENET */ 140 141 #define CONFIG_HOSTNAME M547xEVB 142 #define CONFIG_EXTRA_ENV_SETTINGS \ 143 "netdev=eth0\0" \ 144 "loadaddr=10000\0" \ 145 "u-boot=u-boot.bin\0" \ 146 "load=tftp ${loadaddr) ${u-boot}\0" \ 147 "upd=run load; run prog\0" \ 148 "prog=prot off bank 1;" \ 149 "era ff800000 ff83ffff;" \ 150 "cp.b ${loadaddr} ff800000 ${filesize};"\ 151 "save\0" \ 152 "" 153 154 #define CONFIG_PRAM 512 /* 512 KB */ 155 #define CONFIG_SYS_PROMPT "-> " 156 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 157 158 #ifdef CONFIG_CMD_KGDB 159 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 160 #else 161 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 162 #endif 163 164 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 165 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 166 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 167 #define CONFIG_SYS_LOAD_ADDR 0x00010000 168 169 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 170 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 171 172 #define CONFIG_SYS_MBAR 0xF0000000 173 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 174 #define CONFIG_SYS_INTSRAMSZ 0x8000 175 176 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 177 178 /* 179 * Low Level Configuration Settings 180 * (address mappings, register initial values, etc.) 181 * You should know what you are doing if you make changes here. 182 */ 183 /*----------------------------------------------------------------------- 184 * Definitions for initial stack pointer and data area (in DPRAM) 185 */ 186 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 187 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 188 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 189 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 190 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 191 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 192 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 193 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 194 195 /*----------------------------------------------------------------------- 196 * Start addresses for the final memory configuration 197 * (Set up by the startup code) 198 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 199 */ 200 #define CONFIG_SYS_SDRAM_BASE 0x00000000 201 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 202 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 203 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 204 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 205 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 206 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 207 #ifdef CONFIG_SYS_DRAMSZ1 208 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 209 #else 210 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 211 #endif 212 213 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 214 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 215 216 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 217 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 218 219 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 220 221 /* Reserve 256 kB for malloc() */ 222 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 223 /* 224 * For booting Linux, the board info and command line data 225 * have to be in the first 8 MB of memory, since this is 226 * the maximum mapped by the Linux kernel during initialization ?? 227 */ 228 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 229 230 /*----------------------------------------------------------------------- 231 * FLASH organization 232 */ 233 #define CONFIG_SYS_FLASH_CFI 234 #ifdef CONFIG_SYS_FLASH_CFI 235 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 236 # define CONFIG_FLASH_CFI_DRIVER 1 237 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 238 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 239 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 240 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 241 #ifdef CONFIG_SYS_NOR1SZ 242 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 243 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 244 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 245 #else 246 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 247 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 248 #endif 249 #endif 250 251 /* Configuration for environment 252 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 253 * First time runing may have env crc error warning if there is 254 * no correct environment on the flash. 255 */ 256 #define CONFIG_ENV_OFFSET 0x40000 257 #define CONFIG_ENV_SECT_SIZE 0x10000 258 #define CONFIG_ENV_IS_IN_FLASH 1 259 260 /*----------------------------------------------------------------------- 261 * Cache Configuration 262 */ 263 #define CONFIG_SYS_CACHELINE_SIZE 16 264 265 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 266 CONFIG_SYS_INIT_RAM_SIZE - 8) 267 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 268 CONFIG_SYS_INIT_RAM_SIZE - 4) 269 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 270 CF_CACR_IDCM) 271 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 272 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 273 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 274 CF_ACR_EN | CF_ACR_SM_ALL) 275 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 276 CF_CACR_IEC | CF_CACR_ICINVA) 277 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 278 CF_CACR_DEC | CF_CACR_DDCM_P | \ 279 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 280 281 /*----------------------------------------------------------------------- 282 * Chipselect bank definitions 283 */ 284 /* 285 * CS0 - NOR Flash 1, 2, 4, or 8MB 286 * CS1 - NOR Flash 287 * CS2 - Available 288 * CS3 - Available 289 * CS4 - Available 290 * CS5 - Available 291 */ 292 #define CONFIG_SYS_CS0_BASE 0xFF800000 293 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 294 #define CONFIG_SYS_CS0_CTRL 0x00101980 295 296 #ifdef CONFIG_SYS_NOR1SZ 297 #define CONFIG_SYS_CS1_BASE 0xE0000000 298 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 299 #define CONFIG_SYS_CS1_CTRL 0x00101D80 300 #endif 301 302 #endif /* _M5475EVB_H */ 303