1 /* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54455EVB_H 15 #define _M54455EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54455EVB /* M54455EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_BAUDRATE 115200 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 #define CONFIG_BOOTP_BOOTPATH 36 #define CONFIG_BOOTP_GATEWAY 37 #define CONFIG_BOOTP_HOSTNAME 38 39 /* Command line configuration */ 40 #define CONFIG_CMD_DATE 41 #define CONFIG_CMD_IDE 42 #define CONFIG_CMD_JFFS2 43 #undef CONFIG_CMD_PCI 44 #define CONFIG_CMD_REGINFO 45 46 /* Network configuration */ 47 #define CONFIG_MCFFEC 48 #ifdef CONFIG_MCFFEC 49 # define CONFIG_MII 1 50 # define CONFIG_MII_INIT 1 51 # define CONFIG_SYS_DISCOVER_PHY 52 # define CONFIG_SYS_RX_ETH_BUFFER 8 53 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 54 55 # define CONFIG_SYS_FEC0_PINMUX 0 56 # define CONFIG_SYS_FEC1_PINMUX 0 57 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 58 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 59 # define MCFFEC_TOUT_LOOP 50000 60 # define CONFIG_HAS_ETH1 61 62 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 63 # define CONFIG_ETHPRIME "FEC0" 64 # define CONFIG_IPADDR 192.162.1.2 65 # define CONFIG_NETMASK 255.255.255.0 66 # define CONFIG_SERVERIP 192.162.1.1 67 # define CONFIG_GATEWAYIP 192.162.1.1 68 69 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 70 # ifndef CONFIG_SYS_DISCOVER_PHY 71 # define FECDUPLEX FULL 72 # define FECSPEED _100BASET 73 # else 74 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 75 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 76 # endif 77 # endif /* CONFIG_SYS_DISCOVER_PHY */ 78 #endif 79 80 #define CONFIG_HOSTNAME M54455EVB 81 #ifdef CONFIG_SYS_STMICRO_BOOT 82 /* ST Micro serial flash */ 83 #define CONFIG_SYS_LOAD_ADDR2 0x40010013 84 #define CONFIG_EXTRA_ENV_SETTINGS \ 85 "netdev=eth0\0" \ 86 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 87 "loadaddr=0x40010000\0" \ 88 "sbfhdr=sbfhdr.bin\0" \ 89 "uboot=u-boot.bin\0" \ 90 "load=tftp ${loadaddr} ${sbfhdr};" \ 91 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 92 "upd=run load; run prog\0" \ 93 "prog=sf probe 0:1 1000000 3;" \ 94 "sf erase 0 30000;" \ 95 "sf write ${loadaddr} 0 0x30000;" \ 96 "save\0" \ 97 "" 98 #else 99 /* Atmel and Intel */ 100 #ifdef CONFIG_SYS_ATMEL_BOOT 101 # define CONFIG_SYS_UBOOT_END 0x0403FFFF 102 #elif defined(CONFIG_SYS_INTEL_BOOT) 103 # define CONFIG_SYS_UBOOT_END 0x3FFFF 104 #endif 105 #define CONFIG_EXTRA_ENV_SETTINGS \ 106 "netdev=eth0\0" \ 107 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 108 "loadaddr=0x40010000\0" \ 109 "uboot=u-boot.bin\0" \ 110 "load=tftp ${loadaddr} ${uboot}\0" \ 111 "upd=run load; run prog\0" \ 112 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 113 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 114 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 115 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 116 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 117 " ${filesize}; save\0" \ 118 "" 119 #endif 120 121 /* ATA configuration */ 122 #define CONFIG_ISO_PARTITION 123 #define CONFIG_IDE_RESET 1 124 #define CONFIG_IDE_PREINIT 1 125 #define CONFIG_ATAPI 126 #undef CONFIG_LBA48 127 128 #define CONFIG_SYS_IDE_MAXBUS 1 129 #define CONFIG_SYS_IDE_MAXDEVICE 2 130 131 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 132 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 133 134 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 135 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 136 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 137 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 138 139 /* Realtime clock */ 140 #define CONFIG_MCFRTC 141 #undef RTC_DEBUG 142 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 143 144 /* Timer */ 145 #define CONFIG_MCFTMR 146 #undef CONFIG_MCFPIT 147 148 /* I2c */ 149 #define CONFIG_SYS_I2C 150 #define CONFIG_SYS_I2C_FSL 151 #define CONFIG_SYS_FSL_I2C_SPEED 80000 152 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 153 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 154 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 155 156 /* DSPI and Serial Flash */ 157 #define CONFIG_CF_SPI 158 #define CONFIG_CF_DSPI 159 #define CONFIG_HARD_SPI 160 #define CONFIG_SYS_SBFHDR_SIZE 0x13 161 #ifdef CONFIG_CMD_SPI 162 163 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 164 DSPI_CTAR_PCSSCK_1CLK | \ 165 DSPI_CTAR_PASC(0) | \ 166 DSPI_CTAR_PDT(0) | \ 167 DSPI_CTAR_CSSCK(0) | \ 168 DSPI_CTAR_ASC(0) | \ 169 DSPI_CTAR_DT(1)) 170 #endif 171 172 /* PCI */ 173 #ifdef CONFIG_CMD_PCI 174 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 175 176 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 177 178 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 179 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 180 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 181 182 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 183 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 184 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 185 186 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 187 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 188 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 189 #endif 190 191 /* FPGA - Spartan 2 */ 192 /* experiment 193 #define CONFIG_FPGA 194 #define CONFIG_FPGA_COUNT 1 195 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 196 #define CONFIG_SYS_FPGA_CHECK_CTRLC 197 */ 198 199 /* Input, PCI, Flexbus, and VCO */ 200 #define CONFIG_EXTRA_CLOCK 201 202 #define CONFIG_PRAM 2048 /* 2048 KB */ 203 204 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 205 206 #if defined(CONFIG_CMD_KGDB) 207 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 208 #else 209 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 210 #endif 211 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 212 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 213 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 214 215 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 216 217 #define CONFIG_SYS_MBAR 0xFC000000 218 219 /* 220 * Low Level Configuration Settings 221 * (address mappings, register initial values, etc.) 222 * You should know what you are doing if you make changes here. 223 */ 224 225 /*----------------------------------------------------------------------- 226 * Definitions for initial stack pointer and data area (in DPRAM) 227 */ 228 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 229 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 230 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 231 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 232 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 233 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 234 235 /*----------------------------------------------------------------------- 236 * Start addresses for the final memory configuration 237 * (Set up by the startup code) 238 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 239 */ 240 #define CONFIG_SYS_SDRAM_BASE 0x40000000 241 #define CONFIG_SYS_SDRAM_BASE1 0x48000000 242 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ 243 #define CONFIG_SYS_SDRAM_CFG1 0x65311610 244 #define CONFIG_SYS_SDRAM_CFG2 0x59670000 245 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 246 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 247 #define CONFIG_SYS_SDRAM_MODE 0x00010033 248 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA 249 250 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 251 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 252 253 #ifdef CONFIG_CF_SBF 254 # define CONFIG_SERIAL_BOOT 255 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 256 #else 257 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 258 #endif 259 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 260 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 261 262 /* Reserve 256 kB for malloc() */ 263 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 264 265 /* 266 * For booting Linux, the board info and command line data 267 * have to be in the first 8 MB of memory, since this is 268 * the maximum mapped by the Linux kernel during initialization ?? 269 */ 270 /* Initial Memory map for Linux */ 271 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 272 273 /* 274 * Configuration for environment 275 * Environment is not embedded in u-boot. First time runing may have env 276 * crc error warning if there is no correct environment on the flash. 277 */ 278 #ifdef CONFIG_CF_SBF 279 # define CONFIG_ENV_IS_IN_SPI_FLASH 280 # define CONFIG_ENV_SPI_CS 1 281 #else 282 # define CONFIG_ENV_IS_IN_FLASH 1 283 #endif 284 #undef CONFIG_ENV_OVERWRITE 285 286 /*----------------------------------------------------------------------- 287 * FLASH organization 288 */ 289 #ifdef CONFIG_SYS_STMICRO_BOOT 290 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 291 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE 292 # define CONFIG_ENV_OFFSET 0x30000 293 # define CONFIG_ENV_SIZE 0x2000 294 # define CONFIG_ENV_SECT_SIZE 0x10000 295 #endif 296 #ifdef CONFIG_SYS_ATMEL_BOOT 297 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 298 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 299 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 300 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 301 # define CONFIG_ENV_SIZE 0x2000 302 # define CONFIG_ENV_SECT_SIZE 0x10000 303 #endif 304 #ifdef CONFIG_SYS_INTEL_BOOT 305 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 306 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 307 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 308 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 309 # define CONFIG_ENV_SIZE 0x2000 310 # define CONFIG_ENV_SECT_SIZE 0x20000 311 #endif 312 313 #define CONFIG_SYS_FLASH_CFI 314 #ifdef CONFIG_SYS_FLASH_CFI 315 316 # define CONFIG_FLASH_CFI_DRIVER 1 317 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 318 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 319 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 320 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 321 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 322 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 323 # define CONFIG_SYS_FLASH_CHECKSUM 324 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 325 # define CONFIG_FLASH_CFI_LEGACY 326 327 #ifdef CONFIG_FLASH_CFI_LEGACY 328 # define CONFIG_SYS_ATMEL_REGION 4 329 # define CONFIG_SYS_ATMEL_TOTALSECT 11 330 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 331 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 332 #endif 333 #endif 334 335 /* 336 * This is setting for JFFS2 support in u-boot. 337 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 338 */ 339 #ifdef CONFIG_CMD_JFFS2 340 #ifdef CF_STMICRO_BOOT 341 # define CONFIG_JFFS2_DEV "nor1" 342 # define CONFIG_JFFS2_PART_SIZE 0x01000000 343 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) 344 #endif 345 #ifdef CONFIG_SYS_ATMEL_BOOT 346 # define CONFIG_JFFS2_DEV "nor1" 347 # define CONFIG_JFFS2_PART_SIZE 0x01000000 348 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) 349 #endif 350 #ifdef CONFIG_SYS_INTEL_BOOT 351 # define CONFIG_JFFS2_DEV "nor0" 352 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 353 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 354 #endif 355 #endif 356 357 /*----------------------------------------------------------------------- 358 * Cache Configuration 359 */ 360 #define CONFIG_SYS_CACHELINE_SIZE 16 361 362 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 363 CONFIG_SYS_INIT_RAM_SIZE - 8) 364 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 365 CONFIG_SYS_INIT_RAM_SIZE - 4) 366 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 367 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 368 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 369 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 370 CF_ACR_EN | CF_ACR_SM_ALL) 371 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 372 CF_CACR_ICINVA | CF_CACR_EUSP) 373 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 374 CF_CACR_DEC | CF_CACR_DDCM_P | \ 375 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 376 377 /*----------------------------------------------------------------------- 378 * Memory bank definitions 379 */ 380 /* 381 * CS0 - NOR Flash 1, 2, 4, or 8MB 382 * CS1 - CompactFlash and registers 383 * CS2 - CPLD 384 * CS3 - FPGA 385 * CS4 - Available 386 * CS5 - Available 387 */ 388 389 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) 390 /* Atmel Flash */ 391 #define CONFIG_SYS_CS0_BASE 0x04000000 392 #define CONFIG_SYS_CS0_MASK 0x00070001 393 #define CONFIG_SYS_CS0_CTRL 0x00001140 394 /* Intel Flash */ 395 #define CONFIG_SYS_CS1_BASE 0x00000000 396 #define CONFIG_SYS_CS1_MASK 0x01FF0001 397 #define CONFIG_SYS_CS1_CTRL 0x00000D60 398 399 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE 400 #else 401 /* Intel Flash */ 402 #define CONFIG_SYS_CS0_BASE 0x00000000 403 #define CONFIG_SYS_CS0_MASK 0x01FF0001 404 #define CONFIG_SYS_CS0_CTRL 0x00000D60 405 /* Atmel Flash */ 406 #define CONFIG_SYS_CS1_BASE 0x04000000 407 #define CONFIG_SYS_CS1_MASK 0x00070001 408 #define CONFIG_SYS_CS1_CTRL 0x00001140 409 410 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE 411 #endif 412 413 /* CPLD */ 414 #define CONFIG_SYS_CS2_BASE 0x08000000 415 #define CONFIG_SYS_CS2_MASK 0x00070001 416 #define CONFIG_SYS_CS2_CTRL 0x003f1140 417 418 /* FPGA */ 419 #define CONFIG_SYS_CS3_BASE 0x09000000 420 #define CONFIG_SYS_CS3_MASK 0x00070001 421 #define CONFIG_SYS_CS3_CTRL 0x00000020 422 423 #endif /* _M54455EVB_H */ 424