1 /* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M54455EVB_H 31 #define _M54455EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF5445x /* define processor family */ 38 #define CONFIG_M54455 /* define processor type */ 39 #define CONFIG_M54455EVB /* M54455EVB board */ 40 41 #define CONFIG_MCFUART 42 #define CFG_UART_PORT (0) 43 #define CONFIG_BAUDRATE 115200 44 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 45 46 #undef CONFIG_WATCHDOG 47 48 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 49 50 /* 51 * BOOTP options 52 */ 53 #define CONFIG_BOOTP_BOOTFILESIZE 54 #define CONFIG_BOOTP_BOOTPATH 55 #define CONFIG_BOOTP_GATEWAY 56 #define CONFIG_BOOTP_HOSTNAME 57 58 /* Command line configuration */ 59 #include <config_cmd_default.h> 60 61 #define CONFIG_CMD_BOOTD 62 #define CONFIG_CMD_CACHE 63 #define CONFIG_CMD_DATE 64 #define CONFIG_CMD_DHCP 65 #define CONFIG_CMD_ELF 66 #define CONFIG_CMD_EXT2 67 #define CONFIG_CMD_FAT 68 #define CONFIG_CMD_FLASH 69 #define CONFIG_CMD_I2C 70 #define CONFIG_CMD_IDE 71 #define CONFIG_CMD_JFFS2 72 #define CONFIG_CMD_MEMORY 73 #define CONFIG_CMD_MISC 74 #define CONFIG_CMD_MII 75 #define CONFIG_CMD_NET 76 #undef CONFIG_CMD_PCI 77 #define CONFIG_CMD_PING 78 #define CONFIG_CMD_REGINFO 79 #define CONFIG_CMD_SPI 80 81 #undef CONFIG_CMD_LOADB 82 #undef CONFIG_CMD_LOADS 83 84 /* Network configuration */ 85 #define CONFIG_MCFFEC 86 #ifdef CONFIG_MCFFEC 87 # define CONFIG_NET_MULTI 1 88 # define CONFIG_MII 1 89 # define CONFIG_MII_INIT 1 90 # define CFG_DISCOVER_PHY 91 # define CFG_RX_ETH_BUFFER 8 92 # define CFG_FAULT_ECHO_LINK_DOWN 93 94 # define CFG_FEC0_PINMUX 0 95 # define CFG_FEC1_PINMUX 0 96 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE 97 # define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE 98 # define MCFFEC_TOUT_LOOP 50000 99 # define CONFIG_HAS_ETH1 100 101 # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 102 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 103 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 104 # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 105 # define CONFIG_ETHPRIME "FEC0" 106 # define CONFIG_IPADDR 192.162.1.2 107 # define CONFIG_NETMASK 255.255.255.0 108 # define CONFIG_SERVERIP 192.162.1.1 109 # define CONFIG_GATEWAYIP 192.162.1.1 110 # define CONFIG_OVERWRITE_ETHADDR_ONCE 111 112 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ 113 # ifndef CFG_DISCOVER_PHY 114 # define FECDUPLEX FULL 115 # define FECSPEED _100BASET 116 # else 117 # ifndef CFG_FAULT_ECHO_LINK_DOWN 118 # define CFG_FAULT_ECHO_LINK_DOWN 119 # endif 120 # endif /* CFG_DISCOVER_PHY */ 121 #endif 122 123 #define CONFIG_HOSTNAME M54455EVB 124 #define CONFIG_EXTRA_ENV_SETTINGS \ 125 "netdev=eth0\0" \ 126 "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ 127 "loadaddr=40010000\0" \ 128 "u-boot=u-boot.bin\0" \ 129 "load=tftp ${loadaddr) ${u-boot}\0" \ 130 "upd=run load; run prog\0" \ 131 "prog=prot off 4000000 402ffff;" \ 132 "era 4000000 402ffff;" \ 133 "cp.b ${loadaddr} 0 ${filesize};" \ 134 "save\0" \ 135 "" 136 137 /* ATA configuration */ 138 #define CONFIG_ISO_PARTITION 139 #define CONFIG_DOS_PARTITION 140 #define CONFIG_IDE_RESET 1 141 #define CONFIG_IDE_PREINIT 1 142 #define CONFIG_ATAPI 143 #undef CONFIG_LBA48 144 145 #define CFG_IDE_MAXBUS 1 146 #define CFG_IDE_MAXDEVICE 2 147 148 #define CFG_ATA_BASE_ADDR 0x90000000 149 #define CFG_ATA_IDE0_OFFSET 0 150 151 #define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 152 #define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 153 #define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 154 #define CFG_ATA_STRIDE 4 /* Interval between registers */ 155 #define _IO_BASE 0 156 157 /* Realtime clock */ 158 #define CONFIG_MCFRTC 159 #undef RTC_DEBUG 160 #define CFG_RTC_OSCILLATOR (32 * CFG_HZ) 161 162 /* Timer */ 163 #define CONFIG_MCFTMR 164 #undef CONFIG_MCFPIT 165 166 /* I2c */ 167 #define CONFIG_FSL_I2C 168 #define CONFIG_HARD_I2C /* I2C with hardware support */ 169 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 170 #define CFG_I2C_SPEED 80000 /* I2C speed and slave address */ 171 #define CFG_I2C_SLAVE 0x7F 172 #define CFG_I2C_OFFSET 0x58000 173 #define CFG_IMMR CFG_MBAR 174 175 /* DSPI and Serial Flash */ 176 #define CONFIG_CF_DSPI 177 #define CONFIG_HARD_SPI 178 #ifdef CONFIG_CMD_SPI 179 # define CFG_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ 180 DSPI_DCTAR_CPOL | \ 181 DSPI_DCTAR_CPHA | \ 182 DSPI_DCTAR_PCSSCK_1CLK | \ 183 DSPI_DCTAR_PASC(0) | \ 184 DSPI_DCTAR_PDT(0) | \ 185 DSPI_DCTAR_CSSCK(0) | \ 186 DSPI_DCTAR_ASC(0) | \ 187 DSPI_DCTAR_PBR(0) | \ 188 DSPI_DCTAR_DT(1) | \ 189 DSPI_DCTAR_BR(1)) 190 #endif 191 192 /* PCI */ 193 #ifdef CONFIG_CMD_PCI 194 #define CONFIG_PCI 1 195 #define CONFIG_PCI_PNP 1 196 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 197 198 #define CFG_PCI_CACHE_LINE_SIZE 4 199 200 #define CFG_PCI_MEM_BUS 0xA0000000 201 #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS 202 #define CFG_PCI_MEM_SIZE 0x10000000 203 204 #define CFG_PCI_IO_BUS 0xB1000000 205 #define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS 206 #define CFG_PCI_IO_SIZE 0x01000000 207 208 #define CFG_PCI_CFG_BUS 0xB0000000 209 #define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS 210 #define CFG_PCI_CFG_SIZE 0x01000000 211 #endif 212 213 /* FPGA - Spartan 2 */ 214 /* experiment 215 #define CONFIG_FPGA CFG_SPARTAN3 216 #define CONFIG_FPGA_COUNT 1 217 #define CFG_FPGA_PROG_FEEDBACK 218 #define CFG_FPGA_CHECK_CTRLC 219 */ 220 221 /* Input, PCI, Flexbus, and VCO */ 222 #define CONFIG_EXTRA_CLOCK 223 224 #define CONFIG_PRAM 512 /* 512 KB */ 225 226 #define CFG_PROMPT "-> " 227 #define CFG_LONGHELP /* undef to save memory */ 228 229 #if defined(CONFIG_CMD_KGDB) 230 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 231 #else 232 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 233 #endif 234 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 235 #define CFG_MAXARGS 16 /* max number of command args */ 236 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 237 238 #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000) 239 240 #define CFG_HZ 1000 241 242 #define CFG_MBAR 0xFC000000 243 244 /* 245 * Low Level Configuration Settings 246 * (address mappings, register initial values, etc.) 247 * You should know what you are doing if you make changes here. 248 */ 249 250 /*----------------------------------------------------------------------- 251 * Definitions for initial stack pointer and data area (in DPRAM) 252 */ 253 #define CFG_INIT_RAM_ADDR 0x80000000 254 #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ 255 #define CFG_INIT_RAM_CTRL 0x221 256 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 257 #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16) 258 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 259 260 /*----------------------------------------------------------------------- 261 * Start addresses for the final memory configuration 262 * (Set up by the startup code) 263 * Please note that CFG_SDRAM_BASE _must_ start at 0 264 */ 265 #define CFG_SDRAM_BASE 0x40000000 266 #define CFG_SDRAM_BASE1 0x48000000 267 #define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */ 268 #define CFG_SDRAM_CFG1 0x65311610 269 #define CFG_SDRAM_CFG2 0x59670000 270 #define CFG_SDRAM_CTRL 0xEA0B2000 271 #define CFG_SDRAM_EMOD 0x40010000 272 #define CFG_SDRAM_MODE 0x00010033 273 274 #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 275 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) 276 277 #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) 278 #define CFG_BOOTPARAMS_LEN 64*1024 279 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 280 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 281 282 /* 283 * For booting Linux, the board info and command line data 284 * have to be in the first 8 MB of memory, since this is 285 * the maximum mapped by the Linux kernel during initialization ?? 286 */ 287 /* Initial Memory map for Linux */ 288 #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) 289 290 /* Configuration for environment 291 * Environment is embedded in u-boot in the second sector of the flash 292 */ 293 #define CFG_ENV_IS_IN_FLASH 1 294 #define CONFIG_ENV_OVERWRITE 1 295 #undef CFG_ENV_IS_EMBEDDED 296 297 /*----------------------------------------------------------------------- 298 * FLASH organization 299 */ 300 #ifdef CFG_ATMEL_BOOT 301 # define CFG_FLASH_BASE CFG_CS0_BASE 302 # define CFG_FLASH0_BASE CFG_CS0_BASE 303 # define CFG_FLASH1_BASE CFG_CS1_BASE 304 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) 305 # define CFG_ENV_SECT_SIZE 0x2000 306 #else 307 # define CFG_FLASH_BASE CFG_CS0_BASE 308 # define CFG_FLASH0_BASE CFG_CS0_BASE 309 # define CFG_FLASH1_BASE CFG_CS1_BASE 310 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) 311 # define CFG_ENV_SECT_SIZE 0x20000 312 #endif 313 314 #define CFG_FLASH_CFI 315 #ifdef CFG_FLASH_CFI 316 317 # define CONFIG_FLASH_CFI_DRIVER 1 318 # define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 319 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT 320 # define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ 321 # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 322 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 323 # define CFG_FLASH_CHECKSUM 324 # define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE } 325 # define CONFIG_FLASH_CFI_LEGACY 326 327 #ifdef CONFIG_FLASH_CFI_LEGACY 328 # define CFG_ATMEL_REGION 4 329 # define CFG_ATMEL_TOTALSECT 11 330 # define CFG_ATMEL_SECT {1, 2, 1, 7} 331 # define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 332 #endif 333 #endif 334 335 #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 336 #define CFG_FLASH_CHECKSUM 337 338 /* 339 * This is setting for JFFS2 support in u-boot. 340 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 341 */ 342 #ifdef CFG_ATMEL_BOOT 343 # define CONFIG_JFFS2_DEV "nor1" 344 # define CONFIG_JFFS2_PART_SIZE 0x01000000 345 # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH1_BASE + 0x500000) 346 #else 347 # define CONFIG_JFFS2_DEV "nor0" 348 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 349 # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) 350 #endif 351 352 /*----------------------------------------------------------------------- 353 * Cache Configuration 354 */ 355 #define CFG_CACHELINE_SIZE 16 356 357 /*----------------------------------------------------------------------- 358 * Memory bank definitions 359 */ 360 /* 361 * CS0 - NOR Flash 1, 2, 4, or 8MB 362 * CS1 - CompactFlash and registers 363 * CS2 - CPLD 364 * CS3 - FPGA 365 * CS4 - Available 366 * CS5 - Available 367 */ 368 369 #ifdef CFG_ATMEL_BOOT 370 /* Atmel Flash */ 371 #define CFG_CS0_BASE 0x04000000 372 #define CFG_CS0_MASK 0x00070001 373 #define CFG_CS0_CTRL 0x00001140 374 /* Intel Flash */ 375 #define CFG_CS1_BASE 0x00000000 376 #define CFG_CS1_MASK 0x01FF0001 377 #define CFG_CS1_CTRL 0x00000D60 378 379 #define CFG_ATMEL_BASE CFG_CS0_BASE 380 #else 381 /* Intel Flash */ 382 #define CFG_CS0_BASE 0x00000000 383 #define CFG_CS0_MASK 0x01FF0001 384 #define CFG_CS0_CTRL 0x00000D60 385 /* Atmel Flash */ 386 #define CFG_CS1_BASE 0x04000000 387 #define CFG_CS1_MASK 0x00070001 388 #define CFG_CS1_CTRL 0x00001140 389 390 #define CFG_ATMEL_BASE CFG_CS1_BASE 391 #endif 392 393 /* CPLD */ 394 #define CFG_CS2_BASE 0x08000000 395 #define CFG_CS2_MASK 0x00070001 396 #define CFG_CS2_CTRL 0x003f1140 397 398 /* FPGA */ 399 #define CFG_CS3_BASE 0x09000000 400 #define CFG_CS3_MASK 0x00070001 401 #define CFG_CS3_CTRL 0x00000020 402 403 #endif /* _M54455EVB_H */ 404