1 /* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54455EVB_H 15 #define _M54455EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54455EVB /* M54455EVB board */ 22 23 #define CONFIG_DISPLAY_BOARDINFO 24 25 #define CONFIG_MCFUART 26 #define CONFIG_SYS_UART_PORT (0) 27 #define CONFIG_BAUDRATE 115200 28 29 #undef CONFIG_WATCHDOG 30 31 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 32 33 /* 34 * BOOTP options 35 */ 36 #define CONFIG_BOOTP_BOOTFILESIZE 37 #define CONFIG_BOOTP_BOOTPATH 38 #define CONFIG_BOOTP_GATEWAY 39 #define CONFIG_BOOTP_HOSTNAME 40 41 /* Command line configuration */ 42 #define CONFIG_CMD_CACHE 43 #define CONFIG_CMD_DATE 44 #define CONFIG_CMD_EXT2 45 #define CONFIG_CMD_FAT 46 #define CONFIG_CMD_IDE 47 #define CONFIG_CMD_JFFS2 48 #define CONFIG_CMD_MII 49 #undef CONFIG_CMD_PCI 50 #define CONFIG_CMD_REGINFO 51 52 /* Network configuration */ 53 #define CONFIG_MCFFEC 54 #ifdef CONFIG_MCFFEC 55 # define CONFIG_MII 1 56 # define CONFIG_MII_INIT 1 57 # define CONFIG_SYS_DISCOVER_PHY 58 # define CONFIG_SYS_RX_ETH_BUFFER 8 59 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 60 61 # define CONFIG_SYS_FEC0_PINMUX 0 62 # define CONFIG_SYS_FEC1_PINMUX 0 63 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 64 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 65 # define MCFFEC_TOUT_LOOP 50000 66 # define CONFIG_HAS_ETH1 67 68 # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 69 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 70 # define CONFIG_ETHPRIME "FEC0" 71 # define CONFIG_IPADDR 192.162.1.2 72 # define CONFIG_NETMASK 255.255.255.0 73 # define CONFIG_SERVERIP 192.162.1.1 74 # define CONFIG_GATEWAYIP 192.162.1.1 75 76 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 77 # ifndef CONFIG_SYS_DISCOVER_PHY 78 # define FECDUPLEX FULL 79 # define FECSPEED _100BASET 80 # else 81 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 82 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 83 # endif 84 # endif /* CONFIG_SYS_DISCOVER_PHY */ 85 #endif 86 87 #define CONFIG_HOSTNAME M54455EVB 88 #ifdef CONFIG_SYS_STMICRO_BOOT 89 /* ST Micro serial flash */ 90 #define CONFIG_SYS_LOAD_ADDR2 0x40010013 91 #define CONFIG_EXTRA_ENV_SETTINGS \ 92 "netdev=eth0\0" \ 93 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 94 "loadaddr=0x40010000\0" \ 95 "sbfhdr=sbfhdr.bin\0" \ 96 "uboot=u-boot.bin\0" \ 97 "load=tftp ${loadaddr} ${sbfhdr};" \ 98 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 99 "upd=run load; run prog\0" \ 100 "prog=sf probe 0:1 1000000 3;" \ 101 "sf erase 0 30000;" \ 102 "sf write ${loadaddr} 0 0x30000;" \ 103 "save\0" \ 104 "" 105 #else 106 /* Atmel and Intel */ 107 #ifdef CONFIG_SYS_ATMEL_BOOT 108 # define CONFIG_SYS_UBOOT_END 0x0403FFFF 109 #elif defined(CONFIG_SYS_INTEL_BOOT) 110 # define CONFIG_SYS_UBOOT_END 0x3FFFF 111 #endif 112 #define CONFIG_EXTRA_ENV_SETTINGS \ 113 "netdev=eth0\0" \ 114 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 115 "loadaddr=0x40010000\0" \ 116 "uboot=u-boot.bin\0" \ 117 "load=tftp ${loadaddr} ${uboot}\0" \ 118 "upd=run load; run prog\0" \ 119 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 120 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 121 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 122 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 123 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 124 " ${filesize}; save\0" \ 125 "" 126 #endif 127 128 /* ATA configuration */ 129 #define CONFIG_ISO_PARTITION 130 #define CONFIG_DOS_PARTITION 131 #define CONFIG_IDE_RESET 1 132 #define CONFIG_IDE_PREINIT 1 133 #define CONFIG_ATAPI 134 #undef CONFIG_LBA48 135 136 #define CONFIG_SYS_IDE_MAXBUS 1 137 #define CONFIG_SYS_IDE_MAXDEVICE 2 138 139 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 140 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 141 142 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 143 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 144 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 145 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 146 147 /* Realtime clock */ 148 #define CONFIG_MCFRTC 149 #undef RTC_DEBUG 150 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 151 152 /* Timer */ 153 #define CONFIG_MCFTMR 154 #undef CONFIG_MCFPIT 155 156 /* I2c */ 157 #define CONFIG_SYS_I2C 158 #define CONFIG_SYS_I2C_FSL 159 #define CONFIG_SYS_FSL_I2C_SPEED 80000 160 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 161 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 162 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 163 164 /* DSPI and Serial Flash */ 165 #define CONFIG_CF_SPI 166 #define CONFIG_CF_DSPI 167 #define CONFIG_HARD_SPI 168 #define CONFIG_SYS_SBFHDR_SIZE 0x13 169 #ifdef CONFIG_CMD_SPI 170 171 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 172 DSPI_CTAR_PCSSCK_1CLK | \ 173 DSPI_CTAR_PASC(0) | \ 174 DSPI_CTAR_PDT(0) | \ 175 DSPI_CTAR_CSSCK(0) | \ 176 DSPI_CTAR_ASC(0) | \ 177 DSPI_CTAR_DT(1)) 178 #endif 179 180 /* PCI */ 181 #ifdef CONFIG_CMD_PCI 182 #define CONFIG_PCI 1 183 #define CONFIG_PCI_PNP 1 184 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 185 186 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 187 188 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 189 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 190 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 191 192 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 193 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 194 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 195 196 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 197 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 198 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 199 #endif 200 201 /* FPGA - Spartan 2 */ 202 /* experiment 203 #define CONFIG_FPGA 204 #define CONFIG_FPGA_COUNT 1 205 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 206 #define CONFIG_SYS_FPGA_CHECK_CTRLC 207 */ 208 209 /* Input, PCI, Flexbus, and VCO */ 210 #define CONFIG_EXTRA_CLOCK 211 212 #define CONFIG_PRAM 2048 /* 2048 KB */ 213 214 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 215 216 #if defined(CONFIG_CMD_KGDB) 217 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 218 #else 219 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 220 #endif 221 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 222 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 223 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 224 225 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 226 227 #define CONFIG_SYS_MBAR 0xFC000000 228 229 /* 230 * Low Level Configuration Settings 231 * (address mappings, register initial values, etc.) 232 * You should know what you are doing if you make changes here. 233 */ 234 235 /*----------------------------------------------------------------------- 236 * Definitions for initial stack pointer and data area (in DPRAM) 237 */ 238 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 239 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 240 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 241 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 242 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 243 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 244 245 /*----------------------------------------------------------------------- 246 * Start addresses for the final memory configuration 247 * (Set up by the startup code) 248 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 249 */ 250 #define CONFIG_SYS_SDRAM_BASE 0x40000000 251 #define CONFIG_SYS_SDRAM_BASE1 0x48000000 252 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ 253 #define CONFIG_SYS_SDRAM_CFG1 0x65311610 254 #define CONFIG_SYS_SDRAM_CFG2 0x59670000 255 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 256 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 257 #define CONFIG_SYS_SDRAM_MODE 0x00010033 258 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA 259 260 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 261 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 262 263 #ifdef CONFIG_CF_SBF 264 # define CONFIG_SERIAL_BOOT 265 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 266 #else 267 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 268 #endif 269 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 270 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 271 272 /* Reserve 256 kB for malloc() */ 273 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 274 275 /* 276 * For booting Linux, the board info and command line data 277 * have to be in the first 8 MB of memory, since this is 278 * the maximum mapped by the Linux kernel during initialization ?? 279 */ 280 /* Initial Memory map for Linux */ 281 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 282 283 /* 284 * Configuration for environment 285 * Environment is not embedded in u-boot. First time runing may have env 286 * crc error warning if there is no correct environment on the flash. 287 */ 288 #ifdef CONFIG_CF_SBF 289 # define CONFIG_ENV_IS_IN_SPI_FLASH 290 # define CONFIG_ENV_SPI_CS 1 291 #else 292 # define CONFIG_ENV_IS_IN_FLASH 1 293 #endif 294 #undef CONFIG_ENV_OVERWRITE 295 296 /*----------------------------------------------------------------------- 297 * FLASH organization 298 */ 299 #ifdef CONFIG_SYS_STMICRO_BOOT 300 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 301 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE 302 # define CONFIG_ENV_OFFSET 0x30000 303 # define CONFIG_ENV_SIZE 0x2000 304 # define CONFIG_ENV_SECT_SIZE 0x10000 305 #endif 306 #ifdef CONFIG_SYS_ATMEL_BOOT 307 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 308 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 309 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 310 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 311 # define CONFIG_ENV_SIZE 0x2000 312 # define CONFIG_ENV_SECT_SIZE 0x10000 313 #endif 314 #ifdef CONFIG_SYS_INTEL_BOOT 315 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 316 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 317 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 318 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 319 # define CONFIG_ENV_SIZE 0x2000 320 # define CONFIG_ENV_SECT_SIZE 0x20000 321 #endif 322 323 #define CONFIG_SYS_FLASH_CFI 324 #ifdef CONFIG_SYS_FLASH_CFI 325 326 # define CONFIG_FLASH_CFI_DRIVER 1 327 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 328 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 329 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 330 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 331 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 332 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 333 # define CONFIG_SYS_FLASH_CHECKSUM 334 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 335 # define CONFIG_FLASH_CFI_LEGACY 336 337 #ifdef CONFIG_FLASH_CFI_LEGACY 338 # define CONFIG_SYS_ATMEL_REGION 4 339 # define CONFIG_SYS_ATMEL_TOTALSECT 11 340 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 341 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 342 #endif 343 #endif 344 345 /* 346 * This is setting for JFFS2 support in u-boot. 347 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 348 */ 349 #ifdef CONFIG_CMD_JFFS2 350 #ifdef CF_STMICRO_BOOT 351 # define CONFIG_JFFS2_DEV "nor1" 352 # define CONFIG_JFFS2_PART_SIZE 0x01000000 353 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) 354 #endif 355 #ifdef CONFIG_SYS_ATMEL_BOOT 356 # define CONFIG_JFFS2_DEV "nor1" 357 # define CONFIG_JFFS2_PART_SIZE 0x01000000 358 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) 359 #endif 360 #ifdef CONFIG_SYS_INTEL_BOOT 361 # define CONFIG_JFFS2_DEV "nor0" 362 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 363 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 364 #endif 365 #endif 366 367 /*----------------------------------------------------------------------- 368 * Cache Configuration 369 */ 370 #define CONFIG_SYS_CACHELINE_SIZE 16 371 372 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 373 CONFIG_SYS_INIT_RAM_SIZE - 8) 374 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 375 CONFIG_SYS_INIT_RAM_SIZE - 4) 376 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 377 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 378 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 379 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 380 CF_ACR_EN | CF_ACR_SM_ALL) 381 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 382 CF_CACR_ICINVA | CF_CACR_EUSP) 383 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 384 CF_CACR_DEC | CF_CACR_DDCM_P | \ 385 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 386 387 /*----------------------------------------------------------------------- 388 * Memory bank definitions 389 */ 390 /* 391 * CS0 - NOR Flash 1, 2, 4, or 8MB 392 * CS1 - CompactFlash and registers 393 * CS2 - CPLD 394 * CS3 - FPGA 395 * CS4 - Available 396 * CS5 - Available 397 */ 398 399 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) 400 /* Atmel Flash */ 401 #define CONFIG_SYS_CS0_BASE 0x04000000 402 #define CONFIG_SYS_CS0_MASK 0x00070001 403 #define CONFIG_SYS_CS0_CTRL 0x00001140 404 /* Intel Flash */ 405 #define CONFIG_SYS_CS1_BASE 0x00000000 406 #define CONFIG_SYS_CS1_MASK 0x01FF0001 407 #define CONFIG_SYS_CS1_CTRL 0x00000D60 408 409 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE 410 #else 411 /* Intel Flash */ 412 #define CONFIG_SYS_CS0_BASE 0x00000000 413 #define CONFIG_SYS_CS0_MASK 0x01FF0001 414 #define CONFIG_SYS_CS0_CTRL 0x00000D60 415 /* Atmel Flash */ 416 #define CONFIG_SYS_CS1_BASE 0x04000000 417 #define CONFIG_SYS_CS1_MASK 0x00070001 418 #define CONFIG_SYS_CS1_CTRL 0x00001140 419 420 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE 421 #endif 422 423 /* CPLD */ 424 #define CONFIG_SYS_CS2_BASE 0x08000000 425 #define CONFIG_SYS_CS2_MASK 0x00070001 426 #define CONFIG_SYS_CS2_CTRL 0x003f1140 427 428 /* FPGA */ 429 #define CONFIG_SYS_CS3_BASE 0x09000000 430 #define CONFIG_SYS_CS3_MASK 0x00070001 431 #define CONFIG_SYS_CS3_CTRL 0x00000020 432 433 #endif /* _M54455EVB_H */ 434