1 /* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54455EVB_H 15 #define _M54455EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54455EVB /* M54455EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #undef CONFIG_WATCHDOG 27 28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 29 30 /* 31 * BOOTP options 32 */ 33 #define CONFIG_BOOTP_BOOTFILESIZE 34 #define CONFIG_BOOTP_BOOTPATH 35 #define CONFIG_BOOTP_GATEWAY 36 #define CONFIG_BOOTP_HOSTNAME 37 38 /* Command line configuration */ 39 #define CONFIG_CMD_JFFS2 40 #undef CONFIG_CMD_PCI 41 #define CONFIG_CMD_REGINFO 42 43 /* Network configuration */ 44 #define CONFIG_MCFFEC 45 #ifdef CONFIG_MCFFEC 46 # define CONFIG_MII 1 47 # define CONFIG_MII_INIT 1 48 # define CONFIG_SYS_DISCOVER_PHY 49 # define CONFIG_SYS_RX_ETH_BUFFER 8 50 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 51 52 # define CONFIG_SYS_FEC0_PINMUX 0 53 # define CONFIG_SYS_FEC1_PINMUX 0 54 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 55 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 56 # define MCFFEC_TOUT_LOOP 50000 57 # define CONFIG_HAS_ETH1 58 59 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 60 # define CONFIG_ETHPRIME "FEC0" 61 # define CONFIG_IPADDR 192.162.1.2 62 # define CONFIG_NETMASK 255.255.255.0 63 # define CONFIG_SERVERIP 192.162.1.1 64 # define CONFIG_GATEWAYIP 192.162.1.1 65 66 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 67 # ifndef CONFIG_SYS_DISCOVER_PHY 68 # define FECDUPLEX FULL 69 # define FECSPEED _100BASET 70 # else 71 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 72 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 73 # endif 74 # endif /* CONFIG_SYS_DISCOVER_PHY */ 75 #endif 76 77 #define CONFIG_HOSTNAME M54455EVB 78 #ifdef CONFIG_SYS_STMICRO_BOOT 79 /* ST Micro serial flash */ 80 #define CONFIG_SYS_LOAD_ADDR2 0x40010013 81 #define CONFIG_EXTRA_ENV_SETTINGS \ 82 "netdev=eth0\0" \ 83 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 84 "loadaddr=0x40010000\0" \ 85 "sbfhdr=sbfhdr.bin\0" \ 86 "uboot=u-boot.bin\0" \ 87 "load=tftp ${loadaddr} ${sbfhdr};" \ 88 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 89 "upd=run load; run prog\0" \ 90 "prog=sf probe 0:1 1000000 3;" \ 91 "sf erase 0 30000;" \ 92 "sf write ${loadaddr} 0 0x30000;" \ 93 "save\0" \ 94 "" 95 #else 96 /* Atmel and Intel */ 97 #ifdef CONFIG_SYS_ATMEL_BOOT 98 # define CONFIG_SYS_UBOOT_END 0x0403FFFF 99 #elif defined(CONFIG_SYS_INTEL_BOOT) 100 # define CONFIG_SYS_UBOOT_END 0x3FFFF 101 #endif 102 #define CONFIG_EXTRA_ENV_SETTINGS \ 103 "netdev=eth0\0" \ 104 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 105 "loadaddr=0x40010000\0" \ 106 "uboot=u-boot.bin\0" \ 107 "load=tftp ${loadaddr} ${uboot}\0" \ 108 "upd=run load; run prog\0" \ 109 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 110 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 111 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 112 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 113 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 114 " ${filesize}; save\0" \ 115 "" 116 #endif 117 118 /* ATA configuration */ 119 #define CONFIG_IDE_RESET 1 120 #define CONFIG_IDE_PREINIT 1 121 #define CONFIG_ATAPI 122 #undef CONFIG_LBA48 123 124 #define CONFIG_SYS_IDE_MAXBUS 1 125 #define CONFIG_SYS_IDE_MAXDEVICE 2 126 127 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 128 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 129 130 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 131 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 132 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 133 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 134 135 /* Realtime clock */ 136 #define CONFIG_MCFRTC 137 #undef RTC_DEBUG 138 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 139 140 /* Timer */ 141 #define CONFIG_MCFTMR 142 #undef CONFIG_MCFPIT 143 144 /* I2c */ 145 #define CONFIG_SYS_I2C 146 #define CONFIG_SYS_I2C_FSL 147 #define CONFIG_SYS_FSL_I2C_SPEED 80000 148 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 149 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 150 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 151 152 /* DSPI and Serial Flash */ 153 #define CONFIG_CF_SPI 154 #define CONFIG_CF_DSPI 155 #define CONFIG_HARD_SPI 156 #define CONFIG_SYS_SBFHDR_SIZE 0x13 157 #ifdef CONFIG_CMD_SPI 158 159 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 160 DSPI_CTAR_PCSSCK_1CLK | \ 161 DSPI_CTAR_PASC(0) | \ 162 DSPI_CTAR_PDT(0) | \ 163 DSPI_CTAR_CSSCK(0) | \ 164 DSPI_CTAR_ASC(0) | \ 165 DSPI_CTAR_DT(1)) 166 #endif 167 168 /* PCI */ 169 #ifdef CONFIG_CMD_PCI 170 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 171 172 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 173 174 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 175 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 176 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 177 178 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 179 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 180 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 181 182 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 183 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 184 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 185 #endif 186 187 /* FPGA - Spartan 2 */ 188 /* experiment 189 #define CONFIG_FPGA 190 #define CONFIG_FPGA_COUNT 1 191 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 192 #define CONFIG_SYS_FPGA_CHECK_CTRLC 193 */ 194 195 /* Input, PCI, Flexbus, and VCO */ 196 #define CONFIG_EXTRA_CLOCK 197 198 #define CONFIG_PRAM 2048 /* 2048 KB */ 199 200 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 201 202 #if defined(CONFIG_CMD_KGDB) 203 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 204 #else 205 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 206 #endif 207 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 208 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 209 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 210 211 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 212 213 #define CONFIG_SYS_MBAR 0xFC000000 214 215 /* 216 * Low Level Configuration Settings 217 * (address mappings, register initial values, etc.) 218 * You should know what you are doing if you make changes here. 219 */ 220 221 /*----------------------------------------------------------------------- 222 * Definitions for initial stack pointer and data area (in DPRAM) 223 */ 224 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 225 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 226 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 227 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 228 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 229 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 230 231 /*----------------------------------------------------------------------- 232 * Start addresses for the final memory configuration 233 * (Set up by the startup code) 234 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 235 */ 236 #define CONFIG_SYS_SDRAM_BASE 0x40000000 237 #define CONFIG_SYS_SDRAM_BASE1 0x48000000 238 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ 239 #define CONFIG_SYS_SDRAM_CFG1 0x65311610 240 #define CONFIG_SYS_SDRAM_CFG2 0x59670000 241 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 242 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 243 #define CONFIG_SYS_SDRAM_MODE 0x00010033 244 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA 245 246 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 247 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 248 249 #ifdef CONFIG_CF_SBF 250 # define CONFIG_SERIAL_BOOT 251 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 252 #else 253 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 254 #endif 255 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 256 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 257 258 /* Reserve 256 kB for malloc() */ 259 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 260 261 /* 262 * For booting Linux, the board info and command line data 263 * have to be in the first 8 MB of memory, since this is 264 * the maximum mapped by the Linux kernel during initialization ?? 265 */ 266 /* Initial Memory map for Linux */ 267 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 268 269 /* 270 * Configuration for environment 271 * Environment is not embedded in u-boot. First time runing may have env 272 * crc error warning if there is no correct environment on the flash. 273 */ 274 #ifdef CONFIG_CF_SBF 275 # define CONFIG_ENV_IS_IN_SPI_FLASH 276 # define CONFIG_ENV_SPI_CS 1 277 #else 278 # define CONFIG_ENV_IS_IN_FLASH 1 279 #endif 280 #undef CONFIG_ENV_OVERWRITE 281 282 /*----------------------------------------------------------------------- 283 * FLASH organization 284 */ 285 #ifdef CONFIG_SYS_STMICRO_BOOT 286 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 287 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE 288 # define CONFIG_ENV_OFFSET 0x30000 289 # define CONFIG_ENV_SIZE 0x2000 290 # define CONFIG_ENV_SECT_SIZE 0x10000 291 #endif 292 #ifdef CONFIG_SYS_ATMEL_BOOT 293 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 294 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 295 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 296 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 297 # define CONFIG_ENV_SIZE 0x2000 298 # define CONFIG_ENV_SECT_SIZE 0x10000 299 #endif 300 #ifdef CONFIG_SYS_INTEL_BOOT 301 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 302 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 303 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 304 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 305 # define CONFIG_ENV_SIZE 0x2000 306 # define CONFIG_ENV_SECT_SIZE 0x20000 307 #endif 308 309 #define CONFIG_SYS_FLASH_CFI 310 #ifdef CONFIG_SYS_FLASH_CFI 311 312 # define CONFIG_FLASH_CFI_DRIVER 1 313 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 314 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 315 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 316 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 317 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 318 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 319 # define CONFIG_SYS_FLASH_CHECKSUM 320 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 321 # define CONFIG_FLASH_CFI_LEGACY 322 323 #ifdef CONFIG_FLASH_CFI_LEGACY 324 # define CONFIG_SYS_ATMEL_REGION 4 325 # define CONFIG_SYS_ATMEL_TOTALSECT 11 326 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 327 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 328 #endif 329 #endif 330 331 /* 332 * This is setting for JFFS2 support in u-boot. 333 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 334 */ 335 #ifdef CONFIG_CMD_JFFS2 336 #ifdef CF_STMICRO_BOOT 337 # define CONFIG_JFFS2_DEV "nor1" 338 # define CONFIG_JFFS2_PART_SIZE 0x01000000 339 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) 340 #endif 341 #ifdef CONFIG_SYS_ATMEL_BOOT 342 # define CONFIG_JFFS2_DEV "nor1" 343 # define CONFIG_JFFS2_PART_SIZE 0x01000000 344 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) 345 #endif 346 #ifdef CONFIG_SYS_INTEL_BOOT 347 # define CONFIG_JFFS2_DEV "nor0" 348 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 349 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 350 #endif 351 #endif 352 353 /*----------------------------------------------------------------------- 354 * Cache Configuration 355 */ 356 #define CONFIG_SYS_CACHELINE_SIZE 16 357 358 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 359 CONFIG_SYS_INIT_RAM_SIZE - 8) 360 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 361 CONFIG_SYS_INIT_RAM_SIZE - 4) 362 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 363 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 364 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 365 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 366 CF_ACR_EN | CF_ACR_SM_ALL) 367 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 368 CF_CACR_ICINVA | CF_CACR_EUSP) 369 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 370 CF_CACR_DEC | CF_CACR_DDCM_P | \ 371 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 372 373 /*----------------------------------------------------------------------- 374 * Memory bank definitions 375 */ 376 /* 377 * CS0 - NOR Flash 1, 2, 4, or 8MB 378 * CS1 - CompactFlash and registers 379 * CS2 - CPLD 380 * CS3 - FPGA 381 * CS4 - Available 382 * CS5 - Available 383 */ 384 385 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) 386 /* Atmel Flash */ 387 #define CONFIG_SYS_CS0_BASE 0x04000000 388 #define CONFIG_SYS_CS0_MASK 0x00070001 389 #define CONFIG_SYS_CS0_CTRL 0x00001140 390 /* Intel Flash */ 391 #define CONFIG_SYS_CS1_BASE 0x00000000 392 #define CONFIG_SYS_CS1_MASK 0x01FF0001 393 #define CONFIG_SYS_CS1_CTRL 0x00000D60 394 395 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE 396 #else 397 /* Intel Flash */ 398 #define CONFIG_SYS_CS0_BASE 0x00000000 399 #define CONFIG_SYS_CS0_MASK 0x01FF0001 400 #define CONFIG_SYS_CS0_CTRL 0x00000D60 401 /* Atmel Flash */ 402 #define CONFIG_SYS_CS1_BASE 0x04000000 403 #define CONFIG_SYS_CS1_MASK 0x00070001 404 #define CONFIG_SYS_CS1_CTRL 0x00001140 405 406 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE 407 #endif 408 409 /* CPLD */ 410 #define CONFIG_SYS_CS2_BASE 0x08000000 411 #define CONFIG_SYS_CS2_MASK 0x00070001 412 #define CONFIG_SYS_CS2_CTRL 0x003f1140 413 414 /* FPGA */ 415 #define CONFIG_SYS_CS3_BASE 0x09000000 416 #define CONFIG_SYS_CS3_MASK 0x00070001 417 #define CONFIG_SYS_CS3_CTRL 0x00000020 418 419 #endif /* _M54455EVB_H */ 420