1 /* 2 * Configuation settings for the Freescale MCF54451 EVB board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54451EVB_H 15 #define _M54451EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54451EVB /* M54451EVB board */ 22 23 #define CONFIG_DISPLAY_BOARDINFO 24 25 #define CONFIG_MCFUART 26 #define CONFIG_SYS_UART_PORT (0) 27 #define CONFIG_BAUDRATE 115200 28 29 #undef CONFIG_WATCHDOG 30 31 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 32 33 /* 34 * BOOTP options 35 */ 36 #define CONFIG_BOOTP_BOOTFILESIZE 37 #define CONFIG_BOOTP_BOOTPATH 38 #define CONFIG_BOOTP_GATEWAY 39 #define CONFIG_BOOTP_HOSTNAME 40 41 /* Command line configuration */ 42 #define CONFIG_CMD_CACHE 43 #define CONFIG_CMD_DATE 44 #undef CONFIG_CMD_JFFS2 45 #define CONFIG_CMD_MII 46 #define CONFIG_CMD_REGINFO 47 48 /* Network configuration */ 49 #define CONFIG_MCFFEC 50 #ifdef CONFIG_MCFFEC 51 # define CONFIG_MII 1 52 # define CONFIG_MII_INIT 1 53 # define CONFIG_SYS_DISCOVER_PHY 54 # define CONFIG_SYS_RX_ETH_BUFFER 8 55 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 56 57 # define CONFIG_SYS_FEC0_PINMUX 0 58 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 59 # define MCFFEC_TOUT_LOOP 50000 60 61 # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 62 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" 63 # define CONFIG_ETHPRIME "FEC0" 64 # define CONFIG_IPADDR 192.162.1.2 65 # define CONFIG_NETMASK 255.255.255.0 66 # define CONFIG_SERVERIP 192.162.1.1 67 # define CONFIG_GATEWAYIP 192.162.1.1 68 69 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 70 # ifndef CONFIG_SYS_DISCOVER_PHY 71 # define FECDUPLEX FULL 72 # define FECSPEED _100BASET 73 # else 74 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 75 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 76 # endif 77 # endif /* CONFIG_SYS_DISCOVER_PHY */ 78 #endif 79 80 #define CONFIG_HOSTNAME M54451EVB 81 #ifdef CONFIG_SYS_STMICRO_BOOT 82 /* ST Micro serial flash */ 83 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 84 #define CONFIG_EXTRA_ENV_SETTINGS \ 85 "netdev=eth0\0" \ 86 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 87 "loadaddr=0x40010000\0" \ 88 "sbfhdr=sbfhdr.bin\0" \ 89 "uboot=u-boot.bin\0" \ 90 "load=tftp ${loadaddr} ${sbfhdr};" \ 91 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 92 "upd=run load; run prog\0" \ 93 "prog=sf probe 0:1 1000000 3;" \ 94 "sf erase 0 30000;" \ 95 "sf write ${loadaddr} 0 30000;" \ 96 "save\0" \ 97 "" 98 #else 99 #define CONFIG_SYS_UBOOT_END 0x3FFFF 100 #define CONFIG_EXTRA_ENV_SETTINGS \ 101 "netdev=eth0\0" \ 102 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 103 "loadaddr=40010000\0" \ 104 "u-boot=u-boot.bin\0" \ 105 "load=tftp ${loadaddr) ${u-boot}\0" \ 106 "upd=run load; run prog\0" \ 107 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ 108 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ 109 "cp.b ${loadaddr} 0 ${filesize};" \ 110 "save\0" \ 111 "" 112 #endif 113 114 /* Realtime clock */ 115 #define CONFIG_MCFRTC 116 #undef RTC_DEBUG 117 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 118 119 /* Timer */ 120 #define CONFIG_MCFTMR 121 #undef CONFIG_MCFPIT 122 123 /* I2c */ 124 #define CONFIG_SYS_I2C 125 #define CONFIG_SYS_I2C_FSL 126 #define CONFIG_SYS_FSL_I2C_SPEED 80000 127 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 128 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 129 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 130 131 /* DSPI and Serial Flash */ 132 #define CONFIG_CF_SPI 133 #define CONFIG_CF_DSPI 134 #define CONFIG_SERIAL_FLASH 135 #define CONFIG_HARD_SPI 136 #define CONFIG_SYS_SBFHDR_SIZE 0x7 137 #ifdef CONFIG_CMD_SPI 138 139 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 140 DSPI_CTAR_PCSSCK_1CLK | \ 141 DSPI_CTAR_PASC(0) | \ 142 DSPI_CTAR_PDT(0) | \ 143 DSPI_CTAR_CSSCK(0) | \ 144 DSPI_CTAR_ASC(0) | \ 145 DSPI_CTAR_DT(1)) 146 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 147 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 148 #endif 149 150 /* Input, PCI, Flexbus, and VCO */ 151 #define CONFIG_EXTRA_CLOCK 152 153 #define CONFIG_PRAM 2048 /* 2048 KB */ 154 155 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 156 157 #if defined(CONFIG_CMD_KGDB) 158 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 159 #else 160 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 161 #endif 162 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 163 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 164 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 165 166 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 167 168 #define CONFIG_SYS_MBAR 0xFC000000 169 170 /* 171 * Low Level Configuration Settings 172 * (address mappings, register initial values, etc.) 173 * You should know what you are doing if you make changes here. 174 */ 175 176 /*----------------------------------------------------------------------- 177 * Definitions for initial stack pointer and data area (in DPRAM) 178 */ 179 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 180 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 181 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 182 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 183 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 184 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 185 186 /*----------------------------------------------------------------------- 187 * Start addresses for the final memory configuration 188 * (Set up by the startup code) 189 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 190 */ 191 #define CONFIG_SYS_SDRAM_BASE 0x40000000 192 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 193 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30 194 #define CONFIG_SYS_SDRAM_CFG2 0x57670000 195 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 196 #define CONFIG_SYS_SDRAM_EMOD 0x80810000 197 #define CONFIG_SYS_SDRAM_MODE 0x008D0000 198 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 199 200 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 201 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 202 203 #ifdef CONFIG_CF_SBF 204 # define CONFIG_SERIAL_BOOT 205 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 206 #else 207 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 208 #endif 209 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 210 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 211 212 /* Reserve 256 kB for malloc() */ 213 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 214 /* 215 * For booting Linux, the board info and command line data 216 * have to be in the first 8 MB of memory, since this is 217 * the maximum mapped by the Linux kernel during initialization ?? 218 */ 219 /* Initial Memory map for Linux */ 220 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 221 222 /* Configuration for environment 223 * Environment is not embedded in u-boot. First time runing may have env 224 * crc error warning if there is no correct environment on the flash. 225 */ 226 #if defined(CONFIG_SYS_STMICRO_BOOT) 227 # define CONFIG_ENV_IS_IN_SPI_FLASH 1 228 # define CONFIG_ENV_SPI_CS 1 229 # define CONFIG_ENV_OFFSET 0x20000 230 # define CONFIG_ENV_SIZE 0x2000 231 # define CONFIG_ENV_SECT_SIZE 0x10000 232 #else 233 # define CONFIG_ENV_IS_IN_FLASH 1 234 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 235 # define CONFIG_ENV_SIZE 0x2000 236 # define CONFIG_ENV_SECT_SIZE 0x20000 237 #endif 238 #undef CONFIG_ENV_OVERWRITE 239 240 /* FLASH organization */ 241 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 242 243 #define CONFIG_SYS_FLASH_CFI 244 #ifdef CONFIG_SYS_FLASH_CFI 245 246 # define CONFIG_FLASH_CFI_DRIVER 1 247 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 248 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 249 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 250 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 251 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 252 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 253 # define CONFIG_SYS_FLASH_CHECKSUM 254 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 255 256 #endif 257 258 /* 259 * This is setting for JFFS2 support in u-boot. 260 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 261 */ 262 #ifdef CONFIG_CMD_JFFS2 263 # define CONFIG_JFFS2_DEV "nor0" 264 # define CONFIG_JFFS2_PART_SIZE 0x01000000 265 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 266 #endif 267 268 /* Cache Configuration */ 269 #define CONFIG_SYS_CACHELINE_SIZE 16 270 271 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 272 CONFIG_SYS_INIT_RAM_SIZE - 8) 273 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 274 CONFIG_SYS_INIT_RAM_SIZE - 4) 275 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 276 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 277 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 278 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 279 CF_ACR_EN | CF_ACR_SM_ALL) 280 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 281 CF_CACR_ICINVA | CF_CACR_EUSP) 282 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 283 CF_CACR_DEC | CF_CACR_DDCM_P | \ 284 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 285 286 /*----------------------------------------------------------------------- 287 * Memory bank definitions 288 */ 289 /* 290 * CS0 - NOR Flash 16MB 291 * CS1 - Available 292 * CS2 - Available 293 * CS3 - Available 294 * CS4 - Available 295 * CS5 - Available 296 */ 297 298 /* Flash */ 299 #define CONFIG_SYS_CS0_BASE 0x00000000 300 #define CONFIG_SYS_CS0_MASK 0x00FF0001 301 #define CONFIG_SYS_CS0_CTRL 0x00004D80 302 303 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 304 305 #endif /* _M54451EVB_H */ 306