1 /* 2 * Configuation settings for the Freescale MCF54418 TWR board. 3 * 4 * Copyright 2010-2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54418TWR_H 15 #define _M54418TWR_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_MCF5441x /* define processor family */ 22 #define CONFIG_M54418 /* define processor type */ 23 #define CONFIG_M54418TWR /* M54418TWR board */ 24 25 #define CONFIG_MCFUART 26 #define CONFIG_SYS_UART_PORT (0) 27 #define CONFIG_BAUDRATE 115200 28 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 29 30 #undef CONFIG_WATCHDOG 31 32 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 33 34 /* 35 * BOOTP options 36 */ 37 #define CONFIG_BOOTP_BOOTFILESIZE 38 #define CONFIG_BOOTP_BOOTPATH 39 #define CONFIG_BOOTP_GATEWAY 40 #define CONFIG_BOOTP_HOSTNAME 41 42 /* Command line configuration */ 43 #include <config_cmd_default.h> 44 45 #define CONFIG_CMD_BOOTD 46 #define CONFIG_CMD_CACHE 47 #undef CONFIG_CMD_DATE 48 #define CONFIG_CMD_DHCP 49 #define CONFIG_CMD_ELF 50 #undef CONFIG_CMD_FLASH 51 #undef CONFIG_CMD_I2C 52 #undef CONFIG_CMD_JFFS2 53 #undef CONFIG_CMD_UBI 54 #define CONFIG_CMD_MEMORY 55 #define CONFIG_CMD_MISC 56 #define CONFIG_CMD_MII 57 #undef CONFIG_CMD_NAND 58 #undef CONFIG_CMD_NAND_YAFFS 59 #define CONFIG_CMD_NET 60 #define CONFIG_CMD_NFS 61 #define CONFIG_CMD_PING 62 #define CONFIG_CMD_REGINFO 63 #define CONFIG_CMD_SPI 64 #define CONFIG_CMD_SF 65 #undef CONFIG_CMD_IMLS 66 67 #undef CONFIG_CMD_LOADB 68 #undef CONFIG_CMD_LOADS 69 70 /* 71 * NAND FLASH 72 */ 73 #ifdef CONFIG_CMD_NAND 74 #define CONFIG_JFFS2_NAND 75 #define CONFIG_NAND_FSL_NFC 76 #define CONFIG_SYS_NAND_BASE 0xFC0FC000 77 #define CONFIG_SYS_MAX_NAND_DEVICE 1 78 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 79 #define CONFIG_SYS_NAND_SELECT_DEVICE 80 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ 81 #endif 82 83 /* Network configuration */ 84 #define CONFIG_MCFFEC 85 #ifdef CONFIG_MCFFEC 86 #define CONFIG_NET_MULTI 1 87 #define CONFIG_MII 1 88 #define CONFIG_MII_INIT 1 89 #define CONFIG_SYS_DISCOVER_PHY 90 #define CONFIG_SYS_RX_ETH_BUFFER 2 91 #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN 92 #define CONFIG_SYS_TX_ETH_BUFFER 2 93 #define CONFIG_HAS_ETH1 94 95 #define CONFIG_SYS_FEC0_PINMUX 0 96 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 97 #define CONFIG_SYS_FEC1_PINMUX 0 98 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE 99 #define MCFFEC_TOUT_LOOP 50000 100 #define CONFIG_SYS_FEC0_PHYADDR 0 101 #define CONFIG_SYS_FEC1_PHYADDR 1 102 103 #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ 104 105 #ifdef CONFIG_SYS_NAND_BOOT 106 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ 107 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \ 108 "-(jffs2) console=ttyS0,115200" 109 #else 110 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \ 111 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \ 112 __stringify(CONFIG_IPADDR) " ip=" \ 113 __stringify(CONFIG_IPADDR) ":" \ 114 __stringify(CONFIG_SERVERIP)":" \ 115 __stringify(CONFIG_GATEWAYIP)": " \ 116 __stringify(CONFIG_NETMASK) \ 117 "::eth0:off:rw console=ttyS0,115200" 118 #endif 119 120 #define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 121 #define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 122 #define CONFIG_ETHPRIME "FEC0" 123 #define CONFIG_IPADDR 192.168.1.2 124 #define CONFIG_NETMASK 255.255.255.0 125 #define CONFIG_SERVERIP 192.168.1.1 126 #define CONFIG_GATEWAYIP 192.168.1.1 127 128 #define CONFIG_OVERWRITE_ETHADDR_ONCE 129 #define CONFIG_SYS_FEC_BUF_USE_SRAM 130 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 131 #ifndef CONFIG_SYS_DISCOVER_PHY 132 #define FECDUPLEX FULL 133 #define FECSPEED _100BASET 134 #define LINKSTATUS 1 135 #else 136 #define LINKSTATUS 0 137 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 138 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 139 #endif 140 #endif /* CONFIG_SYS_DISCOVER_PHY */ 141 #endif 142 143 #define CONFIG_HOSTNAME M54418TWR 144 145 #if defined(CONFIG_CF_SBF) 146 /* ST Micro serial flash */ 147 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 148 #define CONFIG_EXTRA_ENV_SETTINGS \ 149 "netdev=eth0\0" \ 150 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 151 "loadaddr=0x40010000\0" \ 152 "sbfhdr=sbfhdr.bin\0" \ 153 "uboot=u-boot.bin\0" \ 154 "load=tftp ${loadaddr} ${sbfhdr};" \ 155 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 156 "upd=run load; run prog\0" \ 157 "prog=sf probe 0:1 1000000 3;" \ 158 "sf erase 0 40000;" \ 159 "sf write ${loadaddr} 0 40000;" \ 160 "save\0" \ 161 "" 162 #elif defined(CONFIG_SYS_NAND_BOOT) 163 #define CONFIG_EXTRA_ENV_SETTINGS \ 164 "netdev=eth0\0" \ 165 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 166 "loadaddr=0x40010000\0" \ 167 "u-boot=u-boot.bin\0" \ 168 "load=tftp ${loadaddr} ${u-boot};\0" \ 169 "upd=run load; run prog\0" \ 170 "prog=nand device 0;" \ 171 "nand erase 0 40000;" \ 172 "nb_update ${loadaddr} ${filesize};" \ 173 "save\0" \ 174 "" 175 #else 176 #define CONFIG_SYS_UBOOT_END 0x3FFFF 177 #define CONFIG_EXTRA_ENV_SETTINGS \ 178 "netdev=eth0\0" \ 179 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 180 "loadaddr=40010000\0" \ 181 "u-boot=u-boot.bin\0" \ 182 "load=tftp ${loadaddr) ${u-boot}\0" \ 183 "upd=run load; run prog\0" \ 184 "prog=prot off mram" " ;" \ 185 "cp.b ${loadaddr} 0 ${filesize};" \ 186 "save\0" \ 187 "" 188 #endif 189 190 /* Realtime clock */ 191 #undef CONFIG_MCFRTC 192 #define CONFIG_RTC_MCFRRTC 193 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 194 195 /* Timer */ 196 #define CONFIG_MCFTMR 197 #undef CONFIG_MCFPIT 198 199 /* I2c */ 200 #undef CONFIG_SYS_FSL_I2C 201 #undef CONFIG_HARD_I2C /* I2C with hardware support */ 202 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 203 /* I2C speed and slave address */ 204 #define CONFIG_SYS_I2C_SPEED 80000 205 #define CONFIG_SYS_I2C_SLAVE 0x7F 206 #define CONFIG_SYS_I2C_OFFSET 0x58000 207 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 208 209 /* DSPI and Serial Flash */ 210 #define CONFIG_CF_SPI 211 #define CONFIG_CF_DSPI 212 #define CONFIG_SERIAL_FLASH 213 #define CONFIG_HARD_SPI 214 #define CONFIG_SYS_SBFHDR_SIZE 0x7 215 #ifdef CONFIG_CMD_SPI 216 # define CONFIG_SPI_FLASH 217 # define CONFIG_SPI_FLASH_ATMEL 218 219 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 220 DSPI_CTAR_PCSSCK_1CLK | \ 221 DSPI_CTAR_PASC(0) | \ 222 DSPI_CTAR_PDT(0) | \ 223 DSPI_CTAR_CSSCK(0) | \ 224 DSPI_CTAR_ASC(0) | \ 225 DSPI_CTAR_DT(1)) 226 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 227 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 228 #endif 229 230 /* Input, PCI, Flexbus, and VCO */ 231 #define CONFIG_EXTRA_CLOCK 232 233 #define CONFIG_PRAM 2048 /* 2048 KB */ 234 235 /* HUSH */ 236 #define CONFIG_SYS_HUSH_PARSER 1 237 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 238 239 #define CONFIG_SYS_PROMPT "-> " 240 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 241 242 #if defined(CONFIG_CMD_KGDB) 243 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 244 #else 245 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 246 #endif 247 /* Print Buffer Size */ 248 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 249 sizeof(CONFIG_SYS_PROMPT) + 16) 250 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 251 /* Boot Argument Buffer Size */ 252 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 253 254 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 255 256 #define CONFIG_SYS_MBAR 0xFC000000 257 258 /* 259 * Low Level Configuration Settings 260 * (address mappings, register initial values, etc.) 261 * You should know what you are doing if you make changes here. 262 */ 263 264 /*----------------------------------------------------------------------- 265 * Definitions for initial stack pointer and data area (in DPRAM) 266 */ 267 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 268 /* End of used area in internal SRAM */ 269 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 270 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 271 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 272 GENERATED_GBL_DATA_SIZE) - 32) 273 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 274 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 275 276 /*----------------------------------------------------------------------- 277 * Start addresses for the final memory configuration 278 * (Set up by the startup code) 279 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 280 */ 281 #define CONFIG_SYS_SDRAM_BASE 0x40000000 282 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 283 284 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 285 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 286 #define CONFIG_SYS_DRAM_TEST 287 288 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) 289 #define CONFIG_SERIAL_BOOT 290 #endif 291 292 #if defined(CONFIG_SERIAL_BOOT) 293 #define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400) 294 #else 295 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 296 #endif 297 298 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 299 /* Reserve 256 kB for Monitor */ 300 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 301 /* Reserve 256 kB for malloc() */ 302 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 303 304 /* 305 * For booting Linux, the board info and command line data 306 * have to be in the first 8 MB of memory, since this is 307 * the maximum mapped by the Linux kernel during initialization ?? 308 */ 309 /* Initial Memory map for Linux */ 310 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 311 (CONFIG_SYS_SDRAM_SIZE << 20)) 312 313 /* Configuration for environment 314 * Environment is embedded in u-boot in the second sector of the flash 315 */ 316 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ 317 #define CONFIG_SYS_NO_FLASH 318 #define CONFIG_ENV_IS_IN_MRAM 1 319 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ 320 #define CONFIG_ENV_SIZE 0x1000 321 #endif 322 323 #if defined(CONFIG_CF_SBF) 324 #define CONFIG_SYS_NO_FLASH 325 #define CONFIG_ENV_IS_IN_SPI_FLASH 1 326 #define CONFIG_ENV_SPI_CS 1 327 #define CONFIG_ENV_OFFSET 0x40000 328 #define CONFIG_ENV_SIZE 0x2000 329 #define CONFIG_ENV_SECT_SIZE 0x10000 330 #endif 331 #if defined(CONFIG_SYS_NAND_BOOT) 332 #define CONFIG_SYS_NO_FLASH 333 #define CONFIG_ENV_IS_NOWHERE 334 #define CONFIG_ENV_OFFSET 0x80000 335 #define CONFIG_ENV_SIZE 0x20000 336 #define CONFIG_ENV_SECT_SIZE 0x20000 337 #endif 338 #undef CONFIG_ENV_OVERWRITE 339 340 /* FLASH organization */ 341 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 342 343 #undef CONFIG_SYS_FLASH_CFI 344 #ifdef CONFIG_SYS_FLASH_CFI 345 346 #define CONFIG_FLASH_CFI_DRIVER 1 347 /* Max size that the board might have */ 348 #define CONFIG_SYS_FLASH_SIZE 0x1000000 349 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 350 /* max number of memory banks */ 351 #define CONFIG_SYS_MAX_FLASH_BANKS 1 352 /* max number of sectors on one chip */ 353 #define CONFIG_SYS_MAX_FLASH_SECT 270 354 /* "Real" (hardware) sectors protection */ 355 #define CONFIG_SYS_FLASH_PROTECTION 356 #define CONFIG_SYS_FLASH_CHECKSUM 357 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 358 #else 359 /* max number of sectors on one chip */ 360 #define CONFIG_SYS_MAX_FLASH_SECT 270 361 /* max number of sectors on one chip */ 362 #define CONFIG_SYS_MAX_FLASH_BANKS 0 363 #endif 364 365 /* 366 * This is setting for JFFS2 support in u-boot. 367 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 368 */ 369 #ifdef CONFIG_CMD_JFFS2 370 #define CONFIG_JFFS2_DEV "nand0" 371 #define CONFIG_JFFS2_PART_OFFSET (0x800000) 372 #define CONFIG_CMD_MTDPARTS 373 #define CONFIG_MTD_DEVICE 374 #define MTDIDS_DEFAULT "nand0=m54418twr.nand" 375 376 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ 377 "7m(kernel)," \ 378 "-(rootfs)" 379 380 #endif 381 382 #ifdef CONFIG_CMD_UBI 383 #define CONFIG_CMD_MTDPARTS 384 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */ 385 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ 386 #define CONFIG_RBTREE 387 #define MTDIDS_DEFAULT "nand0=NAND" 388 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ 389 "-(ubi)" 390 #endif 391 /* Cache Configuration */ 392 #define CONFIG_SYS_CACHELINE_SIZE 16 393 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 394 CONFIG_SYS_INIT_RAM_SIZE - 8) 395 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 396 CONFIG_SYS_INIT_RAM_SIZE - 4) 397 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 398 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 399 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 400 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 401 CF_ACR_EN | CF_ACR_SM_ALL) 402 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 403 CF_CACR_ICINVA | CF_CACR_EUSP) 404 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 405 CF_CACR_DEC | CF_CACR_DDCM_P | \ 406 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 407 408 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 409 CONFIG_SYS_INIT_RAM_SIZE - 12) 410 411 /*----------------------------------------------------------------------- 412 * Memory bank definitions 413 */ 414 /* 415 * CS0 - NOR Flash 16MB 416 * CS1 - Available 417 * CS2 - Available 418 * CS3 - Available 419 * CS4 - Available 420 * CS5 - Available 421 */ 422 423 /* Flash */ 424 #define CONFIG_SYS_CS0_BASE 0x00000000 425 #define CONFIG_SYS_CS0_MASK 0x000F0101 426 #define CONFIG_SYS_CS0_CTRL 0x00001D60 427 428 #endif /* _M54418TWR_H */ 429