1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M5329EVB_H 31 #define _M5329EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF532x /* define processor family */ 38 #define CONFIG_M5329 /* define processor type */ 39 40 #undef DEBUG 41 42 #define CONFIG_MCFSERIAL 43 #define CONFIG_BAUDRATE 115200 44 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 45 46 #undef CONFIG_WATCHDOG 47 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 48 49 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ 50 CFG_CMD_CACHE | \ 51 CFG_CMD_DATE | \ 52 CFG_CMD_ELF | \ 53 CFG_CMD_FLASH | \ 54 (CFG_CMD_LOADB | CFG_CMD_LOADS) | \ 55 CFG_CMD_MEMORY | \ 56 CFG_CMD_MISC | \ 57 CFG_CMD_MII | \ 58 CFG_CMD_NET | \ 59 CFG_CMD_PING | \ 60 CFG_CMD_REGINFO \ 61 ) 62 63 #define CFG_UNIFY_CACHE 64 65 #define CONFIG_MCFFEC 66 #ifdef CONFIG_MCFFEC 67 # define CONFIG_NET_MULTI 1 68 # define CONFIG_MII 1 69 # define CFG_DISCOVER_PHY 70 # define CFG_RX_ETH_BUFFER 8 71 # define CFG_FAULT_ECHO_LINK_DOWN 72 73 # define CFG_FEC0_PINMUX 0 74 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE 75 # define MCFFEC_TOUT_LOOP 50000 76 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ 77 # ifndef CFG_DISCOVER_PHY 78 # define FECDUPLEX FULL 79 # define FECSPEED _100BASET 80 # else 81 # ifndef CFG_FAULT_ECHO_LINK_DOWN 82 # define CFG_FAULT_ECHO_LINK_DOWN 83 # endif 84 # endif /* CFG_DISCOVER_PHY */ 85 #endif 86 87 #define CONFIG_MCFUART 88 #define CFG_UART_PORT (0) 89 90 #define CONFIG_MCFRTC 91 #undef RTC_DEBUG 92 93 /* Timer */ 94 #define CONFIG_MCFTMR 95 #undef CONFIG_MCFPIT 96 97 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 98 #include <cmd_confdefs.h> 99 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 100 #ifdef CONFIG_MCFFEC 101 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 102 # define CONFIG_IPADDR 192.162.1.2 103 # define CONFIG_NETMASK 255.255.255.0 104 # define CONFIG_SERVERIP 192.162.1.1 105 # define CONFIG_GATEWAYIP 192.162.1.1 106 # define CONFIG_OVERWRITE_ETHADDR_ONCE 107 #endif /* FEC_ENET */ 108 109 #define CONFIG_HOSTNAME M5329EVB 110 #define CONFIG_EXTRA_ENV_SETTINGS \ 111 "netdev=eth0\0" \ 112 "loadaddr=40010000\0" \ 113 "u-boot=u-boot.bin\0" \ 114 "load=tftp ${loadaddr) ${u-boot}\0" \ 115 "upd=run load; run prog\0" \ 116 "prog=prot off 0 2ffff;" \ 117 "era 0 2ffff;" \ 118 "cp.b ${loadaddr} 0 ${filesize};" \ 119 "save\0" \ 120 "" 121 122 #define CONFIG_PRAM 512 /* 512 KB */ 123 #define CFG_PROMPT "-> " 124 #define CFG_LONGHELP /* undef to save memory */ 125 126 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 127 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 128 #else 129 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 130 #endif 131 132 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 133 #define CFG_MAXARGS 16 /* max number of command args */ 134 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 135 #define CFG_LOAD_ADDR 0x40010000 136 137 #define CFG_HZ 1000 138 #define CFG_CLK 80000000 139 #define CFG_CPU_CLK CFG_CLK * 3 140 141 #define CFG_MBAR 0xFC000000 142 143 /* 144 * Low Level Configuration Settings 145 * (address mappings, register initial values, etc.) 146 * You should know what you are doing if you make changes here. 147 */ 148 /*----------------------------------------------------------------------- 149 * Definitions for initial stack pointer and data area (in DPRAM) 150 */ 151 #define CFG_INIT_RAM_ADDR 0x80000000 152 #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ 153 #define CFG_INIT_RAM_CTRL 0x221 154 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 155 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 156 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 157 158 /*----------------------------------------------------------------------- 159 * Start addresses for the final memory configuration 160 * (Set up by the startup code) 161 * Please note that CFG_SDRAM_BASE _must_ start at 0 162 */ 163 #define CFG_SDRAM_BASE 0x40000000 164 #define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ 165 #define CFG_SDRAM_CFG1 0x53722730 166 #define CFG_SDRAM_CFG2 0x56670000 167 #define CFG_SDRAM_CTRL 0xE1092000 168 #define CFG_SDRAM_EMOD 0x40010000 169 #define CFG_SDRAM_MODE 0x018D0000 170 171 #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 172 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) 173 174 #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) 175 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 176 177 #define CFG_BOOTPARAMS_LEN 64*1024 178 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 179 180 /* 181 * For booting Linux, the board info and command line data 182 * have to be in the first 8 MB of memory, since this is 183 * the maximum mapped by the Linux kernel during initialization ?? 184 */ 185 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 186 187 /*----------------------------------------------------------------------- 188 * FLASH organization 189 */ 190 #define CFG_FLASH_CFI 191 #ifdef CFG_FLASH_CFI 192 # define CFG_FLASH_CFI_DRIVER 1 193 # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ 194 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT 195 # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ 196 # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 197 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 198 #endif 199 200 #define CFG_FLASH_BASE 0 201 #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) 202 203 /* Configuration for environment 204 * Environment is embedded in u-boot in the second sector of the flash 205 */ 206 #define CFG_ENV_OFFSET 0x4000 207 #define CFG_ENV_SECT_SIZE 0x2000 208 #define CFG_ENV_IS_IN_FLASH 1 209 #define CFG_ENV_IS_EMBEDDED 1 210 211 /*----------------------------------------------------------------------- 212 * Cache Configuration 213 */ 214 #define CFG_CACHELINE_SIZE 16 215 216 /*----------------------------------------------------------------------- 217 * Chipselect bank definitions 218 */ 219 /* 220 * CS0 - NOR Flash 1, 2, 4, or 8MB 221 * CS1 - CompactFlash and registers 222 * CS2 - NAND Flash 16, 32, or 64MB 223 * CS3 - Available 224 * CS4 - Available 225 * CS5 - Available 226 */ 227 #define CFG_CS0_BASE 0 228 #define CFG_CS0_MASK 0x007f0001 229 #define CFG_CS0_CTRL 0x00001fa0 230 231 #define CFG_CS1_BASE 0x1000 232 #define CFG_CS1_MASK 0x001f0001 233 #define CFG_CS1_CTRL 0x002A3780 234 235 #ifdef NANDFLASH_SIZE 236 #define CFG_CS2_BASE 0x00800000 237 #define CFG_CS2_MASK 0x00ff0001 238 #define CFG_CS2_CTRL 0x00001f60 239 #endif 240 241 #define CONFIG_UDP_CHECKSUM 242 243 #endif /* _M5329EVB_H */ 244