1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M5329EVB_H 31 #define _M5329EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF532x /* define processor family */ 38 #define CONFIG_M5329 /* define processor type */ 39 40 #undef DEBUG 41 42 #define CONFIG_MCFSERIAL 43 #define CONFIG_BAUDRATE 115200 44 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 45 46 #undef CONFIG_WATCHDOG 47 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 48 49 #define CFG_NUM_IRQS 128 50 51 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ 52 CFG_CMD_CACHE | \ 53 CFG_CMD_DATE | \ 54 CFG_CMD_ELF | \ 55 CFG_CMD_FLASH | \ 56 (CFG_CMD_LOADB | CFG_CMD_LOADS) | \ 57 CFG_CMD_MEMORY | \ 58 CFG_CMD_MISC | \ 59 CFG_CMD_MII | \ 60 CFG_CMD_NET | \ 61 CFG_CMD_PING | \ 62 CFG_CMD_REGINFO \ 63 ) 64 65 #define CONFIG_MCFFEC 66 #ifdef CONFIG_MCFFEC 67 # define CONFIG_NET_MULTI 1 68 # define CONFIG_MII 1 69 # define CFG_DISCOVER_PHY 70 # define CFG_RX_ETH_BUFFER 8 71 # define CFG_FAULT_ECHO_LINK_DOWN 72 73 # define CFG_FEC0_IOBASE 0xFC030000 74 # define CFG_FEC0_PINMUX 0 75 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE 76 # define MCFFEC_TOUT_LOOP 50000 77 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ 78 # ifndef CFG_DISCOVER_PHY 79 # define FECDUPLEX FULL 80 # define FECSPEED _100BASET 81 # else 82 # ifndef CFG_FAULT_ECHO_LINK_DOWN 83 # define CFG_FAULT_ECHO_LINK_DOWN 84 # endif 85 # endif /* CFG_DISCOVER_PHY */ 86 #endif 87 88 #define CONFIG_MCFUART 89 #ifdef CONFIG_MCFUART 90 # define CFG_UART_PORT (0) 91 # define CFG_UART_BASE (0xFC060000) 92 #endif 93 94 #define CONFIG_MCFRTC 95 #ifdef CONFIG_MCFRTC 96 # define CFG_MCFRTC_BASE (0xFC0A8000) 97 # undef RTC_DEBUG 98 #endif 99 100 /* Timer */ 101 #define CONFIG_MCFTMR 102 #ifdef CONFIG_MCFTMR 103 # define CFG_UDELAY_BASE (0xFC070000) 104 # define CFG_TMR_BASE (0xFC074000) 105 # define CFG_TMRINTR_NO (33) 106 # define CFG_TMRINTR_MASK (2) 107 # define CFG_TMRINTR_PRI (6) 108 # define CFG_TIMER_PRESCALER (((CFG_CLK / 1000000) - 1) << 8) 109 #endif 110 111 #undef CONFIG_MCFPIT 112 #ifdef CONFIG_MCFPIT 113 # define CFG_UDELAY_BASE (0xFC080000) 114 # define CFG_PIT_BASE (0xFC084000) 115 # define CFG_PIT_PRESCALE (6) 116 #endif 117 118 #define CONFIG_MCFINTC 119 #ifdef CONFIG_MCFINTC 120 # define CFG_INTR_BASE (0xFC048000) 121 # define CFG_NUM_IRQ0 64 122 # define CFG_NUM_IRQ1 64 123 #endif 124 125 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 126 #include <cmd_confdefs.h> 127 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 128 #ifdef CONFIG_MCFFEC 129 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 130 # define CONFIG_IPADDR 192.162.1.2 131 # define CONFIG_NETMASK 255.255.255.0 132 # define CONFIG_SERVERIP 192.162.1.1 133 # define CONFIG_GATEWAYIP 192.162.1.1 134 # define CONFIG_OVERWRITE_ETHADDR_ONCE 135 #endif /* FEC_ENET */ 136 137 #define CONFIG_HOSTNAME M5329EVB 138 #define CONFIG_EXTRA_ENV_SETTINGS \ 139 "netdev=eth0\0" \ 140 "loadaddr=40010000\0" \ 141 "u-boot=u-boot.bin\0" \ 142 "load=tftp ${loadaddr) ${u-boot}\0" \ 143 "upd=run load; run prog\0" \ 144 "prog=prot off 0 2ffff;" \ 145 "era 0 2ffff;" \ 146 "cp.b ${loadaddr} 0 ${filesize};" \ 147 "save\0" \ 148 "" 149 150 #define CONFIG_PRAM 512 /* 512 KB */ 151 #define CFG_PROMPT "-> " 152 #define CFG_LONGHELP /* undef to save memory */ 153 154 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 155 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 156 #else 157 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 158 #endif 159 160 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 161 #define CFG_MAXARGS 16 /* max number of command args */ 162 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 163 #define CFG_LOAD_ADDR 0x40010000 164 165 #define CFG_HZ 1000 166 #define CFG_CLK 80000000 167 #define CFG_CPU_CLK CFG_CLK * 3 168 169 #define CFG_MBAR 0xFC000000 170 171 /* 172 * Low Level Configuration Settings 173 * (address mappings, register initial values, etc.) 174 * You should know what you are doing if you make changes here. 175 */ 176 /*----------------------------------------------------------------------- 177 * Definitions for initial stack pointer and data area (in DPRAM) 178 */ 179 #define CFG_INIT_RAM_ADDR 0x80000000 180 #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ 181 #define CFG_INIT_RAM_CTRL 0x221 182 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 183 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 184 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 185 186 /*----------------------------------------------------------------------- 187 * Start addresses for the final memory configuration 188 * (Set up by the startup code) 189 * Please note that CFG_SDRAM_BASE _must_ start at 0 190 */ 191 #define CFG_SDRAM_BASE 0x40000000 192 #define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ 193 #define CFG_SDRAM_CFG1 0x53722730 194 #define CFG_SDRAM_CFG2 0x56670000 195 #define CFG_SDRAM_CTRL 0xE1092000 196 #define CFG_SDRAM_EMOD 0x40010000 197 #define CFG_SDRAM_MODE 0x018D0000 198 199 #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 200 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) 201 202 #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) 203 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 204 205 #define CFG_BOOTPARAMS_LEN 64*1024 206 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 207 208 /* 209 * For booting Linux, the board info and command line data 210 * have to be in the first 8 MB of memory, since this is 211 * the maximum mapped by the Linux kernel during initialization ?? 212 */ 213 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 214 215 /*----------------------------------------------------------------------- 216 * FLASH organization 217 */ 218 #undef CFG_FLASH_CFI 219 #ifdef CFG_FLASH_CFI 220 # define CFG_FLASH_CFI_DRIVER 1 221 # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ 222 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT 223 #else 224 # define CFG_FLASH_UNLOCK_TOUT 1000 225 # define CFG_FLASH_WRITE_TOUT 1000 226 #endif 227 228 #define CFG_FLASH_BASE 0 229 #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) 230 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ 231 #define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 232 #define CFG_FLASH_ERASE_TOUT 1000 233 #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 234 235 /* Configuration for environment 236 * Environment is embedded in u-boot in the second sector of the flash 237 */ 238 #define CFG_ENV_OFFSET 0x4000 239 #define CFG_ENV_SECT_SIZE 0x2000 240 #define CFG_ENV_IS_IN_FLASH 1 241 #define CFG_ENV_IS_EMBEDDED 1 242 243 /*----------------------------------------------------------------------- 244 * Cache Configuration 245 */ 246 #define CFG_CACHELINE_SIZE 16 247 248 /*----------------------------------------------------------------------- 249 * Chipselect bank definitions 250 */ 251 /* 252 * CS0 - NOR Flash 1, 2, 4, or 8MB 253 * CS1 - CompactFlash and registers 254 * CS2 - NAND Flash 16, 32, or 64MB 255 * CS3 - Available 256 * CS4 - Available 257 * CS5 - Available 258 */ 259 #define CFG_CS0_BASE 0 260 #define CFG_CS0_MASK 0x007f0001 261 #define CFG_CS0_CTRL 0x00001fa0 262 263 #define CFG_CS1_BASE 0x1000 264 #define CFG_CS1_MASK 0x001f0001 265 #define CFG_CS1_CTRL 0x002A3780 266 267 #ifdef NANDFLASH_SIZE 268 #define CFG_CS2_BASE 0x00800000 269 #define CFG_CS2_MASK 0x00ff0001 270 #define CFG_CS2_CTRL 0x00001f60 271 #endif 272 273 #define CONFIG_UDP_CHECKSUM 274 275 #endif /* _M5329EVB_H */ 276