1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M5329EVB_H 31 #define _M5329EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF532x /* define processor family */ 38 #define CONFIG_M5329 /* define processor type */ 39 40 #undef DEBUG 41 42 #define CONFIG_MCFSERIAL 43 #define CONFIG_BAUDRATE 115200 44 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 45 46 #undef CONFIG_WATCHDOG 47 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 48 49 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ 50 CFG_CMD_CACHE | \ 51 CFG_CMD_DATE | \ 52 CFG_CMD_ELF | \ 53 CFG_CMD_FLASH | \ 54 (CFG_CMD_LOADB | CFG_CMD_LOADS) | \ 55 CFG_CMD_MEMORY | \ 56 CFG_CMD_MISC | \ 57 CFG_CMD_MII | \ 58 CFG_CMD_NET | \ 59 CFG_CMD_PING | \ 60 CFG_CMD_REGINFO \ 61 ) 62 63 #define CONFIG_MCFFEC 64 #ifdef CONFIG_MCFFEC 65 # define CONFIG_NET_MULTI 1 66 # define CONFIG_MII 1 67 # define CFG_DISCOVER_PHY 68 # define CFG_RX_ETH_BUFFER 8 69 # define CFG_FAULT_ECHO_LINK_DOWN 70 71 # define CFG_FEC0_PINMUX 0 72 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE 73 # define MCFFEC_TOUT_LOOP 50000 74 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ 75 # ifndef CFG_DISCOVER_PHY 76 # define FECDUPLEX FULL 77 # define FECSPEED _100BASET 78 # else 79 # ifndef CFG_FAULT_ECHO_LINK_DOWN 80 # define CFG_FAULT_ECHO_LINK_DOWN 81 # endif 82 # endif /* CFG_DISCOVER_PHY */ 83 #endif 84 85 #define CONFIG_MCFUART 86 #define CFG_UART_PORT (0) 87 88 #define CONFIG_MCFRTC 89 #undef RTC_DEBUG 90 91 /* Timer */ 92 #define CONFIG_MCFTMR 93 #undef CONFIG_MCFPIT 94 95 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 96 #include <cmd_confdefs.h> 97 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 98 #ifdef CONFIG_MCFFEC 99 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 100 # define CONFIG_IPADDR 192.162.1.2 101 # define CONFIG_NETMASK 255.255.255.0 102 # define CONFIG_SERVERIP 192.162.1.1 103 # define CONFIG_GATEWAYIP 192.162.1.1 104 # define CONFIG_OVERWRITE_ETHADDR_ONCE 105 #endif /* FEC_ENET */ 106 107 #define CONFIG_HOSTNAME M5329EVB 108 #define CONFIG_EXTRA_ENV_SETTINGS \ 109 "netdev=eth0\0" \ 110 "loadaddr=40010000\0" \ 111 "u-boot=u-boot.bin\0" \ 112 "load=tftp ${loadaddr) ${u-boot}\0" \ 113 "upd=run load; run prog\0" \ 114 "prog=prot off 0 2ffff;" \ 115 "era 0 2ffff;" \ 116 "cp.b ${loadaddr} 0 ${filesize};" \ 117 "save\0" \ 118 "" 119 120 #define CONFIG_PRAM 512 /* 512 KB */ 121 #define CFG_PROMPT "-> " 122 #define CFG_LONGHELP /* undef to save memory */ 123 124 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 125 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 126 #else 127 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 128 #endif 129 130 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 131 #define CFG_MAXARGS 16 /* max number of command args */ 132 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 133 #define CFG_LOAD_ADDR 0x40010000 134 135 #define CFG_HZ 1000 136 #define CFG_CLK 80000000 137 #define CFG_CPU_CLK CFG_CLK * 3 138 139 #define CFG_MBAR 0xFC000000 140 141 /* 142 * Low Level Configuration Settings 143 * (address mappings, register initial values, etc.) 144 * You should know what you are doing if you make changes here. 145 */ 146 /*----------------------------------------------------------------------- 147 * Definitions for initial stack pointer and data area (in DPRAM) 148 */ 149 #define CFG_INIT_RAM_ADDR 0x80000000 150 #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ 151 #define CFG_INIT_RAM_CTRL 0x221 152 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 153 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 154 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 155 156 /*----------------------------------------------------------------------- 157 * Start addresses for the final memory configuration 158 * (Set up by the startup code) 159 * Please note that CFG_SDRAM_BASE _must_ start at 0 160 */ 161 #define CFG_SDRAM_BASE 0x40000000 162 #define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ 163 #define CFG_SDRAM_CFG1 0x53722730 164 #define CFG_SDRAM_CFG2 0x56670000 165 #define CFG_SDRAM_CTRL 0xE1092000 166 #define CFG_SDRAM_EMOD 0x40010000 167 #define CFG_SDRAM_MODE 0x018D0000 168 169 #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 170 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) 171 172 #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) 173 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 174 175 #define CFG_BOOTPARAMS_LEN 64*1024 176 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 177 178 /* 179 * For booting Linux, the board info and command line data 180 * have to be in the first 8 MB of memory, since this is 181 * the maximum mapped by the Linux kernel during initialization ?? 182 */ 183 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 184 185 /*----------------------------------------------------------------------- 186 * FLASH organization 187 */ 188 #define CFG_FLASH_CFI 189 #ifdef CFG_FLASH_CFI 190 # define CFG_FLASH_CFI_DRIVER 1 191 # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ 192 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT 193 # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ 194 # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 195 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 196 #endif 197 198 #define CFG_FLASH_BASE 0 199 #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) 200 201 /* Configuration for environment 202 * Environment is embedded in u-boot in the second sector of the flash 203 */ 204 #define CFG_ENV_OFFSET 0x4000 205 #define CFG_ENV_SECT_SIZE 0x2000 206 #define CFG_ENV_IS_IN_FLASH 1 207 #define CFG_ENV_IS_EMBEDDED 1 208 209 /*----------------------------------------------------------------------- 210 * Cache Configuration 211 */ 212 #define CFG_CACHELINE_SIZE 16 213 214 /*----------------------------------------------------------------------- 215 * Chipselect bank definitions 216 */ 217 /* 218 * CS0 - NOR Flash 1, 2, 4, or 8MB 219 * CS1 - CompactFlash and registers 220 * CS2 - NAND Flash 16, 32, or 64MB 221 * CS3 - Available 222 * CS4 - Available 223 * CS5 - Available 224 */ 225 #define CFG_CS0_BASE 0 226 #define CFG_CS0_MASK 0x007f0001 227 #define CFG_CS0_CTRL 0x00001fa0 228 229 #define CFG_CS1_BASE 0x1000 230 #define CFG_CS1_MASK 0x001f0001 231 #define CFG_CS1_CTRL 0x002A3780 232 233 #ifdef NANDFLASH_SIZE 234 #define CFG_CS2_BASE 0x00800000 235 #define CFG_CS2_MASK 0x00ff0001 236 #define CFG_CS2_CTRL 0x00001f60 237 #endif 238 239 #define CONFIG_UDP_CHECKSUM 240 241 #endif /* _M5329EVB_H */ 242