1 /* 2 * Configuation settings for the Motorola MC5282EVB board. 3 * 4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _CONFIG_M5282EVB_H 14 #define _CONFIG_M5282EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 #define CONFIG_MCFTMR 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 #define CONFIG_BAUDRATE 115200 25 26 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 27 28 /* Configuration for environment 29 * Environment is embedded in u-boot in the second sector of the flash 30 */ 31 #define CONFIG_ENV_ADDR 0xffe04000 32 #define CONFIG_ENV_SIZE 0x2000 33 #define CONFIG_ENV_IS_IN_FLASH 1 34 35 #define LDS_BOARD_TEXT \ 36 . = DEFINED(env_offset) ? env_offset : .; \ 37 common/env_embedded.o (.text*); 38 39 /* 40 * BOOTP options 41 */ 42 #define CONFIG_BOOTP_BOOTFILESIZE 43 #define CONFIG_BOOTP_BOOTPATH 44 #define CONFIG_BOOTP_GATEWAY 45 #define CONFIG_BOOTP_HOSTNAME 46 47 /* 48 * Command line configuration. 49 */ 50 #define CONFIG_CMD_CACHE 51 #define CONFIG_CMD_MII 52 53 #define CONFIG_MCFFEC 54 #ifdef CONFIG_MCFFEC 55 # define CONFIG_MII 1 56 # define CONFIG_MII_INIT 1 57 # define CONFIG_SYS_DISCOVER_PHY 58 # define CONFIG_SYS_RX_ETH_BUFFER 8 59 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 60 61 # define CONFIG_SYS_FEC0_PINMUX 0 62 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 63 # define MCFFEC_TOUT_LOOP 50000 64 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 65 # ifndef CONFIG_SYS_DISCOVER_PHY 66 # define FECDUPLEX FULL 67 # define FECSPEED _100BASET 68 # else 69 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 70 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 71 # endif 72 # endif /* CONFIG_SYS_DISCOVER_PHY */ 73 #endif 74 75 #define CONFIG_BOOTDELAY 5 76 #ifdef CONFIG_MCFFEC 77 # define CONFIG_IPADDR 192.162.1.2 78 # define CONFIG_NETMASK 255.255.255.0 79 # define CONFIG_SERVERIP 192.162.1.1 80 # define CONFIG_GATEWAYIP 192.162.1.1 81 #endif /* CONFIG_MCFFEC */ 82 83 #define CONFIG_HOSTNAME M5282EVB 84 #define CONFIG_EXTRA_ENV_SETTINGS \ 85 "netdev=eth0\0" \ 86 "loadaddr=10000\0" \ 87 "u-boot=u-boot.bin\0" \ 88 "load=tftp ${loadaddr) ${u-boot}\0" \ 89 "upd=run load; run prog\0" \ 90 "prog=prot off ffe00000 ffe3ffff;" \ 91 "era ffe00000 ffe3ffff;" \ 92 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 93 "save\0" \ 94 "" 95 96 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 97 98 #if defined(CONFIG_CMD_KGDB) 99 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 100 #else 101 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 102 #endif 103 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 104 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 105 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 106 107 #define CONFIG_SYS_LOAD_ADDR 0x20000 108 109 #define CONFIG_SYS_MEMTEST_START 0x400 110 #define CONFIG_SYS_MEMTEST_END 0x380000 111 112 #define CONFIG_SYS_CLK 64000000 113 114 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ 115 116 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 117 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 118 119 /* 120 * Low Level Configuration Settings 121 * (address mappings, register initial values, etc.) 122 * You should know what you are doing if you make changes here. 123 */ 124 #define CONFIG_SYS_MBAR 0x40000000 125 126 /*----------------------------------------------------------------------- 127 * Definitions for initial stack pointer and data area (in DPRAM) 128 */ 129 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 130 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 131 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 132 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 133 134 /*----------------------------------------------------------------------- 135 * Start addresses for the final memory configuration 136 * (Set up by the startup code) 137 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 138 */ 139 #define CONFIG_SYS_SDRAM_BASE 0x00000000 140 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 141 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 142 #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 143 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 144 145 /* If M5282 port is fully implemented the monitor base will be behind 146 * the vector table. */ 147 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) 148 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 149 #else 150 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ 151 #endif 152 153 #define CONFIG_SYS_MONITOR_LEN 0x20000 154 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 155 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 156 157 /* 158 * For booting Linux, the board info and command line data 159 * have to be in the first 8 MB of memory, since this is 160 * the maximum mapped by the Linux kernel during initialization ?? 161 */ 162 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 163 164 /*----------------------------------------------------------------------- 165 * FLASH organization 166 */ 167 #define CONFIG_SYS_FLASH_CFI 168 #ifdef CONFIG_SYS_FLASH_CFI 169 170 # define CONFIG_FLASH_CFI_DRIVER 1 171 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 172 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 173 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 174 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 175 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 176 # define CONFIG_SYS_FLASH_CHECKSUM 177 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 178 #endif 179 180 /*----------------------------------------------------------------------- 181 * Cache Configuration 182 */ 183 #define CONFIG_SYS_CACHELINE_SIZE 16 184 185 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 186 CONFIG_SYS_INIT_RAM_SIZE - 8) 187 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 188 CONFIG_SYS_INIT_RAM_SIZE - 4) 189 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 190 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 191 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 192 CF_ACR_EN | CF_ACR_SM_ALL) 193 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 194 CF_CACR_CEIB | CF_CACR_DBWE | \ 195 CF_CACR_EUSP) 196 197 /*----------------------------------------------------------------------- 198 * Memory bank definitions 199 */ 200 #define CONFIG_SYS_CS0_BASE 0xFFE00000 201 #define CONFIG_SYS_CS0_CTRL 0x00001980 202 #define CONFIG_SYS_CS0_MASK 0x001F0001 203 204 /*----------------------------------------------------------------------- 205 * Port configuration 206 */ 207 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 208 #define CONFIG_SYS_PADDR 0x0000000 209 #define CONFIG_SYS_PADAT 0x0000000 210 211 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 212 #define CONFIG_SYS_PBDDR 0x0000000 213 #define CONFIG_SYS_PBDAT 0x0000000 214 215 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 216 #define CONFIG_SYS_PCDDR 0x0000000 217 #define CONFIG_SYS_PCDAT 0x0000000 218 219 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 220 #define CONFIG_SYS_PCDDR 0x0000000 221 #define CONFIG_SYS_PCDAT 0x0000000 222 223 #define CONFIG_SYS_PEHLPAR 0xC0 224 #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ 225 #define CONFIG_SYS_DDRUA 0x05 226 #define CONFIG_SYS_PJPAR 0xFF 227 228 #endif /* _CONFIG_M5282EVB_H */ 229