1 /* 2 * Configuation settings for the Motorola MC5275EVB board. 3 * 4 * By Arthur Shipkowski <art@videon-central.com> 5 * Copyright (C) 2005 Videon Central, Inc. 6 * 7 * Based off of M5272C3 board code by Josef Baumgartner 8 * <josef.baumgartner@telex.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * board/config.h - configuration options, board specific 15 */ 16 17 #ifndef _M5275EVB_H 18 #define _M5275EVB_H 19 20 /* 21 * High Level Configuration Options 22 * (easy to change) 23 */ 24 #define CONFIG_M5275EVB /* define board type */ 25 26 #define CONFIG_MCFTMR 27 28 #define CONFIG_MCFUART 29 #define CONFIG_SYS_UART_PORT (0) 30 #define CONFIG_BAUDRATE 115200 31 32 /* Configuration for environment 33 * Environment is embedded in u-boot in the second sector of the flash 34 */ 35 #ifndef CONFIG_MONITOR_IS_IN_RAM 36 #define CONFIG_ENV_OFFSET 0x4000 37 #define CONFIG_ENV_SECT_SIZE 0x2000 38 #define CONFIG_ENV_IS_IN_FLASH 1 39 #else 40 #define CONFIG_ENV_ADDR 0xffe04000 41 #define CONFIG_ENV_SECT_SIZE 0x2000 42 #define CONFIG_ENV_IS_IN_FLASH 1 43 #endif 44 45 #define LDS_BOARD_TEXT \ 46 . = DEFINED(env_offset) ? env_offset : .; \ 47 common/env_embedded.o (.text); 48 49 /* 50 * BOOTP options 51 */ 52 #define CONFIG_BOOTP_BOOTFILESIZE 53 #define CONFIG_BOOTP_BOOTPATH 54 #define CONFIG_BOOTP_GATEWAY 55 #define CONFIG_BOOTP_HOSTNAME 56 57 /* Available command configuration */ 58 #define CONFIG_CMD_CACHE 59 #define CONFIG_CMD_MII 60 61 62 #define CONFIG_MCFFEC 63 #ifdef CONFIG_MCFFEC 64 #define CONFIG_MII 1 65 #define CONFIG_MII_INIT 1 66 #define CONFIG_SYS_DISCOVER_PHY 67 #define CONFIG_SYS_RX_ETH_BUFFER 8 68 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 69 #define CONFIG_SYS_FEC0_PINMUX 0 70 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 71 #define CONFIG_SYS_FEC1_PINMUX 0 72 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE 73 #define MCFFEC_TOUT_LOOP 50000 74 #define CONFIG_HAS_ETH1 75 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 76 #ifndef CONFIG_SYS_DISCOVER_PHY 77 #define FECDUPLEX FULL 78 #define FECSPEED _100BASET 79 #else 80 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 81 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 82 #endif 83 #endif 84 #endif 85 86 /* I2C */ 87 #define CONFIG_SYS_I2C 88 #define CONFIG_SYS_I2C_FSL 89 #define CONFIG_SYS_FSL_I2C_SPEED 80000 90 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 91 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 92 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 93 #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) 94 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) 95 #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) 96 97 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 98 99 #if (CONFIG_CMD_KGDB) 100 # define CONFIG_SYS_CBSIZE 1024 101 #else 102 # define CONFIG_SYS_CBSIZE 256 103 #endif 104 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 105 #define CONFIG_SYS_MAXARGS 16 106 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 107 108 #define CONFIG_SYS_LOAD_ADDR 0x800000 109 110 #define CONFIG_BOOTDELAY 5 111 #define CONFIG_BOOTCOMMAND "bootm ffe40000" 112 #define CONFIG_SYS_MEMTEST_START 0x400 113 #define CONFIG_SYS_MEMTEST_END 0x380000 114 115 #ifdef CONFIG_MCFFEC 116 # define CONFIG_NET_RETRY_COUNT 5 117 # define CONFIG_OVERWRITE_ETHADDR_ONCE 118 #endif /* FEC_ENET */ 119 120 #define CONFIG_EXTRA_ENV_SETTINGS \ 121 "netdev=eth0\0" \ 122 "loadaddr=10000\0" \ 123 "uboot=u-boot.bin\0" \ 124 "load=tftp ${loadaddr} ${uboot}\0" \ 125 "upd=run load; run prog\0" \ 126 "prog=prot off ffe00000 ffe3ffff;" \ 127 "era ffe00000 ffe3ffff;" \ 128 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 129 "save\0" \ 130 "" 131 132 #define CONFIG_SYS_CLK 150000000 133 134 /* 135 * Low Level Configuration Settings 136 * (address mappings, register initial values, etc.) 137 * You should know what you are doing if you make changes here. 138 */ 139 140 #define CONFIG_SYS_MBAR 0x40000000 141 142 /*----------------------------------------------------------------------- 143 * Definitions for initial stack pointer and data area (in DPRAM) 144 */ 145 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 146 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 147 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 148 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 149 150 /*----------------------------------------------------------------------- 151 * Start addresses for the final memory configuration 152 * (Set up by the startup code) 153 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 154 */ 155 #define CONFIG_SYS_SDRAM_BASE 0x00000000 156 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 157 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 158 159 #ifdef CONFIG_MONITOR_IS_IN_RAM 160 #define CONFIG_SYS_MONITOR_BASE 0x20000 161 #else 162 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 163 #endif 164 165 #define CONFIG_SYS_MONITOR_LEN 0x20000 166 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 167 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 168 169 /* 170 * For booting Linux, the board info and command line data 171 * have to be in the first 8 MB of memory, since this is 172 * the maximum mapped by the Linux kernel during initialization ?? 173 */ 174 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 175 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 176 177 /*----------------------------------------------------------------------- 178 * FLASH organization 179 */ 180 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 181 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ 182 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 183 184 #define CONFIG_SYS_FLASH_CFI 1 185 #define CONFIG_FLASH_CFI_DRIVER 1 186 #define CONFIG_SYS_FLASH_SIZE 0x200000 187 188 /*----------------------------------------------------------------------- 189 * Cache Configuration 190 */ 191 #define CONFIG_SYS_CACHELINE_SIZE 16 192 193 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 194 CONFIG_SYS_INIT_RAM_SIZE - 8) 195 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 196 CONFIG_SYS_INIT_RAM_SIZE - 4) 197 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 198 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 199 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 200 CF_ACR_EN | CF_ACR_SM_ALL) 201 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 202 CF_CACR_DISD | CF_CACR_INVI | \ 203 CF_CACR_CEIB | CF_CACR_DCM | \ 204 CF_CACR_EUSP) 205 206 /*----------------------------------------------------------------------- 207 * Memory bank definitions 208 */ 209 #define CONFIG_SYS_CS0_BASE 0xffe00000 210 #define CONFIG_SYS_CS0_CTRL 0x00001980 211 #define CONFIG_SYS_CS0_MASK 0x001F0001 212 213 #define CONFIG_SYS_CS1_BASE 0x30000000 214 #define CONFIG_SYS_CS1_CTRL 0x00001900 215 #define CONFIG_SYS_CS1_MASK 0x00070001 216 217 /*----------------------------------------------------------------------- 218 * Port configuration 219 */ 220 #define CONFIG_SYS_FECI2C 0x0FA0 221 222 #endif /* _M5275EVB_H */ 223