1 /* 2 * Configuation settings for the Motorola MC5275EVB board. 3 * 4 * By Arthur Shipkowski <art@videon-central.com> 5 * Copyright (C) 2005 Videon Central, Inc. 6 * 7 * Based off of M5272C3 board code by Josef Baumgartner 8 * <josef.baumgartner@telex.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * board/config.h - configuration options, board specific 15 */ 16 17 #ifndef _M5275EVB_H 18 #define _M5275EVB_H 19 20 /* 21 * High Level Configuration Options 22 * (easy to change) 23 */ 24 #define CONFIG_M5275EVB /* define board type */ 25 26 #define CONFIG_MCFTMR 27 28 #define CONFIG_MCFUART 29 #define CONFIG_SYS_UART_PORT (0) 30 31 /* Configuration for environment 32 * Environment is embedded in u-boot in the second sector of the flash 33 */ 34 #ifndef CONFIG_MONITOR_IS_IN_RAM 35 #define CONFIG_ENV_OFFSET 0x4000 36 #define CONFIG_ENV_SECT_SIZE 0x2000 37 #else 38 #define CONFIG_ENV_ADDR 0xffe04000 39 #define CONFIG_ENV_SECT_SIZE 0x2000 40 #endif 41 42 #define LDS_BOARD_TEXT \ 43 . = DEFINED(env_offset) ? env_offset : .; \ 44 env/embedded.o(.text); 45 46 /* 47 * BOOTP options 48 */ 49 #define CONFIG_BOOTP_BOOTFILESIZE 50 #define CONFIG_BOOTP_BOOTPATH 51 #define CONFIG_BOOTP_GATEWAY 52 #define CONFIG_BOOTP_HOSTNAME 53 54 /* Available command configuration */ 55 56 #define CONFIG_MCFFEC 57 #ifdef CONFIG_MCFFEC 58 #define CONFIG_MII 1 59 #define CONFIG_MII_INIT 1 60 #define CONFIG_SYS_DISCOVER_PHY 61 #define CONFIG_SYS_RX_ETH_BUFFER 8 62 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 63 #define CONFIG_SYS_FEC0_PINMUX 0 64 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 65 #define CONFIG_SYS_FEC1_PINMUX 0 66 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE 67 #define MCFFEC_TOUT_LOOP 50000 68 #define CONFIG_HAS_ETH1 69 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 70 #ifndef CONFIG_SYS_DISCOVER_PHY 71 #define FECDUPLEX FULL 72 #define FECSPEED _100BASET 73 #else 74 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 75 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 76 #endif 77 #endif 78 #endif 79 80 /* I2C */ 81 #define CONFIG_SYS_I2C 82 #define CONFIG_SYS_I2C_FSL 83 #define CONFIG_SYS_FSL_I2C_SPEED 80000 84 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 85 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 86 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 87 #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) 88 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) 89 #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) 90 91 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 92 93 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 94 #define CONFIG_SYS_MAXARGS 16 95 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 96 97 #define CONFIG_SYS_LOAD_ADDR 0x800000 98 99 #define CONFIG_BOOTCOMMAND "bootm ffe40000" 100 #define CONFIG_SYS_MEMTEST_START 0x400 101 #define CONFIG_SYS_MEMTEST_END 0x380000 102 103 #ifdef CONFIG_MCFFEC 104 # define CONFIG_NET_RETRY_COUNT 5 105 # define CONFIG_OVERWRITE_ETHADDR_ONCE 106 #endif /* FEC_ENET */ 107 108 #define CONFIG_EXTRA_ENV_SETTINGS \ 109 "netdev=eth0\0" \ 110 "loadaddr=10000\0" \ 111 "uboot=u-boot.bin\0" \ 112 "load=tftp ${loadaddr} ${uboot}\0" \ 113 "upd=run load; run prog\0" \ 114 "prog=prot off ffe00000 ffe3ffff;" \ 115 "era ffe00000 ffe3ffff;" \ 116 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 117 "save\0" \ 118 "" 119 120 #define CONFIG_SYS_CLK 150000000 121 122 /* 123 * Low Level Configuration Settings 124 * (address mappings, register initial values, etc.) 125 * You should know what you are doing if you make changes here. 126 */ 127 128 #define CONFIG_SYS_MBAR 0x40000000 129 130 /*----------------------------------------------------------------------- 131 * Definitions for initial stack pointer and data area (in DPRAM) 132 */ 133 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 134 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 135 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 136 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 137 138 /*----------------------------------------------------------------------- 139 * Start addresses for the final memory configuration 140 * (Set up by the startup code) 141 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 142 */ 143 #define CONFIG_SYS_SDRAM_BASE 0x00000000 144 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 145 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 146 147 #ifdef CONFIG_MONITOR_IS_IN_RAM 148 #define CONFIG_SYS_MONITOR_BASE 0x20000 149 #else 150 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 151 #endif 152 153 #define CONFIG_SYS_MONITOR_LEN 0x20000 154 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 155 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 156 157 /* 158 * For booting Linux, the board info and command line data 159 * have to be in the first 8 MB of memory, since this is 160 * the maximum mapped by the Linux kernel during initialization ?? 161 */ 162 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 163 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 164 165 /*----------------------------------------------------------------------- 166 * FLASH organization 167 */ 168 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 169 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ 170 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 171 172 #define CONFIG_SYS_FLASH_CFI 1 173 #define CONFIG_FLASH_CFI_DRIVER 1 174 #define CONFIG_SYS_FLASH_SIZE 0x200000 175 176 /*----------------------------------------------------------------------- 177 * Cache Configuration 178 */ 179 #define CONFIG_SYS_CACHELINE_SIZE 16 180 181 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 182 CONFIG_SYS_INIT_RAM_SIZE - 8) 183 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 184 CONFIG_SYS_INIT_RAM_SIZE - 4) 185 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 186 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 187 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 188 CF_ACR_EN | CF_ACR_SM_ALL) 189 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 190 CF_CACR_DISD | CF_CACR_INVI | \ 191 CF_CACR_CEIB | CF_CACR_DCM | \ 192 CF_CACR_EUSP) 193 194 /*----------------------------------------------------------------------- 195 * Memory bank definitions 196 */ 197 #define CONFIG_SYS_CS0_BASE 0xffe00000 198 #define CONFIG_SYS_CS0_CTRL 0x00001980 199 #define CONFIG_SYS_CS0_MASK 0x001F0001 200 201 #define CONFIG_SYS_CS1_BASE 0x30000000 202 #define CONFIG_SYS_CS1_CTRL 0x00001900 203 #define CONFIG_SYS_CS1_MASK 0x00070001 204 205 /*----------------------------------------------------------------------- 206 * Port configuration 207 */ 208 #define CONFIG_SYS_FECI2C 0x0FA0 209 210 #endif /* _M5275EVB_H */ 211