xref: /rk3399_rockchip-uboot/include/configs/M5275EVB.h (revision 545c8e0a7cd3ca9d3846668f69b0d201250abea8)
1*545c8e0aSMatthew Fettke /*
2*545c8e0aSMatthew Fettke  * Configuation settings for the Motorola MC5275EVB board.
3*545c8e0aSMatthew Fettke  *
4*545c8e0aSMatthew Fettke  * By Arthur Shipkowski <art@videon-central.com>
5*545c8e0aSMatthew Fettke  * Copyright (C) 2005 Videon Central, Inc.
6*545c8e0aSMatthew Fettke  *
7*545c8e0aSMatthew Fettke  * Based off of M5272C3 board code by Josef Baumgartner
8*545c8e0aSMatthew Fettke  * <josef.baumgartner@telex.de>
9*545c8e0aSMatthew Fettke  *
10*545c8e0aSMatthew Fettke  * See file CREDITS for list of people who contributed to this
11*545c8e0aSMatthew Fettke  * project.
12*545c8e0aSMatthew Fettke  *
13*545c8e0aSMatthew Fettke  * This program is free software; you can redistribute it and/or
14*545c8e0aSMatthew Fettke  * modify it under the terms of the GNU General Public License as
15*545c8e0aSMatthew Fettke  * published by the Free Software Foundation; either version 2 of
16*545c8e0aSMatthew Fettke  * the License, or (at your option) any later version.
17*545c8e0aSMatthew Fettke  *
18*545c8e0aSMatthew Fettke  * This program is distributed in the hope that it will be useful,
19*545c8e0aSMatthew Fettke  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20*545c8e0aSMatthew Fettke  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
21*545c8e0aSMatthew Fettke  * GNU General Public License for more details.
22*545c8e0aSMatthew Fettke  *
23*545c8e0aSMatthew Fettke  * You should have received a copy of the GNU General Public License
24*545c8e0aSMatthew Fettke  * along with this program; if not, write to the Free Software
25*545c8e0aSMatthew Fettke  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26*545c8e0aSMatthew Fettke  * MA 02111-1307 USA
27*545c8e0aSMatthew Fettke  */
28*545c8e0aSMatthew Fettke 
29*545c8e0aSMatthew Fettke /*
30*545c8e0aSMatthew Fettke  * board/config.h - configuration options, board specific
31*545c8e0aSMatthew Fettke  */
32*545c8e0aSMatthew Fettke 
33*545c8e0aSMatthew Fettke #ifndef _M5275EVB_H
34*545c8e0aSMatthew Fettke #define _M5275EVB_H
35*545c8e0aSMatthew Fettke 
36*545c8e0aSMatthew Fettke /*
37*545c8e0aSMatthew Fettke  * High Level Configuration Options
38*545c8e0aSMatthew Fettke  * (easy to change)
39*545c8e0aSMatthew Fettke  */
40*545c8e0aSMatthew Fettke #define CONFIG_MCF52x2			/* define processor family */
41*545c8e0aSMatthew Fettke #define CONFIG_M5275			/* define processor type */
42*545c8e0aSMatthew Fettke #define CONFIG_M5275EVB			/* define board type */
43*545c8e0aSMatthew Fettke 
44*545c8e0aSMatthew Fettke #define CONFIG_MCFTMR
45*545c8e0aSMatthew Fettke 
46*545c8e0aSMatthew Fettke #define CONFIG_MCFUART
47*545c8e0aSMatthew Fettke #define CFG_UART_PORT		(0)
48*545c8e0aSMatthew Fettke #define CONFIG_BAUDRATE		19200
49*545c8e0aSMatthew Fettke #define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
50*545c8e0aSMatthew Fettke 
51*545c8e0aSMatthew Fettke /* Configuration for environment
52*545c8e0aSMatthew Fettke  * Environment is embedded in u-boot in the second sector of the flash
53*545c8e0aSMatthew Fettke  */
54*545c8e0aSMatthew Fettke #ifndef CONFIG_MONITOR_IS_IN_RAM
55*545c8e0aSMatthew Fettke #define CFG_ENV_OFFSET		0x4000
56*545c8e0aSMatthew Fettke #define CFG_ENV_SECT_SIZE	0x2000
57*545c8e0aSMatthew Fettke #define CFG_ENV_IS_IN_FLASH	1
58*545c8e0aSMatthew Fettke #define CFG_ENV_IS_EMBEDDED	1
59*545c8e0aSMatthew Fettke #else
60*545c8e0aSMatthew Fettke #define CFG_ENV_ADDR		0xffe04000
61*545c8e0aSMatthew Fettke #define CFG_ENV_SECT_SIZE	0x2000
62*545c8e0aSMatthew Fettke #define CFG_ENV_IS_IN_FLASH	1
63*545c8e0aSMatthew Fettke #endif
64*545c8e0aSMatthew Fettke 
65*545c8e0aSMatthew Fettke /*
66*545c8e0aSMatthew Fettke  * BOOTP options
67*545c8e0aSMatthew Fettke  */
68*545c8e0aSMatthew Fettke #define CONFIG_BOOTP_BOOTFILESIZE
69*545c8e0aSMatthew Fettke #define CONFIG_BOOTP_BOOTPATH
70*545c8e0aSMatthew Fettke #define CONFIG_BOOTP_GATEWAY
71*545c8e0aSMatthew Fettke #define CONFIG_BOOTP_HOSTNAME
72*545c8e0aSMatthew Fettke 
73*545c8e0aSMatthew Fettke /* Available command configuration */
74*545c8e0aSMatthew Fettke #include <config_cmd_default.h>
75*545c8e0aSMatthew Fettke 
76*545c8e0aSMatthew Fettke #define CONFIG_CMD_PING
77*545c8e0aSMatthew Fettke #define CONFIG_CMD_MII
78*545c8e0aSMatthew Fettke #define CONFIG_CMD_NET
79*545c8e0aSMatthew Fettke #define CONFIG_CMD_ELF
80*545c8e0aSMatthew Fettke #define CONFIG_CMD_FLASH
81*545c8e0aSMatthew Fettke #define CONFIG_CMD_I2C
82*545c8e0aSMatthew Fettke #define CONFIG_CMD_MEMORY
83*545c8e0aSMatthew Fettke #define CONFIG_CMD_DHCP
84*545c8e0aSMatthew Fettke 
85*545c8e0aSMatthew Fettke #undef CONFIG_CMD_LOADS
86*545c8e0aSMatthew Fettke #undef CONFIG_CMD_LOADB
87*545c8e0aSMatthew Fettke 
88*545c8e0aSMatthew Fettke #define CONFIG_MCFFEC
89*545c8e0aSMatthew Fettke #ifdef CONFIG_MCFFEC
90*545c8e0aSMatthew Fettke #define CONFIG_NET_MULTI	1
91*545c8e0aSMatthew Fettke #define CONFIG_MII		1
92*545c8e0aSMatthew Fettke #define CFG_DISCOVER_PHY
93*545c8e0aSMatthew Fettke #define CFG_RX_ETH_BUFFER	8
94*545c8e0aSMatthew Fettke #define CFG_FAULT_ECHO_LINK_DOWN
95*545c8e0aSMatthew Fettke #define CFG_FEC0_PINMUX		0
96*545c8e0aSMatthew Fettke #define CFG_FEC0_MIIBASE	CFG_FEC0_IOBASE
97*545c8e0aSMatthew Fettke #define CFG_FEC1_PINMUX		0
98*545c8e0aSMatthew Fettke #define CFG_FEC1_MIIBASE	CFG_FEC1_IOBASE
99*545c8e0aSMatthew Fettke #define MCFFEC_TOUT_LOOP	50000
100*545c8e0aSMatthew Fettke #define CONFIG_HAS_ETH1
101*545c8e0aSMatthew Fettke /* If CFG_DISCOVER_PHY is not defined - hardcoded */
102*545c8e0aSMatthew Fettke #ifndef CFG_DISCOVER_PHY
103*545c8e0aSMatthew Fettke #define FECDUPLEX		FULL
104*545c8e0aSMatthew Fettke #define FECSPEED		_100BASET
105*545c8e0aSMatthew Fettke #else
106*545c8e0aSMatthew Fettke #ifndef CFG_FAULT_ECHO_LINK_DOWN
107*545c8e0aSMatthew Fettke #define CFG_FAULT_ECHO_LINK_DOWN
108*545c8e0aSMatthew Fettke #endif
109*545c8e0aSMatthew Fettke #endif
110*545c8e0aSMatthew Fettke #endif
111*545c8e0aSMatthew Fettke 
112*545c8e0aSMatthew Fettke /* I2C */
113*545c8e0aSMatthew Fettke #define CONFIG_FSL_I2C
114*545c8e0aSMatthew Fettke #define CONFIG_HARD_I2C		/* I2C with hw support */
115*545c8e0aSMatthew Fettke #undef CONFIG_SOFT_I2C
116*545c8e0aSMatthew Fettke #define CFG_I2C_SPEED		80000
117*545c8e0aSMatthew Fettke #define CFG_I2C_SLAVE		0x7F
118*545c8e0aSMatthew Fettke #define CFG_I2C_OFFSET		0x00000300
119*545c8e0aSMatthew Fettke #define CFG_IMMR		CFG_MBAR
120*545c8e0aSMatthew Fettke 
121*545c8e0aSMatthew Fettke #ifdef CONFIG_MCFFEC
122*545c8e0aSMatthew Fettke #define CONFIG_ETHADDR		00:06:3b:01:41:55
123*545c8e0aSMatthew Fettke #define CONFIG_ETH1ADDR		00:0e:0c:bc:e5:60
124*545c8e0aSMatthew Fettke #endif
125*545c8e0aSMatthew Fettke 
126*545c8e0aSMatthew Fettke #define CFG_PROMPT		"-> "
127*545c8e0aSMatthew Fettke #define CFG_LONGHELP		/* undef to save memory	*/
128*545c8e0aSMatthew Fettke 
129*545c8e0aSMatthew Fettke #if (CONFIG_CMD_KGDB)
130*545c8e0aSMatthew Fettke #	define CFG_CBSIZE	1024
131*545c8e0aSMatthew Fettke #else
132*545c8e0aSMatthew Fettke #	define CFG_CBSIZE	256
133*545c8e0aSMatthew Fettke #endif
134*545c8e0aSMatthew Fettke #define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
135*545c8e0aSMatthew Fettke #define CFG_MAXARGS		16
136*545c8e0aSMatthew Fettke #define CFG_BARGSIZE		CFG_CBSIZE
137*545c8e0aSMatthew Fettke 
138*545c8e0aSMatthew Fettke #define CFG_LOAD_ADDR		0x800000
139*545c8e0aSMatthew Fettke 
140*545c8e0aSMatthew Fettke #define CONFIG_BOOTDELAY	5
141*545c8e0aSMatthew Fettke #define CONFIG_BOOTCOMMAND	"bootm ffe40000"
142*545c8e0aSMatthew Fettke #define CFG_MEMTEST_START	0x400
143*545c8e0aSMatthew Fettke #define CFG_MEMTEST_END		0x380000
144*545c8e0aSMatthew Fettke 
145*545c8e0aSMatthew Fettke #define CFG_HZ			1000
146*545c8e0aSMatthew Fettke #define CFG_CLK			150000000
147*545c8e0aSMatthew Fettke 
148*545c8e0aSMatthew Fettke /*
149*545c8e0aSMatthew Fettke  * Low Level Configuration Settings
150*545c8e0aSMatthew Fettke  * (address mappings, register initial values, etc.)
151*545c8e0aSMatthew Fettke  * You should know what you are doing if you make changes here.
152*545c8e0aSMatthew Fettke  */
153*545c8e0aSMatthew Fettke 
154*545c8e0aSMatthew Fettke #define CFG_MBAR		0x40000000
155*545c8e0aSMatthew Fettke 
156*545c8e0aSMatthew Fettke /*-----------------------------------------------------------------------
157*545c8e0aSMatthew Fettke  * Definitions for initial stack pointer and data area (in DPRAM)
158*545c8e0aSMatthew Fettke  */
159*545c8e0aSMatthew Fettke #define CFG_INIT_RAM_ADDR	0x20000000
160*545c8e0aSMatthew Fettke #define CFG_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
161*545c8e0aSMatthew Fettke #define CFG_GBL_DATA_SIZE	1000	/* bytes reserved for initial data */
162*545c8e0aSMatthew Fettke #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
163*545c8e0aSMatthew Fettke #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
164*545c8e0aSMatthew Fettke 
165*545c8e0aSMatthew Fettke /*-----------------------------------------------------------------------
166*545c8e0aSMatthew Fettke  * Start addresses for the final memory configuration
167*545c8e0aSMatthew Fettke  * (Set up by the startup code)
168*545c8e0aSMatthew Fettke  * Please note that CFG_SDRAM_BASE _must_ start at 0
169*545c8e0aSMatthew Fettke  */
170*545c8e0aSMatthew Fettke #define CFG_SDRAM_BASE		0x00000000
171*545c8e0aSMatthew Fettke #define CFG_SDRAM_SIZE		16	/* SDRAM size in MB */
172*545c8e0aSMatthew Fettke #define CFG_FLASH_BASE		0xffe00000
173*545c8e0aSMatthew Fettke 
174*545c8e0aSMatthew Fettke #ifdef CONFIG_MONITOR_IS_IN_RAM
175*545c8e0aSMatthew Fettke #define CFG_MONITOR_BASE	0x20000
176*545c8e0aSMatthew Fettke #else
177*545c8e0aSMatthew Fettke #define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
178*545c8e0aSMatthew Fettke #endif
179*545c8e0aSMatthew Fettke 
180*545c8e0aSMatthew Fettke #define CFG_MONITOR_LEN		0x20000
181*545c8e0aSMatthew Fettke #define CFG_MALLOC_LEN		(256 << 10)
182*545c8e0aSMatthew Fettke #define CFG_BOOTPARAMS_LEN	64*1024
183*545c8e0aSMatthew Fettke 
184*545c8e0aSMatthew Fettke /*
185*545c8e0aSMatthew Fettke  * For booting Linux, the board info and command line data
186*545c8e0aSMatthew Fettke  * have to be in the first 8 MB of memory, since this is
187*545c8e0aSMatthew Fettke  * the maximum mapped by the Linux kernel during initialization ??
188*545c8e0aSMatthew Fettke  */
189*545c8e0aSMatthew Fettke #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial mmap for Linux */
190*545c8e0aSMatthew Fettke 
191*545c8e0aSMatthew Fettke /*-----------------------------------------------------------------------
192*545c8e0aSMatthew Fettke  * FLASH organization
193*545c8e0aSMatthew Fettke  */
194*545c8e0aSMatthew Fettke #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
195*545c8e0aSMatthew Fettke #define CFG_MAX_FLASH_SECT	11	/* max number of sectors on one chip */
196*545c8e0aSMatthew Fettke #define CFG_FLASH_ERASE_TOUT	1000
197*545c8e0aSMatthew Fettke 
198*545c8e0aSMatthew Fettke #define CFG_FLASH_CFI		1
199*545c8e0aSMatthew Fettke #define CFG_FLASH_CFI_DRIVER	1
200*545c8e0aSMatthew Fettke #define CFG_FLASH_SIZE		0x200000
201*545c8e0aSMatthew Fettke 
202*545c8e0aSMatthew Fettke /*-----------------------------------------------------------------------
203*545c8e0aSMatthew Fettke  * Cache Configuration
204*545c8e0aSMatthew Fettke  */
205*545c8e0aSMatthew Fettke #define CFG_CACHELINE_SIZE	16
206*545c8e0aSMatthew Fettke 
207*545c8e0aSMatthew Fettke /*-----------------------------------------------------------------------
208*545c8e0aSMatthew Fettke  * Memory bank definitions
209*545c8e0aSMatthew Fettke  */
210*545c8e0aSMatthew Fettke #define CFG_AR0_PRELIM		(CFG_FLASH_BASE >> 16)
211*545c8e0aSMatthew Fettke #define CFG_CR0_PRELIM		0x1980
212*545c8e0aSMatthew Fettke #define CFG_MR0_PRELIM		0x001F0001
213*545c8e0aSMatthew Fettke 
214*545c8e0aSMatthew Fettke #define CFG_AR1_PRELIM		0x3000
215*545c8e0aSMatthew Fettke #define CFG_CR1_PRELIM		0x1900
216*545c8e0aSMatthew Fettke #define CFG_MR1_PRELIM		0x00070001
217*545c8e0aSMatthew Fettke 
218*545c8e0aSMatthew Fettke /*-----------------------------------------------------------------------
219*545c8e0aSMatthew Fettke  * Port configuration
220*545c8e0aSMatthew Fettke  */
221*545c8e0aSMatthew Fettke #define CFG_FECI2C		0x0FA0
222*545c8e0aSMatthew Fettke 
223*545c8e0aSMatthew Fettke #endif	/* _M5275EVB_H */
224