1 /* 2 * Configuation settings for the Motorola MC5272C3 board. 3 * 4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M5272C3_H 14 #define _M5272C3_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 #define CONFIG_MCFTMR 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ 27 28 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 29 30 /* Configuration for environment 31 * Environment is embedded in u-boot in the second sector of the flash 32 */ 33 #ifndef CONFIG_MONITOR_IS_IN_RAM 34 #define CONFIG_ENV_OFFSET 0x4000 35 #define CONFIG_ENV_SECT_SIZE 0x2000 36 #else 37 #define CONFIG_ENV_ADDR 0xffe04000 38 #define CONFIG_ENV_SECT_SIZE 0x2000 39 #endif 40 41 #define LDS_BOARD_TEXT \ 42 . = DEFINED(env_offset) ? env_offset : .; \ 43 env/embedded.o(.text); 44 45 /* 46 * BOOTP options 47 */ 48 #define CONFIG_BOOTP_BOOTFILESIZE 49 #define CONFIG_BOOTP_BOOTPATH 50 #define CONFIG_BOOTP_GATEWAY 51 #define CONFIG_BOOTP_HOSTNAME 52 53 /* 54 * Command line configuration. 55 */ 56 57 #define CONFIG_MCFFEC 58 #ifdef CONFIG_MCFFEC 59 # define CONFIG_MII 1 60 # define CONFIG_MII_INIT 1 61 # define CONFIG_SYS_DISCOVER_PHY 62 # define CONFIG_SYS_RX_ETH_BUFFER 8 63 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 64 65 # define CONFIG_SYS_FEC0_PINMUX 0 66 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 67 # define MCFFEC_TOUT_LOOP 50000 68 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 69 # ifndef CONFIG_SYS_DISCOVER_PHY 70 # define FECDUPLEX FULL 71 # define FECSPEED _100BASET 72 # else 73 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 74 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 75 # endif 76 # endif /* CONFIG_SYS_DISCOVER_PHY */ 77 #endif 78 79 #ifdef CONFIG_MCFFEC 80 # define CONFIG_IPADDR 192.162.1.2 81 # define CONFIG_NETMASK 255.255.255.0 82 # define CONFIG_SERVERIP 192.162.1.1 83 # define CONFIG_GATEWAYIP 192.162.1.1 84 #endif /* CONFIG_MCFFEC */ 85 86 #define CONFIG_HOSTNAME M5272C3 87 #define CONFIG_EXTRA_ENV_SETTINGS \ 88 "netdev=eth0\0" \ 89 "loadaddr=10000\0" \ 90 "u-boot=u-boot.bin\0" \ 91 "load=tftp ${loadaddr) ${u-boot}\0" \ 92 "upd=run load; run prog\0" \ 93 "prog=prot off ffe00000 ffe3ffff;" \ 94 "era ffe00000 ffe3ffff;" \ 95 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 96 "save\0" \ 97 "" 98 99 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 100 101 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 102 #define CONFIG_SYS_LOAD_ADDR 0x20000 103 #define CONFIG_SYS_MEMTEST_START 0x400 104 #define CONFIG_SYS_MEMTEST_END 0x380000 105 #define CONFIG_SYS_CLK 66000000 106 107 /* 108 * Low Level Configuration Settings 109 * (address mappings, register initial values, etc.) 110 * You should know what you are doing if you make changes here. 111 */ 112 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 113 #define CONFIG_SYS_SCR 0x0003 114 #define CONFIG_SYS_SPR 0xffff 115 116 /*----------------------------------------------------------------------- 117 * Definitions for initial stack pointer and data area (in DPRAM) 118 */ 119 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 120 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 121 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 122 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 123 124 /*----------------------------------------------------------------------- 125 * Start addresses for the final memory configuration 126 * (Set up by the startup code) 127 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 128 */ 129 #define CONFIG_SYS_SDRAM_BASE 0x00000000 130 #define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ 131 #define CONFIG_SYS_FLASH_BASE 0xffe00000 132 133 #ifdef CONFIG_MONITOR_IS_IN_RAM 134 #define CONFIG_SYS_MONITOR_BASE 0x20000 135 #else 136 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 137 #endif 138 139 #define CONFIG_SYS_MONITOR_LEN 0x20000 140 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 141 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 142 143 /* 144 * For booting Linux, the board info and command line data 145 * have to be in the first 8 MB of memory, since this is 146 * the maximum mapped by the Linux kernel during initialization ?? 147 */ 148 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 149 150 /* 151 * FLASH organization 152 */ 153 #define CONFIG_SYS_FLASH_CFI 154 #ifdef CONFIG_SYS_FLASH_CFI 155 # define CONFIG_FLASH_CFI_DRIVER 1 156 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 157 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 158 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 159 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 160 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 161 #endif 162 163 /*----------------------------------------------------------------------- 164 * Cache Configuration 165 */ 166 #define CONFIG_SYS_CACHELINE_SIZE 16 167 168 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 169 CONFIG_SYS_INIT_RAM_SIZE - 8) 170 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 171 CONFIG_SYS_INIT_RAM_SIZE - 4) 172 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 173 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 174 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 175 CF_ACR_EN | CF_ACR_SM_ALL) 176 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 177 CF_CACR_DISD | CF_CACR_INVI | \ 178 CF_CACR_CEIB | CF_CACR_DCM | \ 179 CF_CACR_EUSP) 180 181 /*----------------------------------------------------------------------- 182 * Memory bank definitions 183 */ 184 #define CONFIG_SYS_BR0_PRELIM 0xFFE00201 185 #define CONFIG_SYS_OR0_PRELIM 0xFFE00014 186 #define CONFIG_SYS_BR1_PRELIM 0 187 #define CONFIG_SYS_OR1_PRELIM 0 188 #define CONFIG_SYS_BR2_PRELIM 0x30000001 189 #define CONFIG_SYS_OR2_PRELIM 0xFFF80000 190 #define CONFIG_SYS_BR3_PRELIM 0 191 #define CONFIG_SYS_OR3_PRELIM 0 192 #define CONFIG_SYS_BR4_PRELIM 0 193 #define CONFIG_SYS_OR4_PRELIM 0 194 #define CONFIG_SYS_BR5_PRELIM 0 195 #define CONFIG_SYS_OR5_PRELIM 0 196 #define CONFIG_SYS_BR6_PRELIM 0 197 #define CONFIG_SYS_OR6_PRELIM 0 198 #define CONFIG_SYS_BR7_PRELIM 0x00000701 199 #define CONFIG_SYS_OR7_PRELIM 0xFFC0007C 200 201 /*----------------------------------------------------------------------- 202 * Port configuration 203 */ 204 #define CONFIG_SYS_PACNT 0x00000000 205 #define CONFIG_SYS_PADDR 0x0000 206 #define CONFIG_SYS_PADAT 0x0000 207 #define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ 208 #define CONFIG_SYS_PBDDR 0x0000 209 #define CONFIG_SYS_PBDAT 0x0000 210 #define CONFIG_SYS_PDCNT 0x00000000 211 #endif /* _M5272C3_H */ 212