xref: /rk3399_rockchip-uboot/include/configs/M5272C3.h (revision bf9e3b38f77c2eac620263dd60437c6ec47a27bf)
1*bf9e3b38Swdenk /*
2*bf9e3b38Swdenk  * Configuation settings for the Motorola MC5272C3 board.
3*bf9e3b38Swdenk  *
4*bf9e3b38Swdenk  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5*bf9e3b38Swdenk  *
6*bf9e3b38Swdenk  * See file CREDITS for list of people who contributed to this
7*bf9e3b38Swdenk  * project.
8*bf9e3b38Swdenk  *
9*bf9e3b38Swdenk  * This program is free software; you can redistribute it and/or
10*bf9e3b38Swdenk  * modify it under the terms of the GNU General Public License as
11*bf9e3b38Swdenk  * published by the Free Software Foundation; either version 2 of
12*bf9e3b38Swdenk  * the License, or (at your option) any later version.
13*bf9e3b38Swdenk  *
14*bf9e3b38Swdenk  * This program is distributed in the hope that it will be useful,
15*bf9e3b38Swdenk  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16*bf9e3b38Swdenk  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
17*bf9e3b38Swdenk  * GNU General Public License for more details.
18*bf9e3b38Swdenk  *
19*bf9e3b38Swdenk  * You should have received a copy of the GNU General Public License
20*bf9e3b38Swdenk  * along with this program; if not, write to the Free Software
21*bf9e3b38Swdenk  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22*bf9e3b38Swdenk  * MA 02111-1307 USA
23*bf9e3b38Swdenk  */
244e5ca3ebSwdenk 
25*bf9e3b38Swdenk /*
26*bf9e3b38Swdenk  * board/config.h - configuration options, board specific
27*bf9e3b38Swdenk  */
284e5ca3ebSwdenk 
29*bf9e3b38Swdenk #ifndef _M5272C3_H
30*bf9e3b38Swdenk #define _M5272C3_H
31*bf9e3b38Swdenk 
32*bf9e3b38Swdenk /*
33*bf9e3b38Swdenk  * High Level Configuration Options
34*bf9e3b38Swdenk  * (easy to change)
35*bf9e3b38Swdenk  */
36*bf9e3b38Swdenk #define CONFIG_MCF52x2			/* define processor family */
37*bf9e3b38Swdenk #define CONFIG_M5272			/* define processor type */
384e5ca3ebSwdenk 
394e5ca3ebSwdenk #define FEC_ENET
404e5ca3ebSwdenk 
41*bf9e3b38Swdenk #define CONFIG_BAUDRATE		19200
42*bf9e3b38Swdenk #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
434e5ca3ebSwdenk 
44*bf9e3b38Swdenk #define CONFIG_WATCHDOG
45*bf9e3b38Swdenk #define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
46*bf9e3b38Swdenk 
47*bf9e3b38Swdenk #define CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
48*bf9e3b38Swdenk 
49*bf9e3b38Swdenk /* Configuration for environment
50*bf9e3b38Swdenk  * Environment is embedded in u-boot in the second sector of the flash
51*bf9e3b38Swdenk  */
52*bf9e3b38Swdenk #ifndef CONFIG_MONITOR_IS_IN_RAM
53*bf9e3b38Swdenk #define CFG_ENV_OFFSET		0x4000
54*bf9e3b38Swdenk #define CFG_ENV_SECT_SIZE	0x2000
55*bf9e3b38Swdenk #define CFG_ENV_IS_IN_FLASH	1
56*bf9e3b38Swdenk #define CFG_ENV_IS_EMBEDDED	1
57*bf9e3b38Swdenk #else
58*bf9e3b38Swdenk #define CFG_ENV_ADDR		0xffe04000
59*bf9e3b38Swdenk #define CFG_ENV_SECT_SIZE	0x2000
60*bf9e3b38Swdenk #define CFG_ENV_IS_IN_FLASH	1
61*bf9e3b38Swdenk #endif
62*bf9e3b38Swdenk 
63*bf9e3b38Swdenk #define CONFIG_COMMANDS	 ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) | \
64*bf9e3b38Swdenk 			   CFG_CMD_MII)
65*bf9e3b38Swdenk 
66*bf9e3b38Swdenk /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
67*bf9e3b38Swdenk #include <cmd_confdefs.h>
68*bf9e3b38Swdenk #define CONFIG_BOOTDELAY	5
69*bf9e3b38Swdenk 
70*bf9e3b38Swdenk #define CFG_PROMPT		"-> "
71*bf9e3b38Swdenk #define CFG_LONGHELP				/* undef to save memory		*/
72*bf9e3b38Swdenk 
73*bf9e3b38Swdenk #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
74*bf9e3b38Swdenk #define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
75*bf9e3b38Swdenk #else
76*bf9e3b38Swdenk #define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
77*bf9e3b38Swdenk #endif
78*bf9e3b38Swdenk #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
79*bf9e3b38Swdenk #define CFG_MAXARGS		16		/* max number of command args	*/
80*bf9e3b38Swdenk #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
81*bf9e3b38Swdenk 
82*bf9e3b38Swdenk #define CFG_LOAD_ADDR		0x20000
83*bf9e3b38Swdenk 
84*bf9e3b38Swdenk #define CFG_MEMTEST_START	0x400
85*bf9e3b38Swdenk #define CFG_MEMTEST_END		0x380000
86*bf9e3b38Swdenk 
87*bf9e3b38Swdenk #define CFG_HZ			1000
88*bf9e3b38Swdenk #define CFG_CLK			66000000
89*bf9e3b38Swdenk 
90*bf9e3b38Swdenk /*
91*bf9e3b38Swdenk  * Low Level Configuration Settings
92*bf9e3b38Swdenk  * (address mappings, register initial values, etc.)
93*bf9e3b38Swdenk  * You should know what you are doing if you make changes here.
94*bf9e3b38Swdenk  */
95*bf9e3b38Swdenk 
96*bf9e3b38Swdenk #define CFG_MBAR		0x10000000	/* Register Base Addrs */
97*bf9e3b38Swdenk 
98*bf9e3b38Swdenk #define CFG_SCR			0x0003;
99*bf9e3b38Swdenk #define CFG_SPR			0xffff;
100*bf9e3b38Swdenk 
101*bf9e3b38Swdenk #define CFG_DISCOVER_PHY
102*bf9e3b38Swdenk #define CFG_ENET_BD_BASE	0x380000
103*bf9e3b38Swdenk 
104*bf9e3b38Swdenk /*-----------------------------------------------------------------------
105*bf9e3b38Swdenk  * Definitions for initial stack pointer and data area (in DPRAM)
106*bf9e3b38Swdenk  */
107*bf9e3b38Swdenk #define CFG_INIT_RAM_ADDR	0x20000000
108*bf9e3b38Swdenk #define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
109*bf9e3b38Swdenk #define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
110*bf9e3b38Swdenk #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
111*bf9e3b38Swdenk #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
112*bf9e3b38Swdenk 
113*bf9e3b38Swdenk /*-----------------------------------------------------------------------
114*bf9e3b38Swdenk  * Start addresses for the final memory configuration
115*bf9e3b38Swdenk  * (Set up by the startup code)
116*bf9e3b38Swdenk  * Please note that CFG_SDRAM_BASE _must_ start at 0
117*bf9e3b38Swdenk  */
118*bf9e3b38Swdenk #define CFG_SDRAM_BASE		0x00000000
119*bf9e3b38Swdenk #define CFG_SDRAM_SIZE		4		/* SDRAM size in MB */
120*bf9e3b38Swdenk #define CFG_FLASH_BASE		0xffe00000
121*bf9e3b38Swdenk 
122*bf9e3b38Swdenk #ifdef	CONFIG_MONITOR_IS_IN_RAM
123*bf9e3b38Swdenk #define CFG_MONITOR_BASE	0x20000
124*bf9e3b38Swdenk #else
125*bf9e3b38Swdenk #define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
126*bf9e3b38Swdenk #endif
127*bf9e3b38Swdenk 
128*bf9e3b38Swdenk #define CFG_MONITOR_LEN		0x20000
129*bf9e3b38Swdenk #define CFG_MALLOC_LEN		(256 << 10)
130*bf9e3b38Swdenk #define CFG_BOOTPARAMS_LEN	64*1024
131*bf9e3b38Swdenk 
132*bf9e3b38Swdenk /*
133*bf9e3b38Swdenk  * For booting Linux, the board info and command line data
134*bf9e3b38Swdenk  * have to be in the first 8 MB of memory, since this is
135*bf9e3b38Swdenk  * the maximum mapped by the Linux kernel during initialization ??
136*bf9e3b38Swdenk  */
137*bf9e3b38Swdenk #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
138*bf9e3b38Swdenk 
139*bf9e3b38Swdenk /*-----------------------------------------------------------------------
140*bf9e3b38Swdenk  * FLASH organization
141*bf9e3b38Swdenk  */
142*bf9e3b38Swdenk #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
143*bf9e3b38Swdenk #define CFG_MAX_FLASH_SECT	11	/* max number of sectors on one chip	*/
144*bf9e3b38Swdenk #define CFG_FLASH_ERASE_TOUT	1000
145*bf9e3b38Swdenk 
146*bf9e3b38Swdenk /*-----------------------------------------------------------------------
147*bf9e3b38Swdenk  * Cache Configuration
148*bf9e3b38Swdenk  */
149*bf9e3b38Swdenk #define CFG_CACHELINE_SIZE	16
150*bf9e3b38Swdenk 
151*bf9e3b38Swdenk /*-----------------------------------------------------------------------
152*bf9e3b38Swdenk  * Memory bank definitions
153*bf9e3b38Swdenk  */
154*bf9e3b38Swdenk #define CFG_BR0_PRELIM		0xFFE00201
155*bf9e3b38Swdenk #define CFG_OR0_PRELIM		0xFFE00014
156*bf9e3b38Swdenk 
157*bf9e3b38Swdenk #define CFG_BR1_PRELIM		0
158*bf9e3b38Swdenk #define CFG_OR1_PRELIM		0
159*bf9e3b38Swdenk 
160*bf9e3b38Swdenk #define CFG_BR2_PRELIM		0x30000001
161*bf9e3b38Swdenk #define CFG_OR2_PRELIM		0xFFF80000
162*bf9e3b38Swdenk 
163*bf9e3b38Swdenk #define CFG_BR3_PRELIM		0
164*bf9e3b38Swdenk #define CFG_OR3_PRELIM		0
165*bf9e3b38Swdenk 
166*bf9e3b38Swdenk #define CFG_BR4_PRELIM		0
167*bf9e3b38Swdenk #define CFG_OR4_PRELIM		0
168*bf9e3b38Swdenk 
169*bf9e3b38Swdenk #define CFG_BR5_PRELIM		0
170*bf9e3b38Swdenk #define CFG_OR5_PRELIM		0
171*bf9e3b38Swdenk 
172*bf9e3b38Swdenk #define CFG_BR6_PRELIM		0
173*bf9e3b38Swdenk #define CFG_OR6_PRELIM		0
174*bf9e3b38Swdenk 
175*bf9e3b38Swdenk #define CFG_BR7_PRELIM		0x00000701
176*bf9e3b38Swdenk #define CFG_OR7_PRELIM		0xFFC0007C
177*bf9e3b38Swdenk 
178*bf9e3b38Swdenk /*-----------------------------------------------------------------------
179*bf9e3b38Swdenk  * Port configuration
180*bf9e3b38Swdenk  */
181*bf9e3b38Swdenk #define CFG_PACNT		0x00000000
182*bf9e3b38Swdenk #define CFG_PADDR		0x0000
183*bf9e3b38Swdenk #define CFG_PADAT		0x0000
184*bf9e3b38Swdenk #define CFG_PBCNT		0x55554155		/* Ethernet/UART configuration */
185*bf9e3b38Swdenk #define CFG_PBDDR		0x0000
186*bf9e3b38Swdenk #define CFG_PBDAT		0x0000
187*bf9e3b38Swdenk #define CFG_PDCNT		0x00000000
188*bf9e3b38Swdenk 
189*bf9e3b38Swdenk #endif	/* _M5272C3_H */
190