1 /* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * Hayden Fraser (Hayden.Fraser@freescale.com) 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _M5253EVBE_H 9 #define _M5253EVBE_H 10 11 #define CONFIG_M5253EVBE /* define board type */ 12 13 #define CONFIG_MCFTMR 14 15 #define CONFIG_MCFUART 16 #define CONFIG_SYS_UART_PORT (0) 17 #define CONFIG_BAUDRATE 115200 18 19 #undef CONFIG_WATCHDOG /* disable watchdog */ 20 21 #define CONFIG_BOOTDELAY 5 22 23 /* Configuration for environment 24 * Environment is embedded in u-boot in the second sector of the flash 25 */ 26 #ifndef CONFIG_MONITOR_IS_IN_RAM 27 #define CONFIG_ENV_OFFSET 0x4000 28 #define CONFIG_ENV_SECT_SIZE 0x2000 29 #define CONFIG_ENV_IS_IN_FLASH 1 30 #else 31 #define CONFIG_ENV_ADDR 0xffe04000 32 #define CONFIG_ENV_SECT_SIZE 0x2000 33 #define CONFIG_ENV_IS_IN_FLASH 1 34 #endif 35 36 /* 37 * BOOTP options 38 */ 39 #undef CONFIG_BOOTP_BOOTFILESIZE 40 #undef CONFIG_BOOTP_BOOTPATH 41 #undef CONFIG_BOOTP_GATEWAY 42 #undef CONFIG_BOOTP_HOSTNAME 43 44 /* 45 * Command line configuration. 46 */ 47 #include <config_cmd_default.h> 48 #define CONFIG_CMD_CACHE 49 #undef CONFIG_CMD_NET 50 #define CONFIG_CMD_LOADB 51 #define CONFIG_CMD_LOADS 52 #define CONFIG_CMD_EXT2 53 #define CONFIG_CMD_FAT 54 #define CONFIG_CMD_IDE 55 #define CONFIG_CMD_MEMORY 56 #define CONFIG_CMD_MISC 57 58 /* ATA */ 59 #define CONFIG_DOS_PARTITION 60 #define CONFIG_MAC_PARTITION 61 #define CONFIG_IDE_RESET 1 62 #define CONFIG_IDE_PREINIT 1 63 #define CONFIG_ATAPI 64 #undef CONFIG_LBA48 65 66 #define CONFIG_SYS_IDE_MAXBUS 1 67 #define CONFIG_SYS_IDE_MAXDEVICE 2 68 69 #define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 70 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 71 72 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 73 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 74 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 75 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 76 77 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 78 79 #if defined(CONFIG_CMD_KGDB) 80 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 81 #else 82 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 83 #endif 84 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 85 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 86 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 87 88 #define CONFIG_SYS_LOAD_ADDR 0x00100000 89 90 #define CONFIG_SYS_MEMTEST_START 0x400 91 #define CONFIG_SYS_MEMTEST_END 0x380000 92 93 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 94 #define CONFIG_SYS_FAST_CLK 95 #ifdef CONFIG_SYS_FAST_CLK 96 # define CONFIG_SYS_PLLCR 0x1243E054 97 # define CONFIG_SYS_CLK 140000000 98 #else 99 # define CONFIG_SYS_PLLCR 0x135a4140 100 # define CONFIG_SYS_CLK 70000000 101 #endif 102 103 /* 104 * Low Level Configuration Settings 105 * (address mappings, register initial values, etc.) 106 * You should know what you are doing if you make changes here. 107 */ 108 109 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 110 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 111 112 /* 113 * Definitions for initial stack pointer and data area (in DPRAM) 114 */ 115 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 116 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 117 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 118 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 119 120 /* 121 * Start addresses for the final memory configuration 122 * (Set up by the startup code) 123 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 124 */ 125 #define CONFIG_SYS_SDRAM_BASE 0x00000000 126 #define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */ 127 128 #ifdef CONFIG_MONITOR_IS_IN_RAM 129 #define CONFIG_SYS_MONITOR_BASE 0x20000 130 #else 131 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 132 #endif 133 134 #define CONFIG_SYS_MONITOR_LEN 0x40000 135 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 136 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 137 138 /* 139 * For booting Linux, the board info and command line data 140 * have to be in the first 8 MB of memory, since this is 141 * the maximum mapped by the Linux kernel during initialization ?? 142 */ 143 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 144 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 145 146 /* FLASH organization */ 147 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 148 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 149 #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ 150 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 151 152 #define CONFIG_SYS_FLASH_CFI 1 153 #define CONFIG_FLASH_CFI_DRIVER 1 154 #define CONFIG_SYS_FLASH_SIZE 0x200000 155 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 156 157 /* Cache Configuration */ 158 #define CONFIG_SYS_CACHELINE_SIZE 16 159 160 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 161 CONFIG_SYS_INIT_RAM_SIZE - 8) 162 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 163 CONFIG_SYS_INIT_RAM_SIZE - 4) 164 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 165 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 166 CF_ADDRMASK(2) | \ 167 CF_ACR_EN | CF_ACR_SM_ALL) 168 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 169 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 170 CF_ACR_EN | CF_ACR_SM_ALL) 171 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 172 CF_CACR_DBWE) 173 174 /* Port configuration */ 175 #define CONFIG_SYS_FECI2C 0xF0 176 177 #define CONFIG_SYS_CS0_BASE 0xFFE00000 178 #define CONFIG_SYS_CS0_MASK 0x001F0021 179 #define CONFIG_SYS_CS0_CTRL 0x00001D80 180 181 /*----------------------------------------------------------------------- 182 * Port configuration 183 */ 184 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 185 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 186 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 187 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 188 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 189 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 190 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 191 192 #endif /* _M5253EVB_H */ 193