1 /* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * Hayden Fraser (Hayden.Fraser@freescale.com) 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _M5253EVBE_H 9 #define _M5253EVBE_H 10 11 #define CONFIG_M5253EVBE /* define board type */ 12 13 #define CONFIG_MCFTMR 14 15 #define CONFIG_MCFUART 16 #define CONFIG_SYS_UART_PORT (0) 17 #define CONFIG_BAUDRATE 115200 18 19 #undef CONFIG_WATCHDOG /* disable watchdog */ 20 21 22 /* Configuration for environment 23 * Environment is embedded in u-boot in the second sector of the flash 24 */ 25 #ifndef CONFIG_MONITOR_IS_IN_RAM 26 #define CONFIG_ENV_OFFSET 0x4000 27 #define CONFIG_ENV_SECT_SIZE 0x2000 28 #define CONFIG_ENV_IS_IN_FLASH 1 29 #else 30 #define CONFIG_ENV_ADDR 0xffe04000 31 #define CONFIG_ENV_SECT_SIZE 0x2000 32 #define CONFIG_ENV_IS_IN_FLASH 1 33 #endif 34 35 #define LDS_BOARD_TEXT \ 36 . = DEFINED(env_offset) ? env_offset : .; \ 37 common/env_embedded.o (.text) 38 39 /* 40 * BOOTP options 41 */ 42 #undef CONFIG_BOOTP_BOOTFILESIZE 43 #undef CONFIG_BOOTP_BOOTPATH 44 #undef CONFIG_BOOTP_GATEWAY 45 #undef CONFIG_BOOTP_HOSTNAME 46 47 /* 48 * Command line configuration. 49 */ 50 #define CONFIG_CMD_IDE 51 52 /* ATA */ 53 #define CONFIG_IDE_RESET 1 54 #define CONFIG_IDE_PREINIT 1 55 #define CONFIG_ATAPI 56 #undef CONFIG_LBA48 57 58 #define CONFIG_SYS_IDE_MAXBUS 1 59 #define CONFIG_SYS_IDE_MAXDEVICE 2 60 61 #define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 62 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 63 64 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 65 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 66 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 67 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 68 69 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 70 71 #if defined(CONFIG_CMD_KGDB) 72 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 73 #else 74 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 75 #endif 76 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 77 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 78 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 79 80 #define CONFIG_SYS_LOAD_ADDR 0x00100000 81 82 #define CONFIG_SYS_MEMTEST_START 0x400 83 #define CONFIG_SYS_MEMTEST_END 0x380000 84 85 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 86 #define CONFIG_SYS_FAST_CLK 87 #ifdef CONFIG_SYS_FAST_CLK 88 # define CONFIG_SYS_PLLCR 0x1243E054 89 # define CONFIG_SYS_CLK 140000000 90 #else 91 # define CONFIG_SYS_PLLCR 0x135a4140 92 # define CONFIG_SYS_CLK 70000000 93 #endif 94 95 /* 96 * Low Level Configuration Settings 97 * (address mappings, register initial values, etc.) 98 * You should know what you are doing if you make changes here. 99 */ 100 101 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 102 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 103 104 /* 105 * Definitions for initial stack pointer and data area (in DPRAM) 106 */ 107 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 108 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 109 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 110 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 111 112 /* 113 * Start addresses for the final memory configuration 114 * (Set up by the startup code) 115 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 116 */ 117 #define CONFIG_SYS_SDRAM_BASE 0x00000000 118 #define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */ 119 120 #ifdef CONFIG_MONITOR_IS_IN_RAM 121 #define CONFIG_SYS_MONITOR_BASE 0x20000 122 #else 123 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 124 #endif 125 126 #define CONFIG_SYS_MONITOR_LEN 0x40000 127 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 128 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 129 130 /* 131 * For booting Linux, the board info and command line data 132 * have to be in the first 8 MB of memory, since this is 133 * the maximum mapped by the Linux kernel during initialization ?? 134 */ 135 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 136 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 137 138 /* FLASH organization */ 139 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 140 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 141 #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ 142 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 143 144 #define CONFIG_SYS_FLASH_CFI 1 145 #define CONFIG_FLASH_CFI_DRIVER 1 146 #define CONFIG_SYS_FLASH_SIZE 0x200000 147 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 148 149 /* Cache Configuration */ 150 #define CONFIG_SYS_CACHELINE_SIZE 16 151 152 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 153 CONFIG_SYS_INIT_RAM_SIZE - 8) 154 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 155 CONFIG_SYS_INIT_RAM_SIZE - 4) 156 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 157 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 158 CF_ADDRMASK(2) | \ 159 CF_ACR_EN | CF_ACR_SM_ALL) 160 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 161 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 162 CF_ACR_EN | CF_ACR_SM_ALL) 163 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 164 CF_CACR_DBWE) 165 166 /* Port configuration */ 167 #define CONFIG_SYS_FECI2C 0xF0 168 169 #define CONFIG_SYS_CS0_BASE 0xFFE00000 170 #define CONFIG_SYS_CS0_MASK 0x001F0021 171 #define CONFIG_SYS_CS0_CTRL 0x00001D80 172 173 /*----------------------------------------------------------------------- 174 * Port configuration 175 */ 176 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 177 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 178 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 179 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 180 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 181 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 182 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 183 184 #endif /* _M5253EVB_H */ 185