1 /* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * Hayden Fraser (Hayden.Fraser@freescale.com) 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _M5253EVBE_H 9 #define _M5253EVBE_H 10 11 #define CONFIG_M5253EVBE /* define board type */ 12 13 #define CONFIG_MCFTMR 14 15 #define CONFIG_MCFUART 16 #define CONFIG_SYS_UART_PORT (0) 17 #define CONFIG_BAUDRATE 115200 18 19 #undef CONFIG_WATCHDOG /* disable watchdog */ 20 21 #define CONFIG_BOOTDELAY 5 22 23 /* Configuration for environment 24 * Environment is embedded in u-boot in the second sector of the flash 25 */ 26 #ifndef CONFIG_MONITOR_IS_IN_RAM 27 #define CONFIG_ENV_OFFSET 0x4000 28 #define CONFIG_ENV_SECT_SIZE 0x2000 29 #define CONFIG_ENV_IS_IN_FLASH 1 30 #else 31 #define CONFIG_ENV_ADDR 0xffe04000 32 #define CONFIG_ENV_SECT_SIZE 0x2000 33 #define CONFIG_ENV_IS_IN_FLASH 1 34 #endif 35 36 #define LDS_BOARD_TEXT \ 37 . = DEFINED(env_offset) ? env_offset : .; \ 38 common/env_embedded.o (.text) 39 40 /* 41 * BOOTP options 42 */ 43 #undef CONFIG_BOOTP_BOOTFILESIZE 44 #undef CONFIG_BOOTP_BOOTPATH 45 #undef CONFIG_BOOTP_GATEWAY 46 #undef CONFIG_BOOTP_HOSTNAME 47 48 /* 49 * Command line configuration. 50 */ 51 #define CONFIG_CMD_IDE 52 53 /* ATA */ 54 #define CONFIG_DOS_PARTITION 55 #define CONFIG_MAC_PARTITION 56 #define CONFIG_IDE_RESET 1 57 #define CONFIG_IDE_PREINIT 1 58 #define CONFIG_ATAPI 59 #undef CONFIG_LBA48 60 61 #define CONFIG_SYS_IDE_MAXBUS 1 62 #define CONFIG_SYS_IDE_MAXDEVICE 2 63 64 #define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 65 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 66 67 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 68 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 69 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 70 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 71 72 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 73 74 #if defined(CONFIG_CMD_KGDB) 75 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 76 #else 77 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 78 #endif 79 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 80 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 81 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 82 83 #define CONFIG_SYS_LOAD_ADDR 0x00100000 84 85 #define CONFIG_SYS_MEMTEST_START 0x400 86 #define CONFIG_SYS_MEMTEST_END 0x380000 87 88 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 89 #define CONFIG_SYS_FAST_CLK 90 #ifdef CONFIG_SYS_FAST_CLK 91 # define CONFIG_SYS_PLLCR 0x1243E054 92 # define CONFIG_SYS_CLK 140000000 93 #else 94 # define CONFIG_SYS_PLLCR 0x135a4140 95 # define CONFIG_SYS_CLK 70000000 96 #endif 97 98 /* 99 * Low Level Configuration Settings 100 * (address mappings, register initial values, etc.) 101 * You should know what you are doing if you make changes here. 102 */ 103 104 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 105 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 106 107 /* 108 * Definitions for initial stack pointer and data area (in DPRAM) 109 */ 110 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 111 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 112 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 113 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 114 115 /* 116 * Start addresses for the final memory configuration 117 * (Set up by the startup code) 118 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 119 */ 120 #define CONFIG_SYS_SDRAM_BASE 0x00000000 121 #define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */ 122 123 #ifdef CONFIG_MONITOR_IS_IN_RAM 124 #define CONFIG_SYS_MONITOR_BASE 0x20000 125 #else 126 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 127 #endif 128 129 #define CONFIG_SYS_MONITOR_LEN 0x40000 130 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 131 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 132 133 /* 134 * For booting Linux, the board info and command line data 135 * have to be in the first 8 MB of memory, since this is 136 * the maximum mapped by the Linux kernel during initialization ?? 137 */ 138 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 139 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 140 141 /* FLASH organization */ 142 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 143 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 144 #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ 145 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 146 147 #define CONFIG_SYS_FLASH_CFI 1 148 #define CONFIG_FLASH_CFI_DRIVER 1 149 #define CONFIG_SYS_FLASH_SIZE 0x200000 150 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 151 152 /* Cache Configuration */ 153 #define CONFIG_SYS_CACHELINE_SIZE 16 154 155 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 156 CONFIG_SYS_INIT_RAM_SIZE - 8) 157 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 158 CONFIG_SYS_INIT_RAM_SIZE - 4) 159 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 160 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 161 CF_ADDRMASK(2) | \ 162 CF_ACR_EN | CF_ACR_SM_ALL) 163 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 164 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 165 CF_ACR_EN | CF_ACR_SM_ALL) 166 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 167 CF_CACR_DBWE) 168 169 /* Port configuration */ 170 #define CONFIG_SYS_FECI2C 0xF0 171 172 #define CONFIG_SYS_CS0_BASE 0xFFE00000 173 #define CONFIG_SYS_CS0_MASK 0x001F0021 174 #define CONFIG_SYS_CS0_CTRL 0x00001D80 175 176 /*----------------------------------------------------------------------- 177 * Port configuration 178 */ 179 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 180 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 181 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 182 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 183 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 184 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 185 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 186 187 #endif /* _M5253EVB_H */ 188