1 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 2 * Hayden Fraser (Hayden.Fraser@freescale.com) 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _M5253DEMO_H 8 #define _M5253DEMO_H 9 10 #define CONFIG_M5253DEMO /* define board type */ 11 12 #define CONFIG_MCFTMR 13 14 #define CONFIG_MCFUART 15 #define CONFIG_SYS_UART_PORT (0) 16 #define CONFIG_BAUDRATE 115200 17 18 #undef CONFIG_WATCHDOG /* disable watchdog */ 19 20 21 /* Configuration for environment 22 * Environment is embedded in u-boot in the second sector of the flash 23 */ 24 #ifdef CONFIG_MONITOR_IS_IN_RAM 25 # define CONFIG_ENV_OFFSET 0x4000 26 # define CONFIG_ENV_SECT_SIZE 0x1000 27 # define CONFIG_ENV_IS_IN_FLASH 1 28 #else 29 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) 30 # define CONFIG_ENV_SECT_SIZE 0x1000 31 # define CONFIG_ENV_IS_IN_FLASH 1 32 #endif 33 34 #define LDS_BOARD_TEXT \ 35 . = DEFINED(env_offset) ? env_offset : .; \ 36 common/env_embedded.o (.text*); 37 38 /* 39 * Command line configuration. 40 */ 41 #define CONFIG_CMD_IDE 42 43 #ifdef CONFIG_CMD_IDE 44 /* ATA */ 45 # define CONFIG_DOS_PARTITION 46 # define CONFIG_IDE_RESET 1 47 # define CONFIG_IDE_PREINIT 1 48 # define CONFIG_ATAPI 49 # undef CONFIG_LBA48 50 51 # define CONFIG_SYS_IDE_MAXBUS 1 52 # define CONFIG_SYS_IDE_MAXDEVICE 2 53 54 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 55 # define CONFIG_SYS_ATA_IDE0_OFFSET 0 56 57 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 58 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 59 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 60 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 61 #endif 62 63 #define CONFIG_DRIVER_DM9000 64 #ifdef CONFIG_DRIVER_DM9000 65 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) 66 # define DM9000_IO CONFIG_DM9000_BASE 67 # define DM9000_DATA (CONFIG_DM9000_BASE + 4) 68 # undef CONFIG_DM9000_DEBUG 69 # define CONFIG_DM9000_BYTE_SWAPPED 70 71 # define CONFIG_OVERWRITE_ETHADDR_ONCE 72 73 # define CONFIG_EXTRA_ENV_SETTINGS \ 74 "netdev=eth0\0" \ 75 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 76 "loadaddr=10000\0" \ 77 "u-boot=u-boot.bin\0" \ 78 "load=tftp ${loadaddr) ${u-boot}\0" \ 79 "upd=run load; run prog\0" \ 80 "prog=prot off 0xff800000 0xff82ffff;" \ 81 "era 0xff800000 0xff82ffff;" \ 82 "cp.b ${loadaddr} 0xff800000 ${filesize};" \ 83 "save\0" \ 84 "" 85 #endif 86 87 #define CONFIG_HOSTNAME M5253DEMO 88 89 /* I2C */ 90 #define CONFIG_SYS_I2C 91 #define CONFIG_SYS_I2C_FSL 92 #define CONFIG_SYS_FSL_I2C_SPEED 80000 93 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 94 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 95 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 96 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) 97 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) 98 #define CONFIG_SYS_I2C_PINMUX_SET (0) 99 100 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 101 102 #if defined(CONFIG_CMD_KGDB) 103 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 104 #else 105 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 106 #endif 107 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 108 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 109 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 110 111 #define CONFIG_SYS_LOAD_ADDR 0x00100000 112 113 #define CONFIG_SYS_MEMTEST_START 0x400 114 #define CONFIG_SYS_MEMTEST_END 0x380000 115 116 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 117 #define CONFIG_SYS_FAST_CLK 118 #ifdef CONFIG_SYS_FAST_CLK 119 # define CONFIG_SYS_PLLCR 0x1243E054 120 # define CONFIG_SYS_CLK 140000000 121 #else 122 # define CONFIG_SYS_PLLCR 0x135a4140 123 # define CONFIG_SYS_CLK 70000000 124 #endif 125 126 /* 127 * Low Level Configuration Settings 128 * (address mappings, register initial values, etc.) 129 * You should know what you are doing if you make changes here. 130 */ 131 132 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 133 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 134 135 /* 136 * Definitions for initial stack pointer and data area (in DPRAM) 137 */ 138 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 139 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 140 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 141 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 142 143 /* 144 * Start addresses for the final memory configuration 145 * (Set up by the startup code) 146 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 147 */ 148 #define CONFIG_SYS_SDRAM_BASE 0x00000000 149 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 150 151 #ifdef CONFIG_MONITOR_IS_IN_RAM 152 # define CONFIG_SYS_MONITOR_BASE 0x20000 153 #else 154 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 155 #endif 156 157 #define CONFIG_SYS_MONITOR_LEN 0x40000 158 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 159 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 160 161 /* 162 * For booting Linux, the board info and command line data 163 * have to be in the first 8 MB of memory, since this is 164 * the maximum mapped by the Linux kernel during initialization ?? 165 */ 166 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 167 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 168 169 /* FLASH organization */ 170 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 171 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 172 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ 173 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 174 175 #define FLASH_SST6401B 0x200 176 #define SST_ID_xF6401B 0x236D236D 177 178 #undef CONFIG_SYS_FLASH_CFI 179 #ifdef CONFIG_SYS_FLASH_CFI 180 /* 181 * Unable to use CFI driver, due to incompatible sector erase command by SST. 182 * Amd/Atmel use 0x30 for sector erase, SST use 0x50. 183 * 0x30 is block erase in SST 184 */ 185 # define CONFIG_FLASH_CFI_DRIVER 1 186 # define CONFIG_SYS_FLASH_SIZE 0x800000 187 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 188 # define CONFIG_FLASH_CFI_LEGACY 189 #else 190 # define CONFIG_SYS_SST_SECT 2048 191 # define CONFIG_SYS_SST_SECTSZ 0x1000 192 # define CONFIG_SYS_FLASH_WRITE_TOUT 500 193 #endif 194 195 /* Cache Configuration */ 196 #define CONFIG_SYS_CACHELINE_SIZE 16 197 198 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 199 CONFIG_SYS_INIT_RAM_SIZE - 8) 200 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 201 CONFIG_SYS_INIT_RAM_SIZE - 4) 202 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 203 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 204 CF_ADDRMASK(8) | \ 205 CF_ACR_EN | CF_ACR_SM_ALL) 206 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 207 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 208 CF_ACR_EN | CF_ACR_SM_ALL) 209 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 210 CF_CACR_DBWE) 211 212 /* Port configuration */ 213 #define CONFIG_SYS_FECI2C 0xF0 214 215 #define CONFIG_SYS_CS0_BASE 0xFF800000 216 #define CONFIG_SYS_CS0_MASK 0x007F0021 217 #define CONFIG_SYS_CS0_CTRL 0x00001D80 218 219 #define CONFIG_SYS_CS1_BASE 0xE0000000 220 #define CONFIG_SYS_CS1_MASK 0x00000001 221 #define CONFIG_SYS_CS1_CTRL 0x00003DD8 222 223 /*----------------------------------------------------------------------- 224 * Port configuration 225 */ 226 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 227 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 228 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 229 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 230 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 231 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 232 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 233 234 #endif /* _M5253DEMO_H */ 235