1 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 2 * Hayden Fraser (Hayden.Fraser@freescale.com) 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _M5253DEMO_H 8 #define _M5253DEMO_H 9 10 #define CONFIG_M5253DEMO /* define board type */ 11 12 #define CONFIG_MCFTMR 13 14 #define CONFIG_MCFUART 15 #define CONFIG_SYS_UART_PORT (0) 16 #define CONFIG_BAUDRATE 115200 17 18 #undef CONFIG_WATCHDOG /* disable watchdog */ 19 20 #define CONFIG_BOOTDELAY 5 21 22 /* Configuration for environment 23 * Environment is embedded in u-boot in the second sector of the flash 24 */ 25 #ifdef CONFIG_MONITOR_IS_IN_RAM 26 # define CONFIG_ENV_OFFSET 0x4000 27 # define CONFIG_ENV_SECT_SIZE 0x1000 28 # define CONFIG_ENV_IS_IN_FLASH 1 29 #else 30 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) 31 # define CONFIG_ENV_SECT_SIZE 0x1000 32 # define CONFIG_ENV_IS_IN_FLASH 1 33 #endif 34 35 #define LDS_BOARD_TEXT \ 36 . = DEFINED(env_offset) ? env_offset : .; \ 37 common/env_embedded.o (.text*); 38 39 /* 40 * Command line configuration. 41 */ 42 #define CONFIG_CMD_CACHE 43 #define CONFIG_CMD_EXT2 44 #define CONFIG_CMD_FAT 45 #define CONFIG_CMD_IDE 46 47 #ifdef CONFIG_CMD_IDE 48 /* ATA */ 49 # define CONFIG_DOS_PARTITION 50 # define CONFIG_MAC_PARTITION 51 # define CONFIG_IDE_RESET 1 52 # define CONFIG_IDE_PREINIT 1 53 # define CONFIG_ATAPI 54 # undef CONFIG_LBA48 55 56 # define CONFIG_SYS_IDE_MAXBUS 1 57 # define CONFIG_SYS_IDE_MAXDEVICE 2 58 59 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 60 # define CONFIG_SYS_ATA_IDE0_OFFSET 0 61 62 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 63 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 64 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 65 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 66 #endif 67 68 #define CONFIG_DRIVER_DM9000 69 #ifdef CONFIG_DRIVER_DM9000 70 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) 71 # define DM9000_IO CONFIG_DM9000_BASE 72 # define DM9000_DATA (CONFIG_DM9000_BASE + 4) 73 # undef CONFIG_DM9000_DEBUG 74 # define CONFIG_DM9000_BYTE_SWAPPED 75 76 # define CONFIG_OVERWRITE_ETHADDR_ONCE 77 78 # define CONFIG_EXTRA_ENV_SETTINGS \ 79 "netdev=eth0\0" \ 80 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 81 "loadaddr=10000\0" \ 82 "u-boot=u-boot.bin\0" \ 83 "load=tftp ${loadaddr) ${u-boot}\0" \ 84 "upd=run load; run prog\0" \ 85 "prog=prot off 0xff800000 0xff82ffff;" \ 86 "era 0xff800000 0xff82ffff;" \ 87 "cp.b ${loadaddr} 0xff800000 ${filesize};" \ 88 "save\0" \ 89 "" 90 #endif 91 92 #define CONFIG_HOSTNAME M5253DEMO 93 94 /* I2C */ 95 #define CONFIG_SYS_I2C 96 #define CONFIG_SYS_I2C_FSL 97 #define CONFIG_SYS_FSL_I2C_SPEED 80000 98 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 99 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 100 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 101 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) 102 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) 103 #define CONFIG_SYS_I2C_PINMUX_SET (0) 104 105 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 106 107 #if defined(CONFIG_CMD_KGDB) 108 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 109 #else 110 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 111 #endif 112 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 113 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 114 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 115 116 #define CONFIG_SYS_LOAD_ADDR 0x00100000 117 118 #define CONFIG_SYS_MEMTEST_START 0x400 119 #define CONFIG_SYS_MEMTEST_END 0x380000 120 121 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 122 #define CONFIG_SYS_FAST_CLK 123 #ifdef CONFIG_SYS_FAST_CLK 124 # define CONFIG_SYS_PLLCR 0x1243E054 125 # define CONFIG_SYS_CLK 140000000 126 #else 127 # define CONFIG_SYS_PLLCR 0x135a4140 128 # define CONFIG_SYS_CLK 70000000 129 #endif 130 131 /* 132 * Low Level Configuration Settings 133 * (address mappings, register initial values, etc.) 134 * You should know what you are doing if you make changes here. 135 */ 136 137 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 138 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 139 140 /* 141 * Definitions for initial stack pointer and data area (in DPRAM) 142 */ 143 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 144 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 145 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 146 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 147 148 /* 149 * Start addresses for the final memory configuration 150 * (Set up by the startup code) 151 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 152 */ 153 #define CONFIG_SYS_SDRAM_BASE 0x00000000 154 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 155 156 #ifdef CONFIG_MONITOR_IS_IN_RAM 157 # define CONFIG_SYS_MONITOR_BASE 0x20000 158 #else 159 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 160 #endif 161 162 #define CONFIG_SYS_MONITOR_LEN 0x40000 163 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 164 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 165 166 /* 167 * For booting Linux, the board info and command line data 168 * have to be in the first 8 MB of memory, since this is 169 * the maximum mapped by the Linux kernel during initialization ?? 170 */ 171 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 172 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 173 174 /* FLASH organization */ 175 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 176 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 177 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ 178 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 179 180 #define FLASH_SST6401B 0x200 181 #define SST_ID_xF6401B 0x236D236D 182 183 #undef CONFIG_SYS_FLASH_CFI 184 #ifdef CONFIG_SYS_FLASH_CFI 185 /* 186 * Unable to use CFI driver, due to incompatible sector erase command by SST. 187 * Amd/Atmel use 0x30 for sector erase, SST use 0x50. 188 * 0x30 is block erase in SST 189 */ 190 # define CONFIG_FLASH_CFI_DRIVER 1 191 # define CONFIG_SYS_FLASH_SIZE 0x800000 192 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 193 # define CONFIG_FLASH_CFI_LEGACY 194 #else 195 # define CONFIG_SYS_SST_SECT 2048 196 # define CONFIG_SYS_SST_SECTSZ 0x1000 197 # define CONFIG_SYS_FLASH_WRITE_TOUT 500 198 #endif 199 200 /* Cache Configuration */ 201 #define CONFIG_SYS_CACHELINE_SIZE 16 202 203 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 204 CONFIG_SYS_INIT_RAM_SIZE - 8) 205 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 206 CONFIG_SYS_INIT_RAM_SIZE - 4) 207 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 208 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 209 CF_ADDRMASK(8) | \ 210 CF_ACR_EN | CF_ACR_SM_ALL) 211 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 212 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 213 CF_ACR_EN | CF_ACR_SM_ALL) 214 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 215 CF_CACR_DBWE) 216 217 /* Port configuration */ 218 #define CONFIG_SYS_FECI2C 0xF0 219 220 #define CONFIG_SYS_CS0_BASE 0xFF800000 221 #define CONFIG_SYS_CS0_MASK 0x007F0021 222 #define CONFIG_SYS_CS0_CTRL 0x00001D80 223 224 #define CONFIG_SYS_CS1_BASE 0xE0000000 225 #define CONFIG_SYS_CS1_MASK 0x00000001 226 #define CONFIG_SYS_CS1_CTRL 0x00003DD8 227 228 /*----------------------------------------------------------------------- 229 * Port configuration 230 */ 231 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 232 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 233 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 234 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 235 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 236 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 237 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 238 239 #endif /* _M5253DEMO_H */ 240