xref: /rk3399_rockchip-uboot/include/configs/M5253DEMO.h (revision ac265f7fcab1a09b9a837a34ef8b10acc101695e)
16d33c6acSTsiChung Liew /*
26d33c6acSTsiChung Liew  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
36d33c6acSTsiChung Liew  * Hayden Fraser (Hayden.Fraser@freescale.com)
46d33c6acSTsiChung Liew  *
56d33c6acSTsiChung Liew  * See file CREDITS for list of people who contributed to this
66d33c6acSTsiChung Liew  * project.
76d33c6acSTsiChung Liew  *
86d33c6acSTsiChung Liew  * This program is free software; you can redistribute it and/or
96d33c6acSTsiChung Liew  * modify it under the terms of the GNU General Public License as
106d33c6acSTsiChung Liew  * published by the Free Software Foundation; either version 2 of
116d33c6acSTsiChung Liew  * the License, or (at your option) any later version.
126d33c6acSTsiChung Liew  *
136d33c6acSTsiChung Liew  * This program is distributed in the hope that it will be useful,
146d33c6acSTsiChung Liew  * but WITHOUT ANY WARRANTY; without even the implied warranty of
156d33c6acSTsiChung Liew  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
166d33c6acSTsiChung Liew  * GNU General Public License for more details.
176d33c6acSTsiChung Liew  *
186d33c6acSTsiChung Liew  * You should have received a copy of the GNU General Public License
196d33c6acSTsiChung Liew  * along with this program; if not, write to the Free Software
206d33c6acSTsiChung Liew  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
216d33c6acSTsiChung Liew  * MA 02111-1307 USA
226d33c6acSTsiChung Liew  */
236d33c6acSTsiChung Liew 
246d33c6acSTsiChung Liew #ifndef _M5253DEMO_H
256d33c6acSTsiChung Liew #define _M5253DEMO_H
266d33c6acSTsiChung Liew 
276d33c6acSTsiChung Liew #define CONFIG_MCF52x2		/* define processor family */
286d33c6acSTsiChung Liew #define CONFIG_M5253		/* define processor type */
296d33c6acSTsiChung Liew #define CONFIG_M5253DEMO	/* define board type */
306d33c6acSTsiChung Liew 
316d33c6acSTsiChung Liew #define CONFIG_MCFTMR
326d33c6acSTsiChung Liew 
336d33c6acSTsiChung Liew #define CONFIG_MCFUART
346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_UART_PORT		(0)
356d33c6acSTsiChung Liew #define CONFIG_BAUDRATE		115200
366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
376d33c6acSTsiChung Liew 
386d33c6acSTsiChung Liew #undef CONFIG_WATCHDOG		/* disable watchdog */
396d33c6acSTsiChung Liew 
406d33c6acSTsiChung Liew #define CONFIG_BOOTDELAY	5
416d33c6acSTsiChung Liew 
426d33c6acSTsiChung Liew /* Configuration for environment
436d33c6acSTsiChung Liew  * Environment is embedded in u-boot in the second sector of the flash
446d33c6acSTsiChung Liew  */
456d33c6acSTsiChung Liew #ifdef CONFIG_MONITOR_IS_IN_RAM
460e8d1586SJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_ENV_OFFSET		0x4000
470e8d1586SJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_ENV_SECT_SIZE	0x1000
485a1aceb0SJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_ENV_IS_IN_FLASH	1
496d33c6acSTsiChung Liew #else
506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
510e8d1586SJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_ENV_SECT_SIZE	0x1000
525a1aceb0SJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_ENV_IS_IN_FLASH	1
536d33c6acSTsiChung Liew #endif
546d33c6acSTsiChung Liew 
556d33c6acSTsiChung Liew /*
566d33c6acSTsiChung Liew  * Command line configuration.
576d33c6acSTsiChung Liew  */
586d33c6acSTsiChung Liew #include <config_cmd_default.h>
596d33c6acSTsiChung Liew 
606d33c6acSTsiChung Liew #define CONFIG_CMD_LOADB
616d33c6acSTsiChung Liew #define CONFIG_CMD_LOADS
626d33c6acSTsiChung Liew #define CONFIG_CMD_EXT2
636d33c6acSTsiChung Liew #define CONFIG_CMD_FAT
646d33c6acSTsiChung Liew #define CONFIG_CMD_IDE
656d33c6acSTsiChung Liew #define CONFIG_CMD_MEMORY
666d33c6acSTsiChung Liew #define CONFIG_CMD_MISC
676d33c6acSTsiChung Liew #define CONFIG_CMD_PING
686d33c6acSTsiChung Liew 
696d33c6acSTsiChung Liew #ifdef CONFIG_CMD_IDE
706d33c6acSTsiChung Liew /* ATA */
716d33c6acSTsiChung Liew #	define CONFIG_DOS_PARTITION
726d33c6acSTsiChung Liew #	define CONFIG_MAC_PARTITION
736d33c6acSTsiChung Liew #	define CONFIG_IDE_RESET		1
746d33c6acSTsiChung Liew #	define CONFIG_IDE_PREINIT	1
756d33c6acSTsiChung Liew #	define CONFIG_ATAPI
766d33c6acSTsiChung Liew #	undef CONFIG_LBA48
776d33c6acSTsiChung Liew 
786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_IDE_MAXBUS		1
796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_IDE_MAXDEVICE	2
806d33c6acSTsiChung Liew 
816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_ATA_IDE0_OFFSET	0
836d33c6acSTsiChung Liew 
846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */
886d33c6acSTsiChung Liew #endif
896d33c6acSTsiChung Liew 
9060f61e6dSRemy Bohmer #define CONFIG_NET_MULTI		1
916d33c6acSTsiChung Liew #define CONFIG_DRIVER_DM9000
926d33c6acSTsiChung Liew #ifdef CONFIG_DRIVER_DM9000
93012522feSTsiChung Liew #	define CONFIG_DM9000_BASE	(CONFIG_SYS_CS1_BASE | 0x300)
946d33c6acSTsiChung Liew #	define DM9000_IO		CONFIG_DM9000_BASE
956d33c6acSTsiChung Liew #	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
966d33c6acSTsiChung Liew #	undef CONFIG_DM9000_DEBUG
976d33c6acSTsiChung Liew 
986d33c6acSTsiChung Liew #	define CONFIG_OVERWRITE_ETHADDR_ONCE
996d33c6acSTsiChung Liew 
1006d33c6acSTsiChung Liew #	define CONFIG_EXTRA_ENV_SETTINGS		\
1016d33c6acSTsiChung Liew 		"netdev=eth0\0"				\
1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 		"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
1036d33c6acSTsiChung Liew 		"loadaddr=10000\0"			\
1046d33c6acSTsiChung Liew 		"u-boot=u-boot.bin\0"			\
1056d33c6acSTsiChung Liew 		"load=tftp ${loadaddr) ${u-boot}\0"	\
1066d33c6acSTsiChung Liew 		"upd=run load; run prog\0"		\
107*ac265f7fSTsiChung Liew 		"prog=prot off 0xff800000 0xff82ffff;"	\
108*ac265f7fSTsiChung Liew 		"era 0xff800000 0xff82ffff;"		\
1096d33c6acSTsiChung Liew 		"cp.b ${loadaddr} 0 ${filesize};"	\
1106d33c6acSTsiChung Liew 		"save\0"				\
1116d33c6acSTsiChung Liew 		""
1126d33c6acSTsiChung Liew #endif
1136d33c6acSTsiChung Liew 
1146d33c6acSTsiChung Liew #define CONFIG_HOSTNAME		M5253DEMO
1156d33c6acSTsiChung Liew 
116eec567a6STsiChung Liew /* I2C */
117eec567a6STsiChung Liew #define CONFIG_FSL_I2C
118eec567a6STsiChung Liew #define CONFIG_HARD_I2C		/* I2C with hw support */
1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED		80000
1206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE		0x7F
1216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET		0x00000280
1226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
1236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_PINMUX_REG	(*(u32 *) (CONFIG_SYS_MBAR+0x19C))
1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFFFE7FF)
1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_PINMUX_SET	(0)
126eec567a6STsiChung Liew 
1276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT		"=> "
1286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP		/* undef to save memory */
1296d33c6acSTsiChung Liew 
1306d33c6acSTsiChung Liew #if defined(CONFIG_CMD_KGDB)
1316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
1326d33c6acSTsiChung Liew #else
1336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
1346d33c6acSTsiChung Liew #endif
1356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
1366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
1376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
1386d33c6acSTsiChung Liew 
1396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR		0x00100000
1406d33c6acSTsiChung Liew 
1416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START	0x400
1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END		0x380000
1436d33c6acSTsiChung Liew 
1446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ			1000
1456d33c6acSTsiChung Liew 
1466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
1476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FAST_CLK
1486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_FAST_CLK
1496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_PLLCR	0x1243E054
1506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_CLK		140000000
1516d33c6acSTsiChung Liew #else
1526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_PLLCR	0x135a4140
1536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_CLK		70000000
1546d33c6acSTsiChung Liew #endif
1556d33c6acSTsiChung Liew 
1566d33c6acSTsiChung Liew /*
1576d33c6acSTsiChung Liew  * Low Level Configuration Settings
1586d33c6acSTsiChung Liew  * (address mappings, register initial values, etc.)
1596d33c6acSTsiChung Liew  * You should know what you are doing if you make changes here.
1606d33c6acSTsiChung Liew  */
1616d33c6acSTsiChung Liew 
1626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
1636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */
1646d33c6acSTsiChung Liew 
1656d33c6acSTsiChung Liew /*
1666d33c6acSTsiChung Liew  * Definitions for initial stack pointer and data area (in DPRAM)
1676d33c6acSTsiChung Liew  */
1686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
1696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
1706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
1716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
1726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
1736d33c6acSTsiChung Liew 
1746d33c6acSTsiChung Liew /*
1756d33c6acSTsiChung Liew  * Start addresses for the final memory configuration
1766d33c6acSTsiChung Liew  * (Set up by the startup code)
1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
1786d33c6acSTsiChung Liew  */
1796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE		0x00000000
1806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
1816d33c6acSTsiChung Liew 
1826d33c6acSTsiChung Liew #ifdef CONFIG_MONITOR_IS_IN_RAM
1836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_MONITOR_BASE	0x20000
1846d33c6acSTsiChung Liew #else
1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
1866d33c6acSTsiChung Liew #endif
1876d33c6acSTsiChung Liew 
1886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN		0x40000
1896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN		(256 << 10)
1906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)
1916d33c6acSTsiChung Liew 
1926d33c6acSTsiChung Liew /*
1936d33c6acSTsiChung Liew  * For booting Linux, the board info and command line data
1946d33c6acSTsiChung Liew  * have to be in the first 8 MB of memory, since this is
1956d33c6acSTsiChung Liew  * the maximum mapped by the Linux kernel during initialization ??
1966d33c6acSTsiChung Liew  */
1976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
198d6e4baf4STsiChung Liew #define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
1996d33c6acSTsiChung Liew 
2006d33c6acSTsiChung Liew /* FLASH organization */
201012522feSTsiChung Liew #define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
2046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT	1000
2056d33c6acSTsiChung Liew 
2066d33c6acSTsiChung Liew #define FLASH_SST6401B		0x200
2076d33c6acSTsiChung Liew #define SST_ID_xF6401B		0x236D236D
2086d33c6acSTsiChung Liew 
2096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CFI
2106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_FLASH_CFI
2116d33c6acSTsiChung Liew /*
2126d33c6acSTsiChung Liew  * Unable to use CFI driver, due to incompatible sector erase command by SST.
2136d33c6acSTsiChung Liew  * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
2146d33c6acSTsiChung Liew  * 0x30 is block erase in SST
2156d33c6acSTsiChung Liew  */
2160de0afbcSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_FLASH_CFI_DRIVER	1
2176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_FLASH_SIZE		0x800000
2186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
2196d33c6acSTsiChung Liew #	define CONFIG_FLASH_CFI_LEGACY
2206d33c6acSTsiChung Liew #else
2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_SST_SECT		2048
2226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_SST_SECTSZ		0x1000
2236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #	define CONFIG_SYS_FLASH_WRITE_TOUT	500
2246d33c6acSTsiChung Liew #endif
2256d33c6acSTsiChung Liew 
2266d33c6acSTsiChung Liew /* Cache Configuration */
2276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CACHELINE_SIZE	16
2286d33c6acSTsiChung Liew 
2296d33c6acSTsiChung Liew /* Port configuration */
2306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FECI2C		0xF0
2316d33c6acSTsiChung Liew 
232012522feSTsiChung Liew #define CONFIG_SYS_CS0_BASE		0xFF800000
233012522feSTsiChung Liew #define CONFIG_SYS_CS0_MASK		0x007F0021
234012522feSTsiChung Liew #define CONFIG_SYS_CS0_CTRL		0x00001D80
2356d33c6acSTsiChung Liew 
236012522feSTsiChung Liew #define CONFIG_SYS_CS1_BASE		0xE0000000
237012522feSTsiChung Liew #define CONFIG_SYS_CS1_MASK		0x00000001
238012522feSTsiChung Liew #define CONFIG_SYS_CS1_CTRL		0x00003DD8
2396d33c6acSTsiChung Liew 
2406d33c6acSTsiChung Liew /*-----------------------------------------------------------------------
2416d33c6acSTsiChung Liew  * Port configuration
2426d33c6acSTsiChung Liew  */
2436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
2446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
2456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
2466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
2476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
2486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
2496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */
2506d33c6acSTsiChung Liew 
2516d33c6acSTsiChung Liew #endif				/* _M5253DEMO_H */
252