16d33c6acSTsiChung Liew /* 26d33c6acSTsiChung Liew * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 36d33c6acSTsiChung Liew * Hayden Fraser (Hayden.Fraser@freescale.com) 46d33c6acSTsiChung Liew * 56d33c6acSTsiChung Liew * See file CREDITS for list of people who contributed to this 66d33c6acSTsiChung Liew * project. 76d33c6acSTsiChung Liew * 86d33c6acSTsiChung Liew * This program is free software; you can redistribute it and/or 96d33c6acSTsiChung Liew * modify it under the terms of the GNU General Public License as 106d33c6acSTsiChung Liew * published by the Free Software Foundation; either version 2 of 116d33c6acSTsiChung Liew * the License, or (at your option) any later version. 126d33c6acSTsiChung Liew * 136d33c6acSTsiChung Liew * This program is distributed in the hope that it will be useful, 146d33c6acSTsiChung Liew * but WITHOUT ANY WARRANTY; without even the implied warranty of 156d33c6acSTsiChung Liew * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 166d33c6acSTsiChung Liew * GNU General Public License for more details. 176d33c6acSTsiChung Liew * 186d33c6acSTsiChung Liew * You should have received a copy of the GNU General Public License 196d33c6acSTsiChung Liew * along with this program; if not, write to the Free Software 206d33c6acSTsiChung Liew * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 216d33c6acSTsiChung Liew * MA 02111-1307 USA 226d33c6acSTsiChung Liew */ 236d33c6acSTsiChung Liew 246d33c6acSTsiChung Liew #ifndef _M5253DEMO_H 256d33c6acSTsiChung Liew #define _M5253DEMO_H 266d33c6acSTsiChung Liew 276d33c6acSTsiChung Liew #define CONFIG_MCF52x2 /* define processor family */ 286d33c6acSTsiChung Liew #define CONFIG_M5253 /* define processor type */ 296d33c6acSTsiChung Liew #define CONFIG_M5253DEMO /* define board type */ 306d33c6acSTsiChung Liew 316d33c6acSTsiChung Liew #define CONFIG_MCFTMR 326d33c6acSTsiChung Liew 336d33c6acSTsiChung Liew #define CONFIG_MCFUART 34*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_UART_PORT (0) 356d33c6acSTsiChung Liew #define CONFIG_BAUDRATE 115200 36*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 376d33c6acSTsiChung Liew 386d33c6acSTsiChung Liew #undef CONFIG_WATCHDOG /* disable watchdog */ 396d33c6acSTsiChung Liew 406d33c6acSTsiChung Liew #define CONFIG_BOOTDELAY 5 416d33c6acSTsiChung Liew 426d33c6acSTsiChung Liew /* Configuration for environment 436d33c6acSTsiChung Liew * Environment is embedded in u-boot in the second sector of the flash 446d33c6acSTsiChung Liew */ 456d33c6acSTsiChung Liew #ifdef CONFIG_MONITOR_IS_IN_RAM 460e8d1586SJean-Christophe PLAGNIOL-VILLARD # define CONFIG_ENV_OFFSET 0x4000 470e8d1586SJean-Christophe PLAGNIOL-VILLARD # define CONFIG_ENV_SECT_SIZE 0x1000 485a1aceb0SJean-Christophe PLAGNIOL-VILLARD # define CONFIG_ENV_IS_IN_FLASH 1 496d33c6acSTsiChung Liew #else 50*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) 510e8d1586SJean-Christophe PLAGNIOL-VILLARD # define CONFIG_ENV_SECT_SIZE 0x1000 525a1aceb0SJean-Christophe PLAGNIOL-VILLARD # define CONFIG_ENV_IS_IN_FLASH 1 536d33c6acSTsiChung Liew #endif 546d33c6acSTsiChung Liew 556d33c6acSTsiChung Liew /* 566d33c6acSTsiChung Liew * Command line configuration. 576d33c6acSTsiChung Liew */ 586d33c6acSTsiChung Liew #include <config_cmd_default.h> 596d33c6acSTsiChung Liew 606d33c6acSTsiChung Liew #define CONFIG_CMD_LOADB 616d33c6acSTsiChung Liew #define CONFIG_CMD_LOADS 626d33c6acSTsiChung Liew #define CONFIG_CMD_EXT2 636d33c6acSTsiChung Liew #define CONFIG_CMD_FAT 646d33c6acSTsiChung Liew #define CONFIG_CMD_IDE 656d33c6acSTsiChung Liew #define CONFIG_CMD_MEMORY 666d33c6acSTsiChung Liew #define CONFIG_CMD_MISC 676d33c6acSTsiChung Liew #define CONFIG_CMD_PING 686d33c6acSTsiChung Liew 696d33c6acSTsiChung Liew #ifdef CONFIG_CMD_IDE 706d33c6acSTsiChung Liew /* ATA */ 716d33c6acSTsiChung Liew # define CONFIG_DOS_PARTITION 726d33c6acSTsiChung Liew # define CONFIG_MAC_PARTITION 736d33c6acSTsiChung Liew # define CONFIG_IDE_RESET 1 746d33c6acSTsiChung Liew # define CONFIG_IDE_PREINIT 1 756d33c6acSTsiChung Liew # define CONFIG_ATAPI 766d33c6acSTsiChung Liew # undef CONFIG_LBA48 776d33c6acSTsiChung Liew 78*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_IDE_MAXBUS 1 79*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_IDE_MAXDEVICE 2 806d33c6acSTsiChung Liew 81*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 82*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_ATA_IDE0_OFFSET 0 836d33c6acSTsiChung Liew 84*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 85*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 86*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 87*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 886d33c6acSTsiChung Liew # define _IO_BASE 0 896d33c6acSTsiChung Liew #endif 906d33c6acSTsiChung Liew 916d33c6acSTsiChung Liew #define CONFIG_DRIVER_DM9000 926d33c6acSTsiChung Liew #ifdef CONFIG_DRIVER_DM9000 93*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_DM9000_BASE ((CONFIG_SYS_CSAR1 << 16) | 0x300) 946d33c6acSTsiChung Liew # define DM9000_IO CONFIG_DM9000_BASE 956d33c6acSTsiChung Liew # define DM9000_DATA (CONFIG_DM9000_BASE + 4) 966d33c6acSTsiChung Liew # undef CONFIG_DM9000_DEBUG 976d33c6acSTsiChung Liew 986d33c6acSTsiChung Liew # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 996d33c6acSTsiChung Liew # define CONFIG_IPADDR 10.82.121.249 1006d33c6acSTsiChung Liew # define CONFIG_NETMASK 255.255.252.0 1016d33c6acSTsiChung Liew # define CONFIG_SERVERIP 10.82.120.80 1026d33c6acSTsiChung Liew # define CONFIG_GATEWAYIP 10.82.123.254 1036d33c6acSTsiChung Liew # define CONFIG_OVERWRITE_ETHADDR_ONCE 1046d33c6acSTsiChung Liew 1056d33c6acSTsiChung Liew # define CONFIG_EXTRA_ENV_SETTINGS \ 1066d33c6acSTsiChung Liew "netdev=eth0\0" \ 107*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 1086d33c6acSTsiChung Liew "loadaddr=10000\0" \ 1096d33c6acSTsiChung Liew "u-boot=u-boot.bin\0" \ 1106d33c6acSTsiChung Liew "load=tftp ${loadaddr) ${u-boot}\0" \ 1116d33c6acSTsiChung Liew "upd=run load; run prog\0" \ 1126d33c6acSTsiChung Liew "prog=prot off 0 2ffff;" \ 1136d33c6acSTsiChung Liew "era 0 2ffff;" \ 1146d33c6acSTsiChung Liew "cp.b ${loadaddr} 0 ${filesize};" \ 1156d33c6acSTsiChung Liew "save\0" \ 1166d33c6acSTsiChung Liew "" 1176d33c6acSTsiChung Liew #endif 1186d33c6acSTsiChung Liew 1196d33c6acSTsiChung Liew #define CONFIG_HOSTNAME M5253DEMO 1206d33c6acSTsiChung Liew 121eec567a6STsiChung Liew /* I2C */ 122eec567a6STsiChung Liew #define CONFIG_FSL_I2C 123eec567a6STsiChung Liew #define CONFIG_HARD_I2C /* I2C with hw support */ 124*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 80000 125*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 126*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x00000280 127*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 128*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) 129*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) 130*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_PINMUX_SET (0) 131eec567a6STsiChung Liew 132*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " 133*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 1346d33c6acSTsiChung Liew 1356d33c6acSTsiChung Liew #if defined(CONFIG_CMD_KGDB) 136*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 1376d33c6acSTsiChung Liew #else 138*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 1396d33c6acSTsiChung Liew #endif 140*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 141*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 142*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 1436d33c6acSTsiChung Liew 144*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x00100000 1456d33c6acSTsiChung Liew 146*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x400 147*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x380000 1486d33c6acSTsiChung Liew 149*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 1506d33c6acSTsiChung Liew 151*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 152*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FAST_CLK 153*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_FAST_CLK 154*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_PLLCR 0x1243E054 155*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_CLK 140000000 1566d33c6acSTsiChung Liew #else 157*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_PLLCR 0x135a4140 158*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_CLK 70000000 1596d33c6acSTsiChung Liew #endif 1606d33c6acSTsiChung Liew 1616d33c6acSTsiChung Liew /* 1626d33c6acSTsiChung Liew * Low Level Configuration Settings 1636d33c6acSTsiChung Liew * (address mappings, register initial values, etc.) 1646d33c6acSTsiChung Liew * You should know what you are doing if you make changes here. 1656d33c6acSTsiChung Liew */ 1666d33c6acSTsiChung Liew 167*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 168*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 1696d33c6acSTsiChung Liew 1706d33c6acSTsiChung Liew /* 1716d33c6acSTsiChung Liew * Definitions for initial stack pointer and data area (in DPRAM) 1726d33c6acSTsiChung Liew */ 173*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 174*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ 175*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 176*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 177*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 1786d33c6acSTsiChung Liew 1796d33c6acSTsiChung Liew /* 1806d33c6acSTsiChung Liew * Start addresses for the final memory configuration 1816d33c6acSTsiChung Liew * (Set up by the startup code) 182*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 1836d33c6acSTsiChung Liew */ 184*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE 0x00000000 185*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 1866d33c6acSTsiChung Liew 1876d33c6acSTsiChung Liew #ifdef CONFIG_MONITOR_IS_IN_RAM 188*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_MONITOR_BASE 0x20000 1896d33c6acSTsiChung Liew #else 190*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 1916d33c6acSTsiChung Liew #endif 1926d33c6acSTsiChung Liew 193*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN 0x40000 194*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (256 << 10) 195*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 1966d33c6acSTsiChung Liew 1976d33c6acSTsiChung Liew /* 1986d33c6acSTsiChung Liew * For booting Linux, the board info and command line data 1996d33c6acSTsiChung Liew * have to be in the first 8 MB of memory, since this is 2006d33c6acSTsiChung Liew * the maximum mapped by the Linux kernel during initialization ?? 2016d33c6acSTsiChung Liew */ 202*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 2036d33c6acSTsiChung Liew 2046d33c6acSTsiChung Liew /* FLASH organization */ 205*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CSAR0 << 16) 206*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 207*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ 208*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 2096d33c6acSTsiChung Liew 2106d33c6acSTsiChung Liew #define FLASH_SST6401B 0x200 2116d33c6acSTsiChung Liew #define SST_ID_xF6401B 0x236D236D 2126d33c6acSTsiChung Liew 213*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CFI 214*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_FLASH_CFI 2156d33c6acSTsiChung Liew /* 2166d33c6acSTsiChung Liew * Unable to use CFI driver, due to incompatible sector erase command by SST. 2176d33c6acSTsiChung Liew * Amd/Atmel use 0x30 for sector erase, SST use 0x50. 2186d33c6acSTsiChung Liew * 0x30 is block erase in SST 2196d33c6acSTsiChung Liew */ 2200de0afbcSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_FLASH_CFI_DRIVER 1 221*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_FLASH_SIZE 0x800000 222*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 2236d33c6acSTsiChung Liew # define CONFIG_FLASH_CFI_LEGACY 2246d33c6acSTsiChung Liew #else 225*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_SST_SECT 2048 226*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_SST_SECTSZ 0x1000 227*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_FLASH_WRITE_TOUT 500 2286d33c6acSTsiChung Liew #endif 2296d33c6acSTsiChung Liew 2306d33c6acSTsiChung Liew /* Cache Configuration */ 231*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CACHELINE_SIZE 16 2326d33c6acSTsiChung Liew 2336d33c6acSTsiChung Liew /* Port configuration */ 234*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FECI2C 0xF0 2356d33c6acSTsiChung Liew 236*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CSAR0 0xFF80 237*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CSMR0 0x007F0021 238*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CSCR0 0x1D80 2396d33c6acSTsiChung Liew 240*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CSAR1 0xE000 241*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CSMR1 0x00000001 242*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CSCR1 0x3DD8 2436d33c6acSTsiChung Liew 244*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CSAR2 0 245*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CSMR2 0 246*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CSCR2 0 2476d33c6acSTsiChung Liew 248*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CSAR3 0 249*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CSMR3 0 250*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CSCR3 0 2516d33c6acSTsiChung Liew 2526d33c6acSTsiChung Liew /*----------------------------------------------------------------------- 2536d33c6acSTsiChung Liew * Port configuration 2546d33c6acSTsiChung Liew */ 255*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 256*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 257*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 258*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 259*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 260*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 261*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 2626d33c6acSTsiChung Liew 2636d33c6acSTsiChung Liew #endif /* _M5253DEMO_H */ 264